/*
 * Copyright (c) 2015 Petr Pavlu
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/** @addtogroup kernel_arm64
 * @{
 */
/** @file
 * @brief Memory barriers.
 */

#ifndef KERN_arm64_BARRIER_H_
#define KERN_arm64_BARRIER_H_

#include <stddef.h>

#define COHERENCE_INVAL_MIN  4

/** Ensure visibility of instruction updates for a multiprocessor.
 *
 * @param addr Address of the first instruction.
 * @param size Size of the instruction block (in bytes).
 */
static inline void ensure_visibility(void *addr, size_t len)
{
	size_t i;

	/*
	 * Clean to Point of Unification to make the new instructions visible to
	 * the instruction cache.
	 */
	for (i = 0; i < len; i += COHERENCE_INVAL_MIN)
		asm volatile (
		    "dc cvau, %[addr]\n"
		    : : [addr] "r" ((char *) addr + i)
		);

	/* Ensure completion on all PEs. */
	asm volatile ("dsb ish" ::: "memory");

	/* Ensure instruction cache/branch predictor discards stale data. */
	for (i = 0; i < len; i += COHERENCE_INVAL_MIN)
		asm volatile (
		    "ic ivau, %[addr]\n"
		    : : [addr] "r" ((char *) addr + i)
		);

	/* Ensure completion on all PEs. */
	asm volatile ("dsb ish" ::: "memory");

	/* Synchronize context on this PE. */
	asm volatile ("isb");
}

#endif

/** @}
 */
