Index: kernel/arch/ia32xen/include/mm/page.h
===================================================================
--- kernel/arch/ia32xen/include/mm/page.h	(revision 6b781c0c856d94b3114ccd6375bc6667a19e9bfe)
+++ kernel/arch/ia32xen/include/mm/page.h	(revision de7663fb0ae74743dc4eb0f110341bf66804710f)
@@ -57,4 +57,6 @@
  * IA-32 has 2-level page tables, so PTL1 and PTL2 are left out.
  */
+
+/* Number of entries in each level. */
 #define PTL0_ENTRIES_ARCH	1024
 #define PTL1_ENTRIES_ARCH	0
@@ -62,9 +64,11 @@
 #define PTL3_ENTRIES_ARCH	1024
 
-#define PTL0_SIZE_ARCH       ONE_FRAME
-#define PTL1_SIZE_ARCH       0
-#define PTL2_SIZE_ARCH       0
-#define PTL3_SIZE_ARCH       ONE_FRAME
-
+/* Page table size for each level. */
+#define PTL0_SIZE_ARCH		ONE_FRAME
+#define PTL1_SIZE_ARCH		0
+#define PTL2_SIZE_ARCH		0
+#define PTL3_SIZE_ARCH		ONE_FRAME
+
+/* Macros calculating indices into page tables in each level. */
 #define PTL0_INDEX_ARCH(vaddr)	(((vaddr) >> 22) & 0x3ff)
 #define PTL1_INDEX_ARCH(vaddr)	0
@@ -72,10 +76,17 @@
 #define PTL3_INDEX_ARCH(vaddr)	(((vaddr) >> 12) & 0x3ff)
 
-#define GET_PTL1_ADDRESS_ARCH(ptl0, i)		((pte_t *) MA2PA((((pte_t *) (ptl0))[(i)].frame_address) << 12))
-#define GET_PTL2_ADDRESS_ARCH(ptl1, i)		(ptl1)
-#define GET_PTL3_ADDRESS_ARCH(ptl2, i)		(ptl2)
-#define GET_FRAME_ADDRESS_ARCH(ptl3, i)		((uintptr_t) MA2PA((((pte_t *) (ptl3))[(i)].frame_address) << 12))
-
-#define SET_PTL0_ADDRESS_ARCH(ptl0) { \
+/* Get PTE address accessors for each level. */
+#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
+	((pte_t *) MA2PA((((pte_t *) (ptl0))[(i)].frame_address) << 12))
+#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
+	(ptl1)
+#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
+	(ptl2)
+#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
+	((uintptr_t) MA2PA((((pte_t *) (ptl3))[(i)].frame_address) << 12))
+
+/* Set PTE address accessors for each level. */
+#define SET_PTL0_ADDRESS_ARCH(ptl0) \
+{ \
 	mmuext_op_t mmu_ext; \
 	\
@@ -85,5 +96,6 @@
 }
 
-#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) { \
+#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
+{ \
 	mmuext_op_t mmu_ext; \
 	\
@@ -101,5 +113,6 @@
 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
-#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) { \
+#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
+{ \
 	mmu_update_t update; \
 	\
@@ -109,19 +122,33 @@
 }
 
-#define GET_PTL1_FLAGS_ARCH(ptl0, i)		get_pt_flags((pte_t *) (ptl0), (index_t)(i))
-#define GET_PTL2_FLAGS_ARCH(ptl1, i)		PAGE_PRESENT
-#define GET_PTL3_FLAGS_ARCH(ptl2, i)		PAGE_PRESENT
-#define GET_FRAME_FLAGS_ARCH(ptl3, i)		get_pt_flags((pte_t *) (ptl3), (index_t)(i))
-
-#define SET_PTL1_FLAGS_ARCH(ptl0, i, x)		set_pt_flags((pte_t *) (ptl0), (index_t)(i), (x))
+/* Get PTE flags accessors for each level. */
+#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
+	get_pt_flags((pte_t *) (ptl0), (index_t) (i))
+#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
+	PAGE_PRESENT
+#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
+	PAGE_PRESENT
+#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
+	get_pt_flags((pte_t *) (ptl3), (index_t) (i))
+
+/* Set PTE flags accessors for each level. */
+#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
+	set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
 #define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
 #define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
-#define SET_FRAME_FLAGS_ARCH(ptl3, i, x)		set_pt_flags((pte_t *) (ptl3), (index_t)(i), (x))
-
-#define PTE_VALID_ARCH(p)			(*((uint32_t *) (p)) != 0)
-#define PTE_PRESENT_ARCH(p)			((p)->present != 0)
-#define PTE_GET_FRAME_ARCH(p)			((p)->frame_address << FRAME_WIDTH)
-#define PTE_WRITABLE_ARCH(p)			((p)->writeable != 0)
-#define PTE_EXECUTABLE_ARCH(p)			1
+#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
+	set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
+
+/* Query macros for the last level. */
+#define PTE_VALID_ARCH(p) \
+	(*((uint32_t *) (p)) != 0)
+#define PTE_PRESENT_ARCH(p) \
+	((p)->present != 0)
+#define PTE_GET_FRAME_ARCH(p) \
+	((p)->frame_address << FRAME_WIDTH)
+#define PTE_WRITABLE_ARCH(p) \
+	((p)->writeable != 0)
+#define PTE_EXECUTABLE_ARCH(p) \
+	1
 
 #ifndef __ASM__
@@ -133,5 +160,7 @@
 /* Page fault error codes. */
 
-/** When bit on this position is 0, the page fault was caused by a not-present page. */
+/** When bit on this position is 0, the page fault was caused by a not-present
+ * page.
+ */
 #define PFERR_CODE_P		(1 << 0)
 
@@ -165,15 +194,18 @@
 } mmuext_op_t;
 
-static inline int xen_update_va_mapping(const void *va, const pte_t pte, const unsigned int flags)
+static inline int xen_update_va_mapping(const void *va, const pte_t pte,
+    const unsigned int flags)
 {
 	return hypercall4(XEN_UPDATE_VA_MAPPING, va, pte, 0, flags);
 }
 
-static inline int xen_mmu_update(const mmu_update_t *req, const unsigned int count, unsigned int *success_count, domid_t domid)
+static inline int xen_mmu_update(const mmu_update_t *req,
+    const unsigned int count, unsigned int *success_count, domid_t domid)
 {
 	return hypercall4(XEN_MMU_UPDATE, req, count, success_count, domid);
 }
 
-static inline int xen_mmuext_op(const mmuext_op_t *op, const unsigned int count, unsigned int *success_count, domid_t domid)
+static inline int xen_mmuext_op(const mmuext_op_t *op, const unsigned int count,
+    unsigned int *success_count, domid_t domid)
 {
 	return hypercall4(XEN_MMUEXT_OP, op, count, success_count, domid);
@@ -184,13 +216,11 @@
 	pte_t *p = &pt[i];
 	
-	return (
-		(!p->page_cache_disable)<<PAGE_CACHEABLE_SHIFT |
-		(!p->present)<<PAGE_PRESENT_SHIFT |
-		p->uaccessible<<PAGE_USER_SHIFT |
-		1<<PAGE_READ_SHIFT |
-		p->writeable<<PAGE_WRITE_SHIFT |
-		1<<PAGE_EXEC_SHIFT |
-		p->global<<PAGE_GLOBAL_SHIFT
-	);
+	return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT |
+	    (!p->present) << PAGE_PRESENT_SHIFT |
+	    p->uaccessible << PAGE_USER_SHIFT |
+	    1 << PAGE_READ_SHIFT |
+	    p->writeable << PAGE_WRITE_SHIFT |
+	    1 << PAGE_EXEC_SHIFT |
+	    p->global << PAGE_GLOBAL_SHIFT);
 }