Index: kernel/arch/arm32/Makefile.inc =================================================================== --- kernel/arch/arm32/Makefile.inc (revision 664fd6d5f9d3f54ffaa4804f8384c9a6e018bd39) +++ kernel/arch/arm32/Makefile.inc (revision de36fdd14b85a7e8805af1d78bcc5cb399e15335) @@ -38,5 +38,5 @@ # This is necessary to allow vmsr insn and fpexc manipulation # Use vfp32 to allow context save/restore of d16-d31 regs. -GCC_CFLAGS += -mfloat-abi=hard -mfpu=vfp3 +AFLAGS += -mfloat-abi=hard -mfpu=vfp3 endif @@ -70,4 +70,5 @@ ifeq ($(CONFIG_FPU),y) ARCH_SOURCES += arch/$(KARCH)/src/fpu_context.c + ARCH_SOURCES += arch/$(KARCH)/src/fpu.s endif Index: kernel/arch/arm32/src/fpu.s =================================================================== --- kernel/arch/arm32/src/fpu.s (revision de36fdd14b85a7e8805af1d78bcc5cb399e15335) +++ kernel/arch/arm32/src/fpu.s (revision de36fdd14b85a7e8805af1d78bcc5cb399e15335) @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2013 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +.text + +.global fpsid_read +.global mvfr0_read +.global fpscr_read +.global fpscr_write +.global fpexc_read +.global fpexc_write + +.global fpu_context_save_s32 +.global fpu_context_restore_s32 +.global fpu_context_save_d16 +.global fpu_context_restore_d16 +.global fpu_context_save_d32 +.global fpu_context_restore_d32 + +fpsid_read: + vmrs r0, fpsid + mov pc, lr + +mvfr0_read: + vmrs r0, mvfr0 + mov pc, lr + +fpscr_read: + vmrs r0, fpscr + mov pc, lr + +fpscr_write: + vmsr fpscr, r0 + mov pc, lr + +fpexc_read: + vmrs r0, fpexc + mov pc, lr + +fpexc_write: + vmsr fpexc, r0 + mov pc, lr + +fpu_context_save_s32: + vmrs r1, fpexc + vmrs r2, fpscr + stmia r0!, {r1, r2} + vstmia r0!, {s0-s31} + mov pc, lr + +fpu_context_restore_s32: + ldmia r0!, {r1, r2} + vmsr fpexc, r1 + vmsr fpscr, r2 + vldmia r0!, {s0-s31} + mov pc, lr + +fpu_context_save_d16: + vmrs r1, fpexc + vmrs r2, fpscr + stmia r0!, {r1, r2} + vstmia r0!, {d0-d15} + mov pc, lr + +fpu_context_restore_d16: + ldmia r0!, {r1, r2} + vmsr fpexc, r1 + vmsr fpscr, r2 + vldmia r0!, {d0-d15} + mov pc, lr + +fpu_context_save_d32: + vmrs r1, fpexc + stmia r0!, {r1} + vmrs r1, fpscr + stmia r0!, {r1} + vstmia r0!, {d0-d15} + vstmia r0!, {d16-d31} + mov pc, lr + +fpu_context_restore_d32: + ldmia r0!, {r1, r2} + vmsr fpexc, r1 + vmsr fpscr, r2 + vldmia r0!, {d0-d15} + vldmia r0!, {d16-d31} + mov pc, lr + + + Index: kernel/arch/arm32/src/fpu_context.c =================================================================== --- kernel/arch/arm32/src/fpu_context.c (revision 664fd6d5f9d3f54ffaa4804f8384c9a6e018bd39) +++ kernel/arch/arm32/src/fpu_context.c (revision de36fdd14b85a7e8805af1d78bcc5cb399e15335) @@ -103,136 +103,20 @@ }; -static inline uint32_t fpscr_read() -{ - uint32_t reg; - asm volatile ( - "vmrs %0, fpscr\n" - :"=r" (reg):: - ); - return reg; -} - -static inline void fpscr_write(uint32_t val) -{ - asm volatile ( - "vmsr fpscr, %0\n" - ::"r" (val): - ); -} - -static inline uint32_t fpexc_read() -{ - uint32_t reg; - asm volatile ( - "vmrs %0, fpexc\n" - :"=r" (reg):: - ); - return reg; -} - -static inline void fpexc_write(uint32_t val) -{ - asm volatile ( - "vmsr fpexc, %0\n" - ::"r" (val): - ); -} +extern uint32_t fpsid_read(void); +extern uint32_t mvfr0_read(void); +extern uint32_t fpscr_read(void); +extern void fpscr_write(uint32_t); +extern uint32_t fpexc_read(void); +extern void fpexc_write(uint32_t); + +extern void fpu_context_save_s32(fpu_context_t *); +extern void fpu_context_restore_s32(fpu_context_t *); +extern void fpu_context_save_d16(fpu_context_t *); +extern void fpu_context_restore_d16(fpu_context_t *); +extern void fpu_context_save_d32(fpu_context_t *); +extern void fpu_context_restore_d32(fpu_context_t *); static void (*save_context)(fpu_context_t *ctx); static void (*restore_context)(fpu_context_t *ctx); - -/** Saves 32 single precision fpu registers. - * @param ctx FPU context area. - * Used by VFPv1 - */ -static void fpu_context_save_s32(fpu_context_t *ctx) -{ - asm volatile ( - "vmrs r1, fpexc\n" - "vmrs r2, fpscr\n" - "stmia %0!, {r1, r2}\n" - "vstmia %0!, {s0-s31}\n" - ::"r" (ctx): "r1","r2","memory" - ); -} - -/** Restores 32 single precision fpu registers. - * @param ctx FPU context area. - * Used by VFPv1 - */ -static void fpu_context_restore_s32(fpu_context_t *ctx) -{ - asm volatile ( - "ldmia %0!, {r1, r2}\n" - "vmsr fpexc, r1\n" - "vmsr fpscr, r2\n" - "vldmia %0!, {s0-s31}\n" - ::"r" (ctx): "r1","r2" - ); -} - -/** Saves 16 double precision fpu registers. - * @param ctx FPU context area. - * Used by VFPv2, VFPv3-d16, and VFPv4-d16. - */ -static void fpu_context_save_d16(fpu_context_t *ctx) -{ - asm volatile ( - "vmrs r1, fpexc\n" - "vmrs r2, fpscr\n" - "stmia %0!, {r1, r2}\n" - "vstmia %0!, {d0-d15}\n" - ::"r" (ctx): "r1","r2","memory" - ); -} - -/** Restores 16 double precision fpu registers. - * @param ctx FPU context area. - * Used by VFPv2, VFPv3-d16, and VFPv4-d16. - */ -static void fpu_context_restore_d16(fpu_context_t *ctx) -{ - asm volatile ( - "ldmia %0!, {r1, r2}\n" - "vmsr fpexc, r1\n" - "vmsr fpscr, r2\n" - "vldmia %0!, {d0-d15}\n" - ::"r" (ctx): "r1","r2" - ); -} - -/** Saves 32 double precision fpu registers. - * @param ctx FPU context area. - * Used by VFPv3-d32, VFPv4-d32, and advanced SIMD. - */ -static void fpu_context_save_d32(fpu_context_t *ctx) -{ - asm volatile ( - "vmrs r1, fpexc\n" - "stmia %0!, {r1}\n" - "vmrs r1, fpscr\n" - "stmia %0!, {r1}\n" - "vstmia %0!, {d0-d15}\n" - "vstmia %0!, {d16-d31}\n" - ::"r" (ctx): "r1","memory" - ); -} - -/** Restores 32 double precision fpu registers. - * @param ctx FPU context area. - * Used by VFPv3-d32, VFPv4-d32, and advanced SIMD. - */ -static void fpu_context_restore_d32(fpu_context_t *ctx) -{ - asm volatile ( - "ldmia %0!, {r1}\n" - "vmsr fpexc, r1\n" - "ldmia %0!, {r1}\n" - "vmsr fpscr, r1\n" - "vldmia %0!, {d0-d15}\n" - "vldmia %0!, {d16-d31}\n" - ::"r" (ctx): "r1" - ); -} static int fpu_have_coprocessor_access() @@ -285,9 +169,5 @@ return; - uint32_t fpsid = 0; - asm volatile ( - "vmrs %0, fpsid\n" - :"=r"(fpsid):: - ); + const uint32_t fpsid = fpsid_read(); if (fpsid & FPSID_SW_ONLY_FLAG) { printf("No FPU avaiable\n"); @@ -309,9 +189,5 @@ case FPU_VFPv3_NO_COMMON: case FPU_VFPv3_COMMONv3: { - uint32_t mvfr0 = 0; - asm volatile ( - "vmrs %0,mvfr0\n" - :"=r"(mvfr0):: - ); + const uint32_t mvfr0 = mvfr0_read(); /* See page B4-1637 */ if ((mvfr0 & 0xf) == 0x1) {