Changeset de36fdd in mainline

Timestamp:

2013-01-06T19:52:43Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

b4b3a4cb

Parents:

664fd6d5

Message:

arm32: Move fpu handling code to .s file.

restrict kernel fpu instructions to asm files.

Location:

kernel/arch/arm32

Files:

• Makefile.inc (modified) (2 diffs)
• src/fpu.s (added)
• src/fpu_context.c (modified) (3 diffs)

kernel/arch/arm32/Makefile.inc

@@ -38 +38 @@
 # This is necessary to allow vmsr insn and fpexc manipulation
 # Use vfp32 to allow context save/restore of d16-d31 regs.
-GCC_CFLAGS += -mfloat-abi=hard -mfpu=vfp3
+AFLAGS += -mfloat-abi=hard -mfpu=vfp3
 endif
 
@@ -70 +70 @@
 ifeq ($(CONFIG_FPU),y)
         ARCH_SOURCES += arch/$(KARCH)/src/fpu_context.c
+        ARCH_SOURCES += arch/$(KARCH)/src/fpu.s
 endif
 

kernel/arch/arm32/src/fpu_context.c

@@ -103 +103 @@
 };
 
-static inline uint32_t fpscr_read()
-{
-        uint32_t reg;
-        asm volatile (
-                "vmrs %0, fpscr\n"
-                :"=r" (reg)::
-        );
-        return reg;
-}
-
-static inline void fpscr_write(uint32_t val)
-{
-        asm volatile (
-                "vmsr fpscr, %0\n"
-                ::"r" (val):
-        );
-}
-
-static inline uint32_t fpexc_read()
-{
-        uint32_t reg;
-        asm volatile (
-                "vmrs %0, fpexc\n"
-                :"=r" (reg)::
-        );
-        return reg;
-}
-
-static inline void fpexc_write(uint32_t val)
-{
-        asm volatile (
-                "vmsr fpexc, %0\n"
-                ::"r" (val):
-        );
-}
+extern uint32_t fpsid_read(void);
+extern uint32_t mvfr0_read(void);
+extern uint32_t fpscr_read(void);
+extern void fpscr_write(uint32_t);
+extern uint32_t fpexc_read(void);
+extern void fpexc_write(uint32_t);
+
+extern void fpu_context_save_s32(fpu_context_t *);
+extern void fpu_context_restore_s32(fpu_context_t *);
+extern void fpu_context_save_d16(fpu_context_t *);
+extern void fpu_context_restore_d16(fpu_context_t *);
+extern void fpu_context_save_d32(fpu_context_t *);
+extern void fpu_context_restore_d32(fpu_context_t *);
 
 static void (*save_context)(fpu_context_t *ctx);
 static void (*restore_context)(fpu_context_t *ctx);
-
-/** Saves 32 single precision fpu registers.
- * @param ctx FPU context area.
- * Used by VFPv1
- */
-static void fpu_context_save_s32(fpu_context_t *ctx)
-{
-        asm volatile (
-                "vmrs r1, fpexc\n"
-                "vmrs r2, fpscr\n"
-                "stmia %0!, {r1, r2}\n"
-                "vstmia %0!, {s0-s31}\n"
-                ::"r" (ctx): "r1","r2","memory"
-        );
-}
-
-/** Restores 32 single precision fpu registers.
- * @param ctx FPU context area.
- * Used by VFPv1
- */
-static void fpu_context_restore_s32(fpu_context_t *ctx)
-{
-        asm volatile (
-                "ldmia %0!, {r1, r2}\n"
-                "vmsr fpexc, r1\n"
-                "vmsr fpscr, r2\n"
-                "vldmia %0!, {s0-s31}\n"
-                ::"r" (ctx): "r1","r2"
-        );
-}
-
-/** Saves 16 double precision fpu registers.
- * @param ctx FPU context area.
- * Used by VFPv2, VFPv3-d16, and VFPv4-d16.
- */
-static void fpu_context_save_d16(fpu_context_t *ctx)
-{
-        asm volatile (
-                "vmrs r1, fpexc\n"
-                "vmrs r2, fpscr\n"
-                "stmia %0!, {r1, r2}\n"
-                "vstmia %0!, {d0-d15}\n"
-                ::"r" (ctx): "r1","r2","memory"
-        );
-}
-
-/** Restores 16 double precision fpu registers.
- * @param ctx FPU context area.
- * Used by VFPv2, VFPv3-d16, and VFPv4-d16.
- */
-static void fpu_context_restore_d16(fpu_context_t *ctx)
-{
-        asm volatile (
-                "ldmia %0!, {r1, r2}\n"
-                "vmsr fpexc, r1\n"
-                "vmsr fpscr, r2\n"
-                "vldmia %0!, {d0-d15}\n"
-                ::"r" (ctx): "r1","r2"
-        );
-}
-
-/** Saves 32 double precision fpu registers.
- * @param ctx FPU context area.
- * Used by VFPv3-d32, VFPv4-d32, and advanced SIMD.
- */
-static void fpu_context_save_d32(fpu_context_t *ctx)
-{
-        asm volatile (
-                "vmrs r1, fpexc\n"
-                "stmia %0!, {r1}\n"
-                "vmrs r1, fpscr\n"
-                "stmia %0!, {r1}\n"
-                "vstmia %0!, {d0-d15}\n"
-                "vstmia %0!, {d16-d31}\n"
-                ::"r" (ctx): "r1","memory"
-        );
-}
-
-/** Restores 32 double precision fpu registers.
- * @param ctx FPU context area.
- * Used by VFPv3-d32, VFPv4-d32, and advanced SIMD.
- */
-static void fpu_context_restore_d32(fpu_context_t *ctx)
-{
-        asm volatile (
-                "ldmia %0!, {r1}\n"
-                "vmsr fpexc, r1\n"
-                "ldmia %0!, {r1}\n"
-                "vmsr fpscr, r1\n"
-                "vldmia %0!, {d0-d15}\n"
-                "vldmia %0!, {d16-d31}\n"
-                ::"r" (ctx): "r1"
-        );
-}
 
 static int fpu_have_coprocessor_access()
@@ -285 +169 @@
                 return;
 
-        uint32_t fpsid = 0;
-        asm volatile (
-                "vmrs %0, fpsid\n"
-                :"=r"(fpsid)::
-        );
+        const uint32_t fpsid = fpsid_read();
         if (fpsid & FPSID_SW_ONLY_FLAG) {
                 printf("No FPU avaiable\n");
@@ -309 +189 @@
         case FPU_VFPv3_NO_COMMON:
         case FPU_VFPv3_COMMONv3: {
-                uint32_t mvfr0 = 0;
-                asm volatile (
-                        "vmrs %0,mvfr0\n"
-                        :"=r"(mvfr0)::
-                );
+                const uint32_t mvfr0 = mvfr0_read();
                 /* See page B4-1637 */
                 if ((mvfr0 & 0xf) == 0x1) {