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-              r40ca402
+              rdd4d6b0
+}
+/** Write to MSR */
+static inline void write_msr(__u32 msr, __u64 value)
+{
+        __asm__ volatile (
+                "wrmsr;" : : "c" (msr),
+                "a" ((__u32)(value)),
+                "d" ((__u32)(value >> 32))
+                );
+}
+static inline __native read_msr(__u32 msr)
+{
+        __u32 ax, dx;
+        __asm__ volatile (
+                "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
+                );
+        return ((__u64)dx << 32) | ax;
+}
 /** Enable local APIC

arch/amd64/include/cpu.h

-              r40ca402
+              rdd4d6b0
 #define AMD_NXE_FLAG    11
+/* MSR registers */
+#define AMD_MSR_STAR    0xc0000081
+#define AMD_MSR_LSTAR   0xc0000082
+#define AMD_MSR_SFMASK  0xc0000084
 #ifndef __ASM__

-              r40ca402
+              rdd4d6b0
 #define NULL_DES        0
+/* Warning: Do not reorder next items, unless you look into syscall.c!!! */
 #define KTEXT_DES       1
 #define KDATA_DES       2
 #define UTEXT_DES       3
 #define UDATA_DES       4
+#define UDATA_DES       3
+#define UTEXT_DES       4
 #define KTEXT32_DES     5
+/* EndOfWarning */
 #define TSS_DES         6

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