Index: kernel/arch/amd64/include/context.h =================================================================== --- kernel/arch/amd64/include/context.h (revision 0b4a67a31961a80515a7b28d5b2e27fbb8f7249d) +++ kernel/arch/amd64/include/context.h (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -27,5 +27,5 @@ */ -/** @addtogroup amd64 +/** @addtogroup amd64 * @{ */ @@ -44,5 +44,5 @@ * panic sooner or later */ -#define SP_DELTA 16 +#define SP_DELTA 16 #define context_set(c, _pc, stack, size) \ Index: kernel/arch/amd64/include/context_offset.h =================================================================== --- kernel/arch/amd64/include/context_offset.h (revision 0b4a67a31961a80515a7b28d5b2e27fbb8f7249d) +++ kernel/arch/amd64/include/context_offset.h (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -30,22 +30,22 @@ #define KERN_amd64_CONTEXT_OFFSET_H_ -#define OFFSET_SP 0x0 -#define OFFSET_PC 0x8 -#define OFFSET_RBX 0x10 -#define OFFSET_RBP 0x18 -#define OFFSET_R12 0x20 -#define OFFSET_R13 0x28 -#define OFFSET_R14 0x30 -#define OFFSET_R15 0x38 +#define OFFSET_SP 0x00 +#define OFFSET_PC 0x08 +#define OFFSET_RBX 0x10 +#define OFFSET_RBP 0x18 +#define OFFSET_R12 0x20 +#define OFFSET_R13 0x28 +#define OFFSET_R14 0x30 +#define OFFSET_R15 0x38 #ifdef KERNEL -# define OFFSET_IPL 0x40 + #define OFFSET_IPL 0x40 #else -# define OFFSET_TLS 0x40 + #define OFFSET_TLS 0x40 #endif #ifdef __ASM__ -# ctx: address of the structure with saved context +# ctx: address of the structure with saved context # pc: return address .macro CONTEXT_SAVE_ARCH_CORE ctx:req pc:req @@ -61,5 +61,5 @@ .endm -# ctx: address of the structure with saved context +# ctx: address of the structure with saved context .macro CONTEXT_RESTORE_ARCH_CORE ctx:req pc:req movq OFFSET_R15(\ctx), %r15 @@ -68,5 +68,5 @@ movq OFFSET_R12(\ctx), %r12 movq OFFSET_RBP(\ctx), %rbp - movq OFFSET_RBX(\ctx), %rbx + movq OFFSET_RBX(\ctx), %rbx movq OFFSET_SP(\ctx), %rsp # ctx->sp -> %rsp Index: kernel/arch/amd64/include/cpu.h =================================================================== --- kernel/arch/amd64/include/cpu.h (revision 0b4a67a31961a80515a7b28d5b2e27fbb8f7249d) +++ kernel/arch/amd64/include/cpu.h (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -36,15 +36,15 @@ #define KERN_amd64_CPU_H_ -#define RFLAGS_CF (1 << 0) -#define RFLAGS_PF (1 << 2) -#define RFLAGS_AF (1 << 4) -#define RFLAGS_ZF (1 << 6) -#define RFLAGS_SF (1 << 7) -#define RFLAGS_TF (1 << 8) -#define RFLAGS_IF (1 << 9) -#define RFLAGS_DF (1 << 10) -#define RFLAGS_OF (1 << 11) -#define RFLAGS_NT (1 << 14) -#define RFLAGS_RF (1 << 16) +#define RFLAGS_CF (1 << 0) +#define RFLAGS_PF (1 << 2) +#define RFLAGS_AF (1 << 4) +#define RFLAGS_ZF (1 << 6) +#define RFLAGS_SF (1 << 7) +#define RFLAGS_TF (1 << 8) +#define RFLAGS_IF (1 << 9) +#define RFLAGS_DF (1 << 10) +#define RFLAGS_OF (1 << 11) +#define RFLAGS_NT (1 << 14) +#define RFLAGS_RF (1 << 16) #define EFER_MSR_NUM 0xc0000080 Index: kernel/arch/amd64/include/debugger.h =================================================================== --- kernel/arch/amd64/include/debugger.h (revision 0b4a67a31961a80515a7b28d5b2e27fbb8f7249d) +++ kernel/arch/amd64/include/debugger.h (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -41,9 +41,9 @@ /* Flags that are passed to breakpoint_add function */ -#define BKPOINT_INSTR 0x1 -#define BKPOINT_WRITE 0x2 -#define BKPOINT_READ_WRITE 0x4 +#define BKPOINT_INSTR 0x1U +#define BKPOINT_WRITE 0x2U +#define BKPOINT_READ_WRITE 0x4U -#define BKPOINT_CHECK_ZERO 0x8 +#define BKPOINT_CHECK_ZERO 0x8U Index: kernel/arch/amd64/include/istate.h =================================================================== --- kernel/arch/amd64/include/istate.h (revision 0b4a67a31961a80515a7b28d5b2e27fbb8f7249d) +++ kernel/arch/amd64/include/istate.h (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -37,10 +37,15 @@ #ifdef KERNEL + #include #include -#else + +#else /* KERNEL */ + #include + #define NO_TRACE -#endif + +#endif /* KERNEL */ /** This is passed to interrupt handlers */ @@ -61,13 +66,13 @@ uint64_t r14; uint64_t r15; - uint64_t alignment; /* align rbp_frame on multiple of 16 */ - uint64_t rbp_frame; /* imitation of frame pointer linkage */ - uint64_t rip_frame; /* imitation of return address linkage */ - uint64_t error_word; /* real or fake error word */ + uint64_t alignment; /* align rbp_frame on multiple of 16 */ + uint64_t rbp_frame; /* imitation of frame pointer linkage */ + uint64_t rip_frame; /* imitation of return address linkage */ + uint64_t error_word; /* real or fake error word */ uint64_t rip; uint64_t cs; uint64_t rflags; - uint64_t rsp; /* only if istate_t is from uspace */ - uint64_t ss; /* only if istate_t is from uspace */ + uint64_t rsp; /* only if istate_t is from uspace */ + uint64_t ss; /* only if istate_t is from uspace */ } istate_t; @@ -75,5 +80,5 @@ NO_TRACE static inline int istate_from_uspace(istate_t *istate) { - return !(istate->rip & 0x8000000000000000); + return !(istate->rip & UINT64_C(0x8000000000000000)); } Index: kernel/arch/amd64/include/mm/as.h =================================================================== --- kernel/arch/amd64/include/mm/as.h (revision 0b4a67a31961a80515a7b28d5b2e27fbb8f7249d) +++ kernel/arch/amd64/include/mm/as.h (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -36,14 +36,14 @@ #define KERN_amd64_AS_H_ -#define ADDRESS_SPACE_HOLE_START 0x0000800000000000ULL -#define ADDRESS_SPACE_HOLE_END 0xffff7fffffffffffULL +#define ADDRESS_SPACE_HOLE_START UINT64_C(0x0000800000000000) +#define ADDRESS_SPACE_HOLE_END UINT64_C(0xffff7fffffffffff) #define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0 -#define KERNEL_ADDRESS_SPACE_START_ARCH 0xffff800000000000ULL -#define KERNEL_ADDRESS_SPACE_END_ARCH 0xffffffffffffffffULL +#define KERNEL_ADDRESS_SPACE_START_ARCH UINT64_C(0xffff800000000000) +#define KERNEL_ADDRESS_SPACE_END_ARCH UINT64_C(0xffffffffffffffff) -#define USER_ADDRESS_SPACE_START_ARCH 0x0000000000000000ULL -#define USER_ADDRESS_SPACE_END_ARCH 0x00007fffffffffffULL +#define USER_ADDRESS_SPACE_START_ARCH UINT64_C(0x0000000000000000) +#define USER_ADDRESS_SPACE_END_ARCH UINT64_C(0x00007fffffffffff) #define USTACK_ADDRESS_ARCH (USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1)) Index: kernel/arch/amd64/include/mm/page.h =================================================================== --- kernel/arch/amd64/include/mm/page.h (revision 0b4a67a31961a80515a7b28d5b2e27fbb8f7249d) +++ kernel/arch/amd64/include/mm/page.h (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -55,6 +55,6 @@ #ifndef __ASM__ -#define KA2PA(x) (((uintptr_t) (x)) - 0xffff800000000000) -#define PA2KA(x) (((uintptr_t) (x)) + 0xffff800000000000) +#define KA2PA(x) (((uintptr_t) (x)) - UINT64_C(0xffff800000000000)) +#define PA2KA(x) (((uintptr_t) (x)) + UINT64_C(0xffff800000000000)) #else /* __ASM__ */ @@ -78,8 +78,8 @@ /* Macros calculating indices into page tables in each level. */ -#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 39) & 0x1ff) -#define PTL1_INDEX_ARCH(vaddr) (((vaddr) >> 30) & 0x1ff) -#define PTL2_INDEX_ARCH(vaddr) (((vaddr) >> 21) & 0x1ff) -#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x1ff) +#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 39) & 0x1ffU) +#define PTL1_INDEX_ARCH(vaddr) (((vaddr) >> 30) & 0x1ffU) +#define PTL2_INDEX_ARCH(vaddr) (((vaddr) >> 21) & 0x1ffU) +#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x1ffU) /* Get PTE address accessors for each level. */ @@ -205,5 +205,5 @@ pte_t *p = &pt[i]; - p->addr_12_31 = (a >> 12) & 0xfffff; + p->addr_12_31 = (a >> 12) & UINT32_C(0xfffff); p->addr_32_51 = a >> 32; } Index: kernel/arch/amd64/include/pm.h =================================================================== --- kernel/arch/amd64/include/pm.h (revision 0b4a67a31961a80515a7b28d5b2e27fbb8f7249d) +++ kernel/arch/amd64/include/pm.h (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -75,7 +75,7 @@ #define AR_WRITABLE (1 << 1) #define AR_READABLE (1 << 1) -#define AR_TSS (0x09) -#define AR_INTERRUPT (0x0e) -#define AR_TRAP (0x0f) +#define AR_TSS (0x09U) +#define AR_INTERRUPT (0x0eU) +#define AR_TRAP (0x0fU) #define DPL_KERNEL (PL_KERNEL << 5) Index: kernel/arch/amd64/include/types.h =================================================================== --- kernel/arch/amd64/include/types.h (revision 0b4a67a31961a80515a7b28d5b2e27fbb8f7249d) +++ kernel/arch/amd64/include/types.h (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -50,26 +50,9 @@ } fncptr_t; -/* Formats for uintptr_t, size_t */ -#define PRIp "llx" -#define PRIs "llu" - -/* Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */ -#define PRId8 "d" -#define PRId16 "d" -#define PRId32 "d" -#define PRId64 "lld" -#define PRIdn "lld" - -#define PRIu8 "u" -#define PRIu16 "u" -#define PRIu32 "u" -#define PRIu64 "llu" -#define PRIun "llu" - -#define PRIx8 "x" -#define PRIx16 "x" -#define PRIx32 "x" -#define PRIx64 "llx" -#define PRIxn "llx" +#define PRIp PRIx64 /**< Format for uintptr_t. */ +#define PRIs PRIu64 /**< Format for size_t. */ +#define PRIdn PRId64 /**< Format for native_t. */ +#define PRIun PRIu64 /**< Format for unative_t. */ +#define PRIxn PRIx64 /**< Format for hexadecimal unative_t. */ #endif Index: kernel/arch/amd64/src/boot/memmap.c =================================================================== --- kernel/arch/amd64/src/boot/memmap.c (revision 0b4a67a31961a80515a7b28d5b2e27fbb8f7249d) +++ kernel/arch/amd64/src/boot/memmap.c (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -35,5 +35,5 @@ #include -uint8_t e820counter = 0xff; +uint8_t e820counter = 0xffU; e820memmap_t e820table[MEMMAP_E820_MAX_RECORDS]; Index: kernel/arch/amd64/src/cpu/cpu.c =================================================================== --- kernel/arch/amd64/src/cpu/cpu.c (revision 0b4a67a31961a80515a7b28d5b2e27fbb8f7249d) +++ kernel/arch/amd64/src/cpu/cpu.c (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -47,12 +47,11 @@ * Contains only non-MP-Specification specific SMP code. */ -#define AMD_CPUID_EBX 0x68747541 -#define AMD_CPUID_ECX 0x444d4163 -#define AMD_CPUID_EDX 0x69746e65 +#define AMD_CPUID_EBX UINT32_C(0x68747541) +#define AMD_CPUID_ECX UINT32_C(0x444d4163) +#define AMD_CPUID_EDX UINT32_C(0x69746e65) -#define INTEL_CPUID_EBX 0x756e6547 -#define INTEL_CPUID_ECX 0x6c65746e -#define INTEL_CPUID_EDX 0x49656e69 - +#define INTEL_CPUID_EBX UINT32_C(0x756e6547) +#define INTEL_CPUID_ECX UINT32_C(0x6c65746e) +#define INTEL_CPUID_EDX UINT32_C(0x49656e69) enum vendor { Index: kernel/arch/amd64/src/debugger.c =================================================================== --- kernel/arch/amd64/src/debugger.c (revision 0b4a67a31961a80515a7b28d5b2e27fbb8f7249d) +++ kernel/arch/amd64/src/debugger.c (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -126,5 +126,5 @@ /* Disable breakpoint in DR7 */ unative_t dr7 = read_dr7(); - dr7 &= ~(0x2 << (curidx * 2)); + dr7 &= ~(0x02U << (curidx * 2)); /* Setup DR register */ @@ -147,24 +147,24 @@ /* Set type to requested breakpoint & length*/ - dr7 &= ~(0x3 << (16 + 4 * curidx)); - dr7 &= ~(0x3 << (18 + 4 * curidx)); + dr7 &= ~(0x03U << (16 + 4 * curidx)); + dr7 &= ~(0x03U << (18 + 4 * curidx)); if (!(flags & BKPOINT_INSTR)) { #ifdef __32_BITS__ - dr7 |= ((unative_t) 0x3) << (18 + 4 * curidx); + dr7 |= ((unative_t) 0x03U) << (18 + 4 * curidx); #endif #ifdef __64_BITS__ - dr7 |= ((unative_t) 0x2) << (18 + 4 * curidx); + dr7 |= ((unative_t) 0x02U) << (18 + 4 * curidx); #endif if ((flags & BKPOINT_WRITE)) - dr7 |= ((unative_t) 0x1) << (16 + 4 * curidx); + dr7 |= ((unative_t) 0x01U) << (16 + 4 * curidx); else if ((flags & BKPOINT_READ_WRITE)) - dr7 |= ((unative_t) 0x3) << (16 + 4 * curidx); + dr7 |= ((unative_t) 0x03U) << (16 + 4 * curidx); } /* Enable global breakpoint */ - dr7 |= 0x2 << (curidx * 2); + dr7 |= 0x02U << (curidx * 2); write_dr7(dr7); Index: kernel/arch/amd64/src/pm.c =================================================================== --- kernel/arch/amd64/src/pm.c (revision 0b4a67a31961a80515a7b28d5b2e27fbb8f7249d) +++ kernel/arch/amd64/src/pm.c (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -28,5 +28,5 @@ */ -/** @addtogroup amd64 +/** @addtogroup amd64 * @{ */ @@ -52,57 +52,57 @@ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* KTEXT descriptor */ - { .limit_0_15 = 0xffff, - .base_0_15 = 0, - .base_16_23 = 0, - .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, - .limit_16_19 = 0xf, - .available = 0, - .longmode = 1, + { .limit_0_15 = 0xffffU, + .base_0_15 = 0, + .base_16_23 = 0, + .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, + .limit_16_19 = 0x0fU, + .available = 0, + .longmode = 1, .special = 0, - .granularity = 1, + .granularity = 1, .base_24_31 = 0 }, /* KDATA descriptor */ - { .limit_0_15 = 0xffff, - .base_0_15 = 0, - .base_16_23 = 0, - .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, - .limit_16_19 = 0xf, - .available = 0, - .longmode = 0, - .special = 0, - .granularity = 1, + { .limit_0_15 = 0xffffU, + .base_0_15 = 0, + .base_16_23 = 0, + .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, + .limit_16_19 = 0x0fU, + .available = 0, + .longmode = 0, + .special = 0, + .granularity = 1, .base_24_31 = 0 }, /* UDATA descriptor */ - { .limit_0_15 = 0xffff, - .base_0_15 = 0, - .base_16_23 = 0, - .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, - .limit_16_19 = 0xf, - .available = 0, - .longmode = 0, - .special = 1, - .granularity = 1, + { .limit_0_15 = 0xffffU, + .base_0_15 = 0, + .base_16_23 = 0, + .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, + .limit_16_19 = 0x0fU, + .available = 0, + .longmode = 0, + .special = 1, + .granularity = 1, .base_24_31 = 0 }, /* UTEXT descriptor */ - { .limit_0_15 = 0xffff, - .base_0_15 = 0, - .base_16_23 = 0, - .access = AR_PRESENT | AR_CODE | DPL_USER, - .limit_16_19 = 0xf, - .available = 0, - .longmode = 1, - .special = 0, - .granularity = 1, + { .limit_0_15 = 0xffffU, + .base_0_15 = 0, + .base_16_23 = 0, + .access = AR_PRESENT | AR_CODE | DPL_USER, + .limit_16_19 = 0x0fU, + .available = 0, + .longmode = 1, + .special = 0, + .granularity = 1, .base_24_31 = 0 }, /* KTEXT 32-bit protected, for protected mode before long mode */ - { .limit_0_15 = 0xffff, - .base_0_15 = 0, - .base_16_23 = 0, - .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, - .limit_16_19 = 0xf, - .available = 0, - .longmode = 0, + { .limit_0_15 = 0xffffU, + .base_0_15 = 0, + .base_16_23 = 0, + .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, + .limit_16_19 = 0x0fU, + .available = 0, + .longmode = 0, .special = 1, - .granularity = 1, + .granularity = 1, .base_24_31 = 0 }, /* TSS descriptor - set up will be completed later, @@ -111,7 +111,8 @@ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* VESA Init descriptor */ -#ifdef CONFIG_FB - { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | DPL_KERNEL, - 0xf, 0, 0, 0, 0, 0 +#ifdef CONFIG_FB + { + 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | DPL_KERNEL, + 0xf, 0, 0, 0, 0, 0 } #endif @@ -129,8 +130,8 @@ { tss_descriptor_t *td = (tss_descriptor_t *) d; - - td->base_0_15 = base & 0xffff; - td->base_16_23 = ((base) >> 16) & 0xff; - td->base_24_31 = ((base) >> 24) & 0xff; + + td->base_0_15 = base & 0xffffU; + td->base_16_23 = ((base) >> 16) & 0xffU; + td->base_24_31 = ((base) >> 24) & 0xffU; td->base_32_63 = ((base) >> 32); } @@ -140,6 +141,6 @@ tss_descriptor_t *td = (tss_descriptor_t *) d; - td->limit_0_15 = limit & 0xffff; - td->limit_16_19 = (limit >> 16) & 0xf; + td->limit_0_15 = limit & 0xffffU; + td->limit_16_19 = (limit >> 16) & 0x0fU; } @@ -149,6 +150,6 @@ * Offset is a linear address. */ - d->offset_0_15 = offset & 0xffff; - d->offset_16_31 = offset >> 16 & 0xffff; + d->offset_0_15 = offset & 0xffffU; + d->offset_16_31 = (offset >> 16) & 0xffffU; d->offset_32_63 = offset >> 32; } @@ -165,16 +166,16 @@ { idescriptor_t *d; - int i; - + unsigned int i; + for (i = 0; i < IDT_ITEMS; i++) { d = &idt[i]; - + d->unused = 0; d->selector = GDT_SELECTOR(KTEXT_DES); - + d->present = 1; - d->type = AR_INTERRUPT; /* masking interrupt */ + d->type = AR_INTERRUPT; /* masking interrupt */ } - + d = &idt[0]; idt_setoffset(d++, (uintptr_t) &int_0);