Changes in kernel/arch/amd64/src/pm.c [149d14e5:dc0b964] in mainline
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- 1 edited
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kernel/arch/amd64/src/pm.c (modified) (8 diffs)
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kernel/arch/amd64/src/pm.c
r149d14e5 rdc0b964 28 28 */ 29 29 30 /** @addtogroup amd64 30 /** @addtogroup amd64 31 31 * @{ 32 32 */ … … 52 52 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 53 53 /* KTEXT descriptor */ 54 { .limit_0_15 = 0xffff ,55 .base_0_15 = 0, 56 .base_16_23 = 0, 57 .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, 58 .limit_16_19 = 0x f,59 .available = 0, 60 .longmode = 1, 54 { .limit_0_15 = 0xffffU, 55 .base_0_15 = 0, 56 .base_16_23 = 0, 57 .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, 58 .limit_16_19 = 0x0fU, 59 .available = 0, 60 .longmode = 1, 61 61 .special = 0, 62 .granularity = 1, 62 .granularity = 1, 63 63 .base_24_31 = 0 }, 64 64 /* KDATA descriptor */ 65 { .limit_0_15 = 0xffff ,66 .base_0_15 = 0, 67 .base_16_23 = 0, 68 .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 69 .limit_16_19 = 0x f,70 .available = 0, 71 .longmode = 0, 72 .special = 0, 73 .granularity = 1, 65 { .limit_0_15 = 0xffffU, 66 .base_0_15 = 0, 67 .base_16_23 = 0, 68 .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 69 .limit_16_19 = 0x0fU, 70 .available = 0, 71 .longmode = 0, 72 .special = 0, 73 .granularity = 1, 74 74 .base_24_31 = 0 }, 75 75 /* UDATA descriptor */ 76 { .limit_0_15 = 0xffff ,77 .base_0_15 = 0, 78 .base_16_23 = 0, 79 .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 80 .limit_16_19 = 0x f,81 .available = 0, 82 .longmode = 0, 83 .special = 1, 84 .granularity = 1, 76 { .limit_0_15 = 0xffffU, 77 .base_0_15 = 0, 78 .base_16_23 = 0, 79 .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 80 .limit_16_19 = 0x0fU, 81 .available = 0, 82 .longmode = 0, 83 .special = 1, 84 .granularity = 1, 85 85 .base_24_31 = 0 }, 86 86 /* UTEXT descriptor */ 87 { .limit_0_15 = 0xffff ,88 .base_0_15 = 0, 89 .base_16_23 = 0, 90 .access = AR_PRESENT | AR_CODE | DPL_USER, 91 .limit_16_19 = 0x f,92 .available = 0, 93 .longmode = 1, 94 .special = 0, 95 .granularity = 1, 87 { .limit_0_15 = 0xffffU, 88 .base_0_15 = 0, 89 .base_16_23 = 0, 90 .access = AR_PRESENT | AR_CODE | DPL_USER, 91 .limit_16_19 = 0x0fU, 92 .available = 0, 93 .longmode = 1, 94 .special = 0, 95 .granularity = 1, 96 96 .base_24_31 = 0 }, 97 97 /* KTEXT 32-bit protected, for protected mode before long mode */ 98 { .limit_0_15 = 0xffff ,99 .base_0_15 = 0, 100 .base_16_23 = 0, 101 .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, 102 .limit_16_19 = 0x f,103 .available = 0, 104 .longmode = 0, 98 { .limit_0_15 = 0xffffU, 99 .base_0_15 = 0, 100 .base_16_23 = 0, 101 .access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE, 102 .limit_16_19 = 0x0fU, 103 .available = 0, 104 .longmode = 0, 105 105 .special = 1, 106 .granularity = 1, 106 .granularity = 1, 107 107 .base_24_31 = 0 }, 108 108 /* TSS descriptor - set up will be completed later, … … 111 111 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 112 112 /* VESA Init descriptor */ 113 #ifdef CONFIG_FB 114 { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | DPL_KERNEL, 115 0xf, 0, 0, 0, 0, 0 113 #ifdef CONFIG_FB 114 { 115 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | DPL_KERNEL, 116 0xf, 0, 0, 0, 0, 0 116 117 } 117 118 #endif … … 129 130 { 130 131 tss_descriptor_t *td = (tss_descriptor_t *) d; 131 132 td->base_0_15 = base & 0xffff ;133 td->base_16_23 = ((base) >> 16) & 0xff ;134 td->base_24_31 = ((base) >> 24) & 0xff ;132 133 td->base_0_15 = base & 0xffffU; 134 td->base_16_23 = ((base) >> 16) & 0xffU; 135 td->base_24_31 = ((base) >> 24) & 0xffU; 135 136 td->base_32_63 = ((base) >> 32); 136 137 } … … 140 141 tss_descriptor_t *td = (tss_descriptor_t *) d; 141 142 142 td->limit_0_15 = limit & 0xffff ;143 td->limit_16_19 = (limit >> 16) & 0x f;143 td->limit_0_15 = limit & 0xffffU; 144 td->limit_16_19 = (limit >> 16) & 0x0fU; 144 145 } 145 146 … … 149 150 * Offset is a linear address. 150 151 */ 151 d->offset_0_15 = offset & 0xffff ;152 d->offset_16_31 = offset >> 16 & 0xffff;152 d->offset_0_15 = offset & 0xffffU; 153 d->offset_16_31 = (offset >> 16) & 0xffffU; 153 154 d->offset_32_63 = offset >> 32; 154 155 } … … 165 166 { 166 167 idescriptor_t *d; 167 int i;168 168 unsigned int i; 169 169 170 for (i = 0; i < IDT_ITEMS; i++) { 170 171 d = &idt[i]; 171 172 172 173 d->unused = 0; 173 d->selector = gdtselector(KTEXT_DES);174 174 d->selector = GDT_SELECTOR(KTEXT_DES); 175 175 176 d->present = 1; 176 d->type = AR_INTERRUPT; /* masking interrupt */ 177 178 idt_setoffset(d, ((uintptr_t) interrupt_handlers) + 179 i * interrupt_handler_size); 177 d->type = AR_INTERRUPT; /* masking interrupt */ 180 178 } 179 180 d = &idt[0]; 181 idt_setoffset(d++, (uintptr_t) &int_0); 182 idt_setoffset(d++, (uintptr_t) &int_1); 183 idt_setoffset(d++, (uintptr_t) &int_2); 184 idt_setoffset(d++, (uintptr_t) &int_3); 185 idt_setoffset(d++, (uintptr_t) &int_4); 186 idt_setoffset(d++, (uintptr_t) &int_5); 187 idt_setoffset(d++, (uintptr_t) &int_6); 188 idt_setoffset(d++, (uintptr_t) &int_7); 189 idt_setoffset(d++, (uintptr_t) &int_8); 190 idt_setoffset(d++, (uintptr_t) &int_9); 191 idt_setoffset(d++, (uintptr_t) &int_10); 192 idt_setoffset(d++, (uintptr_t) &int_11); 193 idt_setoffset(d++, (uintptr_t) &int_12); 194 idt_setoffset(d++, (uintptr_t) &int_13); 195 idt_setoffset(d++, (uintptr_t) &int_14); 196 idt_setoffset(d++, (uintptr_t) &int_15); 197 idt_setoffset(d++, (uintptr_t) &int_16); 198 idt_setoffset(d++, (uintptr_t) &int_17); 199 idt_setoffset(d++, (uintptr_t) &int_18); 200 idt_setoffset(d++, (uintptr_t) &int_19); 201 idt_setoffset(d++, (uintptr_t) &int_20); 202 idt_setoffset(d++, (uintptr_t) &int_21); 203 idt_setoffset(d++, (uintptr_t) &int_22); 204 idt_setoffset(d++, (uintptr_t) &int_23); 205 idt_setoffset(d++, (uintptr_t) &int_24); 206 idt_setoffset(d++, (uintptr_t) &int_25); 207 idt_setoffset(d++, (uintptr_t) &int_26); 208 idt_setoffset(d++, (uintptr_t) &int_27); 209 idt_setoffset(d++, (uintptr_t) &int_28); 210 idt_setoffset(d++, (uintptr_t) &int_29); 211 idt_setoffset(d++, (uintptr_t) &int_30); 212 idt_setoffset(d++, (uintptr_t) &int_31); 213 idt_setoffset(d++, (uintptr_t) &int_32); 214 idt_setoffset(d++, (uintptr_t) &int_33); 215 idt_setoffset(d++, (uintptr_t) &int_34); 216 idt_setoffset(d++, (uintptr_t) &int_35); 217 idt_setoffset(d++, (uintptr_t) &int_36); 218 idt_setoffset(d++, (uintptr_t) &int_37); 219 idt_setoffset(d++, (uintptr_t) &int_38); 220 idt_setoffset(d++, (uintptr_t) &int_39); 221 idt_setoffset(d++, (uintptr_t) &int_40); 222 idt_setoffset(d++, (uintptr_t) &int_41); 223 idt_setoffset(d++, (uintptr_t) &int_42); 224 idt_setoffset(d++, (uintptr_t) &int_43); 225 idt_setoffset(d++, (uintptr_t) &int_44); 226 idt_setoffset(d++, (uintptr_t) &int_45); 227 idt_setoffset(d++, (uintptr_t) &int_46); 228 idt_setoffset(d++, (uintptr_t) &int_47); 229 idt_setoffset(d++, (uintptr_t) &int_48); 230 idt_setoffset(d++, (uintptr_t) &int_49); 231 idt_setoffset(d++, (uintptr_t) &int_50); 232 idt_setoffset(d++, (uintptr_t) &int_51); 233 idt_setoffset(d++, (uintptr_t) &int_52); 234 idt_setoffset(d++, (uintptr_t) &int_53); 235 idt_setoffset(d++, (uintptr_t) &int_54); 236 idt_setoffset(d++, (uintptr_t) &int_55); 237 idt_setoffset(d++, (uintptr_t) &int_56); 238 idt_setoffset(d++, (uintptr_t) &int_57); 239 idt_setoffset(d++, (uintptr_t) &int_58); 240 idt_setoffset(d++, (uintptr_t) &int_59); 241 idt_setoffset(d++, (uintptr_t) &int_60); 242 idt_setoffset(d++, (uintptr_t) &int_61); 243 idt_setoffset(d++, (uintptr_t) &int_62); 244 idt_setoffset(d++, (uintptr_t) &int_63); 181 245 } 182 246 … … 228 292 * to its own TSS. We just need to load the TR register. 229 293 */ 230 tr_load( gdtselector(TSS_DES));294 tr_load(GDT_SELECTOR(TSS_DES)); 231 295 } 232 296
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