Changeset db4d6de in mainline for kernel/arch


Ignore:
Timestamp:
2009-11-28T16:30:43Z (16 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/fix-logger-deadlock, topic/msim-upgrade, topic/simplify-dev-export
Children:
c4702804
Parents:
ba8f8cb (diff), 67392fa (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

Location:
kernel/arch
Files:
17 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/amd64/include/mm/page.h

    rba8f8cb rdb4d6de  
    177177#define PFERR_CODE_ID           (1 << 4)
    178178
    179 static inline int get_pt_flags(pte_t *pt, size_t i)
     179/** Page Table Entry. */
     180typedef struct {
     181        unsigned present : 1;
     182        unsigned writeable : 1;
     183        unsigned uaccessible : 1;
     184        unsigned page_write_through : 1;
     185        unsigned page_cache_disable : 1;
     186        unsigned accessed : 1;
     187        unsigned dirty : 1;
     188        unsigned unused: 1;
     189        unsigned global : 1;
     190        unsigned soft_valid : 1;                /**< Valid content even if present bit is cleared. */
     191        unsigned avl : 2;
     192        unsigned addr_12_31 : 30;
     193        unsigned addr_32_51 : 21;
     194        unsigned no_execute : 1;
     195} __attribute__ ((packed)) pte_t;
     196
     197static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
    180198{
    181199        pte_t *p = &pt[i];

  • kernel/arch/amd64/include/types.h

    rba8f8cb rdb4d6de  
    8282#define PRIxn "llx"
    8383
    84 /** Page Table Entry. */
    85 typedef struct {
    86         unsigned present : 1;
    87         unsigned writeable : 1;
    88         unsigned uaccessible : 1;
    89         unsigned page_write_through : 1;
    90         unsigned page_cache_disable : 1;
    91         unsigned accessed : 1;
    92         unsigned dirty : 1;
    93         unsigned unused: 1;
    94         unsigned global : 1;
    95         unsigned soft_valid : 1;                /**< Valid content even if present bit is cleared. */
    96         unsigned avl : 2;
    97         unsigned addr_12_31 : 30;
    98         unsigned addr_32_51 : 21;
    99         unsigned no_execute : 1;
    100 } __attribute__ ((packed)) pte_t;
    101 
    10284#endif
    10385

  • kernel/arch/amd64/src/cpu/cpu.c

    rba8f8cb rdb4d6de  
    130130        CPU->arch.vendor = VendorUnknown;
    131131        if (has_cpuid()) {
    132                 cpuid(0, &info);
     132                cpuid(INTEL_CPUID_LEVEL, &info);
    133133
    134134                /*
    … …  
    150150                }
    151151                               
    152                 cpuid(1, &info);
     152                cpuid(INTEL_CPUID_STANDARD, &info);
    153153                CPU->arch.family = (info.cpuid_eax >> 8) & 0xf;
    154154                CPU->arch.model = (info.cpuid_eax >> 4) & 0xf;

  • kernel/arch/arm32/include/mm/page.h

    rba8f8cb rdb4d6de  
    7575/* Get PTE address accessors for each level. */
    7676#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
    77         ((pte_t *) ((((pte_level0_t *)(ptl0))[(i)]).coarse_table_addr << 10))
     77        ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10))
    7878#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
    7979        (ptl1)
    … …  
    8181        (ptl2)
    8282#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
    83         ((uintptr_t) ((((pte_level1_t *)(ptl3))[(i)]).frame_base_addr << 12))
     83        ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12))
    8484
    8585/* Set PTE address accessors for each level. */
    8686#define SET_PTL0_ADDRESS_ARCH(ptl0) \
    87         (set_ptl0_addr((pte_level0_t *) (ptl0)))
     87        (set_ptl0_addr((pte_t *) (ptl0)))
    8888#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
    89         (((pte_level0_t *) (ptl0))[(i)].coarse_table_addr = (a) >> 10)
     89        (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)
    9090#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
    9191#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
    9292#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
    93         (((pte_level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12)
     93        (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)
    9494
    9595/* Get PTE flags accessors for each level. */
    9696#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
    97         get_pt_level0_flags((pte_level0_t *) (ptl0), (size_t) (i))
     97        get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i))
    9898#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
    9999        PAGE_PRESENT
    … …  
    101101        PAGE_PRESENT
    102102#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
    103         get_pt_level1_flags((pte_level1_t *) (ptl3), (size_t) (i))
     103        get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i))
    104104
    105105/* Set PTE flags accessors for each level. */
    106106#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
    107         set_pt_level0_flags((pte_level0_t *) (ptl0), (size_t) (i), (x))
     107        set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x))
    108108#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
    109109#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
    110110#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
    111         set_pt_level1_flags((pte_level1_t *) (ptl3), (size_t) (i), (x))
     111        set_pt_level1_flags((pte_t *) (ptl3), (size_t) (i), (x))
    112112
    113113/* Macros for querying the last-level PTE entries. */
    … …  
    115115        (*((uint32_t *) (pte)) != 0)
    116116#define PTE_PRESENT_ARCH(pte) \
    117         (((pte_level0_t *) (pte))->descriptor_type != 0)
     117        (((pte_t *) (pte))->l0.descriptor_type != 0)
    118118#define PTE_GET_FRAME_ARCH(pte) \
    119         (((pte_level1_t *) (pte))->frame_base_addr << FRAME_WIDTH)
     119        (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH)
    120120#define PTE_WRITABLE_ARCH(pte) \
    121         (((pte_level1_t *) (pte))->access_permission_0 == \
    122             PTE_AP_USER_RW_KERNEL_RW)
     121        (((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW)
    123122#define PTE_EXECUTABLE_ARCH(pte) \
    124123        1
    … …  
    159158} ATTRIBUTE_PACKED pte_level1_t;
    160159
     160typedef union {
     161        pte_level0_t l0;
     162        pte_level1_t l1;
     163} pte_t;
    161164
    162165/* Level 1 page tables access permissions */
    … …  
    191194 * @param pt    Pointer to the page table to set.
    192195 */   
    193 static inline void set_ptl0_addr(pte_level0_t *pt)
     196static inline void set_ptl0_addr(pte_t *pt)
    194197{
    195198        asm volatile (
    … …  
    205208 *  @param i      Index of the entry to return.
    206209 */
    207 static inline int get_pt_level0_flags(pte_level0_t *pt, size_t i)
    208 {
    209         pte_level0_t *p = &pt[i];
     210static inline int get_pt_level0_flags(pte_t *pt, size_t i)
     211{
     212        pte_level0_t *p = &pt[i].l0;
    210213        int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT);
    211214
    … …  
    220223 *  @param i      Index of the entry to return.
    221224 */
    222 static inline int get_pt_level1_flags(pte_level1_t *pt, size_t i)
    223 {
    224         pte_level1_t *p = &pt[i];
     225static inline int get_pt_level1_flags(pte_t *pt, size_t i)
     226{
     227        pte_level1_t *p = &pt[i].l1;
    225228
    226229        int dt = p->descriptor_type;
    … …  
    245248 *  @param flags  new flags
    246249 */
    247 static inline void set_pt_level0_flags(pte_level0_t *pt, size_t i, int flags)
    248 {
    249         pte_level0_t *p = &pt[i];
     250static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
     251{
     252        pte_level0_t *p = &pt[i].l0;
    250253
    251254        if (flags & PAGE_NOT_PRESENT) {
    … …  
    273276 *  @param flags  New flags.
    274277 */ 
    275 static inline void set_pt_level1_flags(pte_level1_t *pt, size_t i, int flags)
    276 {
    277         pte_level1_t *p = &pt[i];
     278static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
     279{
     280        pte_level1_t *p = &pt[i].l1;
    278281       
    279282        if (flags & PAGE_NOT_PRESENT) {

  • kernel/arch/arm32/include/types.h

    rba8f8cb rdb4d6de  
    8787#define PRIxn "x"       /**< Format for hexadecimal (u)native_t. */
    8888
    89 /** Page table entry.
    90  *
    91  *  We have different structs for level 0 and level 1 page table entries.
    92  *  See page.h for definition of pte_level*_t.
    93  */
    94 typedef struct {
    95         unsigned dummy : 32;
    96 } pte_t;
    97 
    9889#endif
    9990

  • kernel/arch/ia32/include/cpu.h

    rba8f8cb rdb4d6de  
    5050#include <arch/pm.h>
    5151#include <arch/asm.h>
     52#include <arch/cpuid.h>
    5253
    5354typedef struct {
    … …  
    5657        unsigned int model;
    5758        unsigned int stepping;
     59        cpuid_feature_info fi;
     60
    5861        tss_t *tss;
    5962       

  • kernel/arch/ia32/include/cpuid.h

    rba8f8cb rdb4d6de  
    6363
    6464struct __cpuid_feature_info {
    65         unsigned                        : 23;
     65        unsigned      : 11;
     66        unsigned sep  :  1;
     67        unsigned      : 11;
    6668        unsigned mmx  :  1;
    6769        unsigned fxsr :  1;

  • kernel/arch/ia32/include/mm/page.h

    rba8f8cb rdb4d6de  
    146146#define PFERR_CODE_RSVD         (1 << 3)       
    147147
    148 static inline int get_pt_flags(pte_t *pt, size_t i)
     148/** Page Table Entry. */
     149typedef struct {
     150        unsigned present : 1;
     151        unsigned writeable : 1;
     152        unsigned uaccessible : 1;
     153        unsigned page_write_through : 1;
     154        unsigned page_cache_disable : 1;
     155        unsigned accessed : 1;
     156        unsigned dirty : 1;
     157        unsigned pat : 1;
     158        unsigned global : 1;
     159        unsigned soft_valid : 1;        /**< Valid content even if the present bit is not set. */
     160        unsigned avl : 2;
     161        unsigned frame_address : 20;
     162} __attribute__ ((packed)) pte_t;
     163
     164static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
    149165{
    150166        pte_t *p = &pt[i];

  • kernel/arch/ia32/include/types.h

    rba8f8cb rdb4d6de  
    8080#define PRIxn "x"       /**< Format for hexadecimal (u)native_t. */
    8181
    82 /** Page Table Entry. */
    83 typedef struct {
    84         unsigned present : 1;
    85         unsigned writeable : 1;
    86         unsigned uaccessible : 1;
    87         unsigned page_write_through : 1;
    88         unsigned page_cache_disable : 1;
    89         unsigned accessed : 1;
    90         unsigned dirty : 1;
    91         unsigned pat : 1;
    92         unsigned global : 1;
    93         unsigned soft_valid : 1;        /**< Valid content even if the present bit is not set. */
    94         unsigned avl : 2;
    95         unsigned frame_address : 20;
    96 } __attribute__ ((packed)) pte_t;
    97 
    9882#endif
    9983

  • kernel/arch/ia32/src/boot/boot.S

    rba8f8cb rdb4d6de  
    8585        pse_supported:
    8686       
    87         bt $(INTEL_SEP), %edx
    88         jc sep_supported
    89        
    90                 movl $sep_msg, %esi
    91                 jmp error_halt
    92        
    93         sep_supported:
    94 
    9587#include "vesa_prot.inc"
    9688
    … …  
    225217        .asciz "Page Size Extension not supported. System halted."
    226218
    227 sep_msg:
    228         .asciz "SYSENTER/SYSEXIT not supported. System halted."

  • kernel/arch/ia32/src/cpu/cpu.c

    rba8f8cb rdb4d6de  
    9292void cpu_arch_init(void)
    9393{
    94         cpuid_feature_info fi;
    9594        cpuid_extended_feature_info efi;
    9695        cpu_info_t info;
    … …  
    102101        CPU->fpu_owner = NULL;
    103102       
    104         cpuid(1, &info);
     103        cpuid(INTEL_CPUID_STANDARD, &info);
    105104       
    106         fi.word = info.cpuid_edx;
     105        CPU->arch.fi.word = info.cpuid_edx;
    107106        efi.word = info.cpuid_ecx;
    108107       
    109         if (fi.bits.fxsr)
     108        if (CPU->arch.fi.bits.fxsr)
    110109                fpu_fxsr();
    111110        else
    112111                fpu_fsr();
    113112       
    114         if (fi.bits.sse) {
     113        if (CPU->arch.fi.bits.sse) {
    115114                asm volatile (
    116115                        "mov %%cr4, %[help]\n"
    … …  
    122121        }
    123122       
    124         /* Setup fast SYSENTER/SYSEXIT syscalls */
    125         syscall_setup_cpu();
     123        if (CPU->arch.fi.bits.sep) {
     124                /* Setup fast SYSENTER/SYSEXIT syscalls */
     125                syscall_setup_cpu();
     126        }
    126127}
    127128
    … …  
    132133        CPU->arch.vendor = VendorUnknown;
    133134        if (has_cpuid()) {
    134                 cpuid(0, &info);
     135                cpuid(INTEL_CPUID_LEVEL, &info);
    135136
    136137                /*
    … …  
    150151                        CPU->arch.vendor = VendorIntel;
    151152               
    152                 cpuid(1, &info);
     153                cpuid(INTEL_CPUID_STANDARD, &info);
    153154                CPU->arch.family = (info.cpuid_eax >> 8) & 0x0f;
    154155                CPU->arch.model = (info.cpuid_eax >> 4) & 0x0f;

  • kernel/arch/ia32/src/proc/scheduler.c

    rba8f8cb rdb4d6de  
    6161            SP_DELTA];
    6262       
    63         /* Set kernel stack for CP3 -> CPL0 switch via SYSENTER */
    64         write_msr(IA32_MSR_SYSENTER_ESP, kstk);
     63        if (CPU->arch.fi.bits.sep) {
     64                /* Set kernel stack for CP3 -> CPL0 switch via SYSENTER */
     65                write_msr(IA32_MSR_SYSENTER_ESP, kstk);
     66        }
    6567       
    6668        /* Set kernel stack for CPL3 -> CPL0 switch via interrupt */

  • kernel/arch/ia32/src/userspace.c

    rba8f8cb rdb4d6de  
    7070                "movl %[uarg], %%eax\n"
    7171               
    72                 /* %ebx is defined to hold pcb_ptr - set it to 0 */
    73                 "xorl %%ebx, %%ebx\n"
     72                /* %edi is defined to hold pcb_ptr - set it to 0 */
     73                "xorl %%edi, %%edi\n"
    7474               
    7575                "iret\n"

  • kernel/arch/mips32/include/mm/page.h

    rba8f8cb rdb4d6de  
    141141#include <arch/exception.h>
    142142
    143 static inline int get_pt_flags(pte_t *pt, size_t i)
     143/** Page Table Entry. */
     144typedef struct {
     145        unsigned g : 1;                 /**< Global bit. */
     146        unsigned p : 1;                 /**< Present bit. */
     147        unsigned d : 1;                 /**< Dirty bit. */
     148        unsigned cacheable : 1;         /**< Cacheable bit. */
     149        unsigned : 1;                   /**< Unused. */
     150        unsigned soft_valid : 1;        /**< Valid content even if not present. */
     151        unsigned pfn : 24;              /**< Physical frame number. */
     152        unsigned w : 1;                 /**< Page writable bit. */
     153        unsigned a : 1;                 /**< Accessed bit. */
     154} pte_t;
     155
     156
     157static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
    144158{
    145159        pte_t *p = &pt[i];

  • kernel/arch/mips32/include/types.h

    rba8f8cb rdb4d6de  
    8080#define PRIxn "x"       /**< Format for hexadecimal (u)native_t. */
    8181
    82 /** Page Table Entry. */
    83 typedef struct {
    84         unsigned g : 1;                 /**< Global bit. */
    85         unsigned p : 1;                 /**< Present bit. */
    86         unsigned d : 1;                 /**< Dirty bit. */
    87         unsigned cacheable : 1;         /**< Cacheable bit. */
    88         unsigned : 1;                   /**< Unused. */
    89         unsigned soft_valid : 1;        /**< Valid content even if not present. */
    90         unsigned pfn : 24;              /**< Physical frame number. */
    91         unsigned w : 1;                 /**< Page writable bit. */
    92         unsigned a : 1;                 /**< Accessed bit. */
    93 } pte_t;
    94 
    9582#endif
    9683

  • kernel/arch/ppc32/include/mm/page.h

    rba8f8cb rdb4d6de  
    131131#include <arch/interrupt.h>
    132132
    133 static inline int get_pt_flags(pte_t *pt, size_t i)
     133/** Page Table Entry. */
     134typedef struct {
     135        unsigned present : 1;             /**< Present bit. */
     136        unsigned page_write_through : 1;  /**< Write thought caching. */
     137        unsigned page_cache_disable : 1;  /**< No caching. */
     138        unsigned accessed : 1;            /**< Accessed bit. */
     139        unsigned global : 1;              /**< Global bit. */
     140        unsigned valid : 1;               /**< Valid content even if not present. */
     141        unsigned pfn : 20;                /**< Physical frame number. */
     142} pte_t;
     143
     144static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
    134145{
    135146        pte_t *p = &pt[i];

  • kernel/arch/ppc32/include/types.h

    rba8f8cb rdb4d6de  
    8282#define PRIxn "x"
    8383
    84 /** Page Table Entry. */
    85 typedef struct {
    86         unsigned present : 1;             /**< Present bit. */
    87         unsigned page_write_through : 1;  /**< Write thought caching. */
    88         unsigned page_cache_disable : 1;  /**< No caching. */
    89         unsigned accessed : 1;            /**< Accessed bit. */
    90         unsigned global : 1;              /**< Global bit. */
    91         unsigned valid : 1;               /**< Valid content even if not present. */
    92         unsigned pfn : 20;                /**< Physical frame number. */
    93 } pte_t;
    94 
    9584#endif
    9685
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