Index: kernel/arch/sparc64/include/arch/asm.h
===================================================================
--- kernel/arch/sparc64/include/arch/asm.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/include/arch/asm.h	(revision db3c88347157ed2aeffe98179283d9e4e0243edd)
@@ -91,10 +91,10 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"rdpr %%pstate, %[v]\n"
 		: [v] "=r" (v)
 	);
-	
+
 	return v;
 }
@@ -122,10 +122,10 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"rd %%tick_cmpr, %[v]\n"
 		: [v] "=r" (v)
 	);
-	
+
 	return v;
 }
@@ -153,10 +153,10 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"rd %%asr25, %[v]\n"
 		: [v] "=r" (v)
 	);
-	
+
 	return v;
 }
@@ -184,10 +184,10 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"rdpr %%tick, %[v]\n"
 		: [v] "=r" (v)
 	);
-	
+
 	return v;
 }
@@ -215,10 +215,10 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"rd %%fprs, %[v]\n"
 		: [v] "=r" (v)
 	);
-	
+
 	return v;
 }
@@ -246,10 +246,10 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"rd %%softint, %[v]\n"
 		: [v] "=r" (v)
 	);
-	
+
 	return v;
 }
@@ -312,9 +312,9 @@
 	pstate_reg_t pstate;
 	uint64_t value = pstate_read();
-	
+
 	pstate.value = value;
 	pstate.ie = true;
 	pstate_write(pstate.value);
-	
+
 	return (ipl_t) value;
 }
@@ -331,9 +331,9 @@
 	pstate_reg_t pstate;
 	uint64_t value = pstate_read();
-	
+
 	pstate.value = value;
 	pstate.ie = false;
 	pstate_write(pstate.value);
-	
+
 	return (ipl_t) value;
 }
@@ -348,5 +348,5 @@
 NO_TRACE static inline void interrupts_restore(ipl_t ipl) {
 	pstate_reg_t pstate;
-	
+
 	pstate.value = pstate_read();
 	pstate.ie = ((pstate_reg_t)(uint64_t) ipl).ie;
@@ -373,5 +373,5 @@
 {
 	pstate_reg_t pstate;
-	
+
 	pstate.value = pstate_read();
 	return !pstate.ie;
@@ -388,5 +388,5 @@
 {
 	uintptr_t unbiased_sp;
-	
+
 	asm volatile (
 		"add %%sp, %[stack_bias], %[unbiased_sp]\n"
@@ -394,5 +394,5 @@
 		: [stack_bias] "i" (STACK_BIAS)
 	);
-	
+
 	return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
 }
@@ -406,10 +406,10 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"rdpr %%ver, %[v]\n"
 		: [v] "=r" (v)
 	);
-	
+
 	return v;
 }
@@ -423,10 +423,10 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"rdpr %%tpc, %[v]\n"
 		: [v] "=r" (v)
 	);
-	
+
 	return v;
 }
@@ -440,10 +440,10 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"rdpr %%tl, %[v]\n"
 		: [v] "=r" (v)
 	);
-	
+
 	return v;
 }
@@ -457,10 +457,10 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"rdpr %%tba, %[v]\n"
 		: [v] "=r" (v)
 	);
-	
+
 	return v;
 }
@@ -492,5 +492,5 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"ldxa [%[va]] %[asi], %[v]\n"
@@ -499,5 +499,5 @@
 		  [asi] "i" ((unsigned int) asi)
 	);
-	
+
 	return v;
 }
Index: kernel/arch/sparc64/include/arch/atomic.h
===================================================================
--- kernel/arch/sparc64/include/arch/atomic.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/include/arch/atomic.h	(revision db3c88347157ed2aeffe98179283d9e4e0243edd)
@@ -56,11 +56,11 @@
 	atomic_count_t a;
 	atomic_count_t b;
-	
+
 	do {
 		volatile uintptr_t ptr = (uintptr_t) &val->count;
-		
+
 		a = *((atomic_count_t *) ptr);
 		b = a + i;
-		
+
 		asm volatile (
 			"casx %0, %2, %1\n"
@@ -70,5 +70,5 @@
 		);
 	} while (a != b);
-	
+
 	return a;
 }
@@ -108,5 +108,5 @@
 	atomic_count_t v = 1;
 	volatile uintptr_t ptr = (uintptr_t) &val->count;
-	
+
 	asm volatile (
 		"casx %0, %2, %1\n"
@@ -115,5 +115,5 @@
 	    : "r" (0)
 	);
-	
+
 	return v;
 }
@@ -123,9 +123,9 @@
 	atomic_count_t tmp1 = 1;
 	atomic_count_t tmp2 = 0;
-	
+
 	volatile uintptr_t ptr = (uintptr_t) &val->count;
-	
+
 	preemption_disable();
-	
+
 	asm volatile (
 		"0:\n"
@@ -144,5 +144,5 @@
 		: "r" (0)
 	);
-	
+
 	/*
 	 * Prevent critical section code from bleeding out this way up.
Index: kernel/arch/sparc64/include/arch/barrier.h
===================================================================
--- kernel/arch/sparc64/include/arch/barrier.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/include/arch/barrier.h	(revision db3c88347157ed2aeffe98179283d9e4e0243edd)
@@ -83,5 +83,5 @@
 {
 	unsigned long pc;
-	
+
 	/*
 	 * The FLUSH instruction takes address parameter.
@@ -94,5 +94,5 @@
 	 *
 	 */
-	
+
 	asm volatile (
 		"rd %%pc, %[pc]\n"
Index: kernel/arch/sparc64/include/arch/cpu_family.h
===================================================================
--- kernel/arch/sparc64/include/arch/cpu_family.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/include/arch/cpu_family.h	(revision db3c88347157ed2aeffe98179283d9e4e0243edd)
@@ -76,5 +76,5 @@
 	return (impl == IMPL_ULTRASPARCIV) || (impl == IMPL_ULTRASPARCIV_PLUS);
 }
-	
+
 #endif
 
Index: kernel/arch/sparc64/include/arch/mm/sun4u/mmu.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4u/mmu.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/include/arch/mm/sun4u/mmu.h	(revision db3c88347157ed2aeffe98179283d9e4e0243edd)
@@ -111,5 +111,5 @@
 		unsigned dc : 1;	/**< D-Cache enable. */
 		unsigned ic : 1;	/**< I-Cache enable. */
-		
+
 	} __attribute__ ((packed));
 } lsu_cr_reg_t;
Index: kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h	(revision db3c88347157ed2aeffe98179283d9e4e0243edd)
@@ -79,5 +79,5 @@
 #define TLB_DBIG_0	2
 #define TLB_DBIG_1	3
-	
+
 /* I-MMU: one small (16-entry) TLB and one big TLB */
 #define TLB_ISMALL	0
@@ -327,5 +327,5 @@
 {
 	itlb_data_access_addr_t reg;
-	
+
 	reg.value = 0;
 	reg.tlb_entry = entry;
@@ -341,5 +341,5 @@
 {
 	itlb_data_access_addr_t reg;
-	
+
 	reg.value = 0;
 	reg.tlb_entry = entry;
@@ -358,5 +358,5 @@
 {
 	dtlb_data_access_addr_t reg;
-	
+
 	reg.value = 0;
 	reg.tlb_entry = entry;
@@ -372,5 +372,5 @@
 {
 	dtlb_data_access_addr_t reg;
-	
+
 	reg.value = 0;
 	reg.tlb_entry = entry;
@@ -423,5 +423,5 @@
 {
 	itlb_data_access_addr_t reg;
-	
+
 	reg.value = 0;
 	reg.tlb_number = tlb;
@@ -439,5 +439,5 @@
 {
 	itlb_data_access_addr_t reg;
-	
+
 	reg.value = 0;
 	reg.tlb_number = tlb;
@@ -458,5 +458,5 @@
 {
 	dtlb_data_access_addr_t reg;
-	
+
 	reg.value = 0;
 	reg.tlb_number = tlb;
@@ -475,5 +475,5 @@
 {
 	dtlb_data_access_addr_t reg;
-	
+
 	reg.value = 0;
 	reg.tlb_number = tlb;
@@ -638,12 +638,12 @@
 	tlb_demap_addr_t da;
 	page_address_t pg;
-	
+
 	da.value = 0;
 	pg.address = page;
-	
+
 	da.type = type;
 	da.context = context_encoding;
 	da.vpn = pg.vpn;
-	
+
 	/* da.value is the address within the ASI */
 	asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
@@ -664,12 +664,12 @@
 	tlb_demap_addr_t da;
 	page_address_t pg;
-	
+
 	da.value = 0;
 	pg.address = page;
-	
+
 	da.type = type;
 	da.context = context_encoding;
 	da.vpn = pg.vpn;
-	
+
 	/* da.value is the address within the ASI */
 	asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
Index: kernel/arch/sparc64/include/arch/mm/sun4v/mmu.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4v/mmu.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/include/arch/mm/sun4v/mmu.h	(revision db3c88347157ed2aeffe98179283d9e4e0243edd)
@@ -41,5 +41,5 @@
 #define VA_PRIMARY_CONTEXT_REG		0x8	/**< primary context register VA. */
 #define ASI_PRIMARY_CONTEXT_REG		0x21	/**< primary context register ASI. */
- 
+
 #define VA_SECONDARY_CONTEXT_REG	0x10	/**< secondary context register VA. */
 #define ASI_SECONDARY_CONTEXT_REG	0x21	/**< secondary context register ASI. */
Index: kernel/arch/sparc64/include/arch/sun4u/asm.h
===================================================================
--- kernel/arch/sparc64/include/arch/sun4u/asm.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/include/arch/sun4u/asm.h	(revision db3c88347157ed2aeffe98179283d9e4e0243edd)
@@ -46,10 +46,10 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"rdpr %%ver, %[v]\n"
 		: [v] "=r" (v)
 	);
-	
+
 	return v;
 }
Index: kernel/arch/sparc64/include/arch/sun4u/cpu.h
===================================================================
--- kernel/arch/sparc64/include/arch/sun4u/cpu.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/include/arch/sun4u/cpu.h	(revision db3c88347157ed2aeffe98179283d9e4e0243edd)
@@ -78,5 +78,5 @@
 	uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0);
 	icbus_config = icbus_config >> ICBUS_CONFIG_MID_SHIFT;
-	
+
 #if defined (US)
 	return icbus_config & 0x1f;
Index: kernel/arch/sparc64/include/arch/sun4v/hypercall.h
===================================================================
--- kernel/arch/sparc64/include/arch/sun4v/hypercall.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/sparc64/include/arch/sun4v/hypercall.h	(revision db3c88347157ed2aeffe98179283d9e4e0243edd)
@@ -105,5 +105,5 @@
 	set function_number, %o5; \
 	ta FAST_TRAP;
-	
+
 /**
  * Performs a fast hypervisor API call from the assembly language code.
@@ -197,5 +197,5 @@
 	register uint64_t a4 asm("o3") = p4;
 	register uint64_t a5 asm("o4") = p5;
-	
+
 	asm volatile (
 		"ta %8\n"
@@ -239,5 +239,5 @@
 		: "memory"
 	);
-	
+
 	return a1;
 }