Index: kernel/arch/ppc32/include/arch/asm.h
===================================================================
--- kernel/arch/ppc32/include/arch/asm.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ppc32/include/arch/asm.h	(revision db3c88347157ed2aeffe98179283d9e4e0243edd)
@@ -45,10 +45,10 @@
 {
 	uint32_t msr;
-	
+
 	asm volatile (
 		"mfmsr %[msr]\n"
 		: [msr] "=r" (msr)
 	);
-	
+
 	return msr;
 }
@@ -77,5 +77,5 @@
 {
 	uint32_t vsid;
-	
+
 	asm volatile (
 		"mfsrin %[vsid], %[vaddr]\n"
@@ -83,5 +83,5 @@
 		: [vaddr] "r" (vaddr)
 	);
-	
+
 	return vsid;
 }
@@ -90,10 +90,10 @@
 {
 	uint32_t sdr1;
-	
+
 	asm volatile (
 		"mfsdr1 %[sdr1]\n"
 		: [sdr1] "=r" (sdr1)
 	);
-	
+
 	return sdr1;
 }
@@ -173,5 +173,5 @@
 {
 	uintptr_t base;
-	
+
 	asm volatile (
 		"and %[base], %%sp, %[mask]\n"
@@ -179,5 +179,5 @@
 		: [mask] "r" (~(STACK_SIZE - 1))
 	);
-	
+
 	return base;
 }
Index: kernel/arch/ppc32/include/arch/atomic.h
===================================================================
--- kernel/arch/ppc32/include/arch/atomic.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ppc32/include/arch/atomic.h	(revision db3c88347157ed2aeffe98179283d9e4e0243edd)
@@ -41,5 +41,5 @@
 {
 	atomic_count_t tmp;
-	
+
 	asm volatile (
 		"1:\n"
@@ -59,5 +59,5 @@
 {
 	atomic_count_t tmp;
-	
+
 	asm volatile (
 		"1:\n"
Index: kernel/arch/ppc32/include/arch/barrier.h
===================================================================
--- kernel/arch/ppc32/include/arch/barrier.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ppc32/include/arch/barrier.h	(revision db3c88347157ed2aeffe98179283d9e4e0243edd)
@@ -77,5 +77,5 @@
 {
 	unsigned int i;
-	
+
 	for (i = 0; i < len; i += COHERENCE_INVAL_MIN)
 		asm volatile (
@@ -83,7 +83,7 @@
 			:: [addr] "r" (addr + i)
 		);
-	
+
 	memory_barrier();
-	
+
 	for (i = 0; i < len; i += COHERENCE_INVAL_MIN)
 		asm volatile (
@@ -91,5 +91,5 @@
 			:: [addr] "r" (addr + i)
 		);
-	
+
 	instruction_barrier();
 }
Index: kernel/arch/ppc32/include/arch/cycle.h
===================================================================
--- kernel/arch/ppc32/include/arch/cycle.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ppc32/include/arch/cycle.h	(revision db3c88347157ed2aeffe98179283d9e4e0243edd)
@@ -43,5 +43,5 @@
 	uint32_t upper;
 	uint32_t tmp;
-	
+
 	do {
 		asm volatile (
@@ -54,5 +54,5 @@
 		);
 	} while (upper != tmp);
-	
+
 	return ((uint64_t) upper << 32) + (uint64_t) lower;
 }
Index: kernel/arch/ppc32/include/arch/mm/frame.h
===================================================================
--- kernel/arch/ppc32/include/arch/mm/frame.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ppc32/include/arch/mm/frame.h	(revision db3c88347157ed2aeffe98179283d9e4e0243edd)
@@ -49,10 +49,10 @@
 {
 	uint32_t physmem;
-	
+
 	asm volatile (
 		"mfsprg3 %[physmem]\n"
 		: [physmem] "=r" (physmem)
 	);
-	
+
 	return physmem;
 }
Index: kernel/arch/ppc32/include/arch/mm/page.h
===================================================================
--- kernel/arch/ppc32/include/arch/mm/page.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ppc32/include/arch/mm/page.h	(revision db3c88347157ed2aeffe98179283d9e4e0243edd)
@@ -165,5 +165,5 @@
 {
 	pte_t *entry = &pt[i];
-	
+
 	return (((!entry->page_cache_disable) << PAGE_CACHEABLE_SHIFT) |
 	    ((!entry->present) << PAGE_PRESENT_SHIFT) |
@@ -178,5 +178,5 @@
 {
 	pte_t *entry = &pt[i];
-	
+
 	entry->page_cache_disable = !(flags & PAGE_CACHEABLE);
 	entry->present = !(flags & PAGE_NOT_PRESENT);