Index: kernel/arch/mips32/include/arch/asm.h
===================================================================
--- kernel/arch/mips32/include/arch/asm.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/mips32/include/arch/asm.h	(revision db3c88347157ed2aeffe98179283d9e4e0243edd)
@@ -55,5 +55,5 @@
 {
 	uintptr_t base;
-	
+
 	asm volatile (
 		"and %[base], $29, %[mask]\n"
@@ -61,5 +61,5 @@
 		: [mask] "r" (~(STACK_SIZE - 1))
 	);
-	
+
 	return base;
 }
Index: kernel/arch/mips32/include/arch/atomic.h
===================================================================
--- kernel/arch/mips32/include/arch/atomic.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/mips32/include/arch/atomic.h	(revision db3c88347157ed2aeffe98179283d9e4e0243edd)
@@ -60,5 +60,5 @@
 	atomic_count_t tmp;
 	atomic_count_t v;
-	
+
 	asm volatile (
 		"1:\n"
@@ -75,5 +75,5 @@
 		  "i" (0)
 	);
-	
+
 	return v;
 }
@@ -83,5 +83,5 @@
 	atomic_count_t tmp;
 	atomic_count_t v;
-	
+
 	asm volatile (
 		"1:\n"
@@ -98,5 +98,5 @@
 		: "i" (1)
 	);
-	
+
 	return v;
 }
Index: kernel/arch/mips32/include/arch/mm/page.h
===================================================================
--- kernel/arch/mips32/include/arch/mm/page.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/mips32/include/arch/mm/page.h	(revision db3c88347157ed2aeffe98179283d9e4e0243edd)
@@ -165,5 +165,5 @@
 {
 	pte_t *p = &pt[i];
-	
+
 	return ((p->cacheable << PAGE_CACHEABLE_SHIFT) |
 	    ((!p->p) << PAGE_PRESENT_SHIFT) |
@@ -178,10 +178,10 @@
 {
 	pte_t *p = &pt[i];
-	
+
 	p->cacheable = (flags & PAGE_CACHEABLE) != 0;
 	p->p = !(flags & PAGE_NOT_PRESENT);
 	p->g = (flags & PAGE_GLOBAL) != 0;
 	p->w = (flags & PAGE_WRITE) != 0;
-	
+
 	/*
 	 * Ensure that valid entries have at least one bit set.