Index: arch/ia32/_link.ld
===================================================================
--- arch/ia32/_link.ld	(revision 93ca46f7db9fa7b986fd58472ab20b5b0321e051)
+++ arch/ia32/_link.ld	(revision da585a52045238cf4d613295769429747b2a4670)
@@ -1,4 +1,3 @@
-/*
- *  ia32 linker script
+/** IA-32 linker script
  *  
  *  kernel text
Index: arch/ia32/src/asm.s
===================================================================
--- arch/ia32/src/asm.s	(revision 93ca46f7db9fa7b986fd58472ab20b5b0321e051)
+++ arch/ia32/src/asm.s	(revision da585a52045238cf4d613295769429747b2a4670)
@@ -27,5 +27,5 @@
 #
 
-# very low and hardware-level functions
+## very low and hardware-level functions
 
 .text
@@ -54,6 +54,10 @@
 .global memcmp
 
-#
-# set priority level high
+
+## Set priority level high
+#
+# Disable interrupts and return previous
+# EFLAGS in EAX.
+#
 cpu_priority_high:
 	pushf
@@ -61,7 +65,11 @@
 	cli
 	ret
-    
-#
-# set priority level low
+
+
+## Set priority level low
+#
+# Enable interrupts and return previous
+# EFLAGS in EAX.
+#    
 cpu_priority_low:
         pushf
@@ -70,6 +78,9 @@
 	ret
 
-#
-# restore priority level
+
+## Restore priority level
+#
+# Restore EFLAGS.
+#
 cpu_priority_restore:
 	push 4(%esp)
@@ -77,5 +88,8 @@
 	ret
 
-# return raw priority level
+## Return raw priority level
+#
+# Return EFLAFS in EAX.
+#
 cpu_priority_read:
 	pushf
@@ -83,4 +97,9 @@
 	ret
 
+
+## Halt the CPU
+#
+# Halt the CPU using HLT.
+#
 cpu_halt:
 cpu_sleep:
@@ -88,4 +107,9 @@
 	ret
 
+
+## Turn paging on
+#
+# Enable paging and write-back caching in CR0.
+#
 paging_on:
 	pushl %eax
@@ -99,8 +123,18 @@
 	ret
 
+
+## Read CR3
+#
+# Store CR3 in EAX.
+#
 cpu_read_dba:
 	movl %cr3,%eax
 	ret
 
+
+## Write CR3
+#
+# Set CR3.
+#
 cpu_write_dba:
 	pushl %eax
@@ -110,8 +144,18 @@
 	ret
 
+
+## Read CR2
+#
+# Store CR2 in EAX.
+#
 cpu_read_cr2:
 	movl %cr2,%eax
 	ret
 
+
+## Enable local APIC
+#
+# Enable local APIC in MSR.
+#
 enable_l_apic_in_msr:
 	pusha
@@ -126,4 +170,13 @@
 	ret
 
+
+## Declare interrupt handlers
+#
+# Declare interrupt handlers for n interrupt
+# vectors starting at vector i.
+#
+# The handlers setup data segment registers
+# and call trap_dispatcher().
+#
 .macro handler i n
 	push %ebp
@@ -170,4 +223,8 @@
 
 
+## I/O input (byte)
+#
+# Get a byte from I/O port and store it AL.
+#
 inb:
 	push %edx
@@ -178,4 +235,9 @@
 	ret
 
+
+## I/O input (word)
+#
+# Get a word from I/O port and store it AX.
+#
 inw:
 	push %edx
@@ -186,4 +248,9 @@
 	ret
 
+
+## I/O input (dword)
+#
+# Get a dword from I/O port and store it EAX.
+#
 inl:
 	push %edx
@@ -194,4 +261,9 @@
 	ret
 
+
+## I/O output (byte)
+#
+# Send a byte to I/O port.
+#
 outb:
 	push %ebp
@@ -207,4 +279,9 @@
 	ret
 
+
+## I/O output (word)
+#
+# Send a word to I/O port.
+#
 outw:
 	push %ebp
@@ -220,4 +297,9 @@
 	ret
 
+
+## I/O output (dword)
+#
+# Send a dword to I/O port.
+#
 outl:
 	push %ebp
@@ -233,4 +315,12 @@
 	ret
 
+
+## Copy memory
+#
+# Copy a given number of bytes (3rd argument)
+# from the memory location defined by 1st argument
+# to the memory location defined by 2nd argument.
+# The memory areas cannot overlap.
+#
 SRC=8
 DST=12
@@ -252,4 +342,37 @@
 	ret
 
+
+## Fill memory with bytes
+#
+# Fill a given number of bytes (2nd argument)
+# at memory defined by 1st argument with the
+# byte value defined by 3rd argument.
+#
+DST=8
+CNT=12
+X=16
+memsetb:
+	push %ebp
+	movl %esp,%ebp
+	pusha
+    
+	cld
+	movl CNT(%ebp),%ecx
+	movl DST(%ebp),%edi
+	movl X(%ebp),%eax
+    
+	rep stosb %al,%es:(%edi)
+    
+        popa
+	pop %ebp
+	ret
+
+
+## Fill memory with words
+#
+# Fill a given number of words (2nd argument)
+# at memory defined by 1st argument with the
+# word value defined by 3rd argument.
+#
 DST=8
 CNT=12
@@ -271,23 +394,12 @@
 	ret
 
-DST=8
-CNT=12
-X=16
-memsetb:
-	push %ebp
-	movl %esp,%ebp
-	pusha
-    
-	cld
-	movl CNT(%ebp),%ecx
-	movl DST(%ebp),%edi
-	movl X(%ebp),%eax
-    
-	rep stosb %al,%es:(%edi)
-    
-        popa
-	pop %ebp
-	ret
-
+
+## Compare memory regions for equality
+#
+# Compare a given number of bytes (3rd argument)
+# at memory locations defined by 1st and 2nd argument
+# for equality. If the bytes are equal, EAX contains
+# 0.
+#
 SRC=12
 DST=16
Index: arch/ia32/src/context.s
===================================================================
--- arch/ia32/src/context.s	(revision 93ca46f7db9fa7b986fd58472ab20b5b0321e051)
+++ arch/ia32/src/context.s	(revision da585a52045238cf4d613295769429747b2a4670)
@@ -36,6 +36,10 @@
 .global fpu_lazy_context_restore
 
+
+## Save current CPU context
 #
-# save context of this CPU
+# Save CPU context to the kernel_context variable
+# pointed by the 1st argument. Returns 1 in EAX.
+#
 context_save:
 	push %ebx
@@ -59,7 +63,11 @@
 	incl %eax
 	ret
-    
+
+
+## Restore current CPU context
 #
-# restore saved context on this CPU
+# Restore CPU context from the kernel_context variable
+# pointed by the 1st argument. Returns 0 in EAX.
+#    
 context_restore:
 	movl 4(%esp),%eax	# address of the kernel_context variable to restore context from
@@ -78,4 +86,2 @@
         xorl %eax,%eax		# context_restore returns 0
 	ret
-
-
Index: arch/ia32/src/cpuid.s
===================================================================
--- arch/ia32/src/cpuid.s	(revision 93ca46f7db9fa7b986fd58472ab20b5b0321e051)
+++ arch/ia32/src/cpuid.s	(revision da585a52045238cf4d613295769429747b2a4670)
@@ -27,6 +27,4 @@
 #
 
-#
-# CPU identification functions.
 # The code below just interfaces the CPUID instruction.
 # CPU recognition logic is contained in higher-level functions.
@@ -38,4 +36,9 @@
 .global rdtsc
 
+
+## Determine CPUID support
+#
+# Return 0 in EAX if CPUID is not support, 1 if supported.
+#
 has_cpuid:
 	push %ebx
@@ -56,5 +59,16 @@
 	ret
 
-# cpuid(__u32 cmd, struct cpu_info *info)
+
+## Get CPUID data
+#
+# This code is just an interfaces the CPUID instruction, CPU recognition
+# logic is contained in higher-level functions.
+#
+# The C prototype is:
+#   void cpuid(__u32 cmd, struct cpu_info *info)
+#
+# @param cmd  CPUID command.
+# @param info Buffer to store CPUID output.
+#
 cpuid:
 	pushl %ebp
Index: arch/ia32/src/userspace.c
===================================================================
--- arch/ia32/src/userspace.c	(revision 93ca46f7db9fa7b986fd58472ab20b5b0321e051)
+++ arch/ia32/src/userspace.c	(revision da585a52045238cf4d613295769429747b2a4670)
@@ -34,4 +34,10 @@
 #include <mm/vm.h>
 
+
+/** Enter userspace
+ *
+ * Change CPU protection level to 3, enter userspace.
+ *
+ */
 void userspace(void)
 {
@@ -48,6 +54,6 @@
 	    "iret"
 	    : : "i" (selector(UDATA_DES) | PL_USER), "i" (USTACK_ADDRESS+THREAD_STACK_SIZE-1000), "r" (pri), "i" (selector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS));
-	/* NOT REACHED */
-
+	
+	/* Unreachable */
 	for(;;);
 }
