Index: kernel/arch/amd64/include/debugger.h =================================================================== --- kernel/arch/amd64/include/debugger.h (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/amd64/include/debugger.h (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -38,17 +38,17 @@ #include -#define BKPOINTS_MAX 4 +#define BKPOINTS_MAX 4 /* Flags that are passed to breakpoint_add function */ -#define BKPOINT_INSTR 0x1 -#define BKPOINT_WRITE 0x2 -#define BKPOINT_READ_WRITE 0x4 +#define BKPOINT_INSTR 0x1 +#define BKPOINT_WRITE 0x2 +#define BKPOINT_READ_WRITE 0x4 -#define BKPOINT_CHECK_ZERO 0x8 +#define BKPOINT_CHECK_ZERO 0x8 extern void debugger_init(void); -extern int breakpoint_add(const void *where, const int flags, int curidx); -extern void breakpoint_del(int slot); +extern int breakpoint_add(const void *, const unsigned int, int); +extern void breakpoint_del(int); #endif Index: kernel/arch/amd64/src/ddi/ddi.c =================================================================== --- kernel/arch/amd64/src/ddi/ddi.c (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/amd64/src/ddi/ddi.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -49,30 +49,27 @@ * Interrupts are disabled and task is locked. * - * @param task Task. + * @param task Task. * @param ioaddr Startign I/O space address. - * @param size Size of the enabled I/O range. + * @param size Size of the enabled I/O range. * * @return 0 on success or an error code from errno.h. + * */ int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size) { - size_t bits; - - bits = ioaddr + size; + size_t bits = ioaddr + size; if (bits > IO_PORTS) return ENOENT; if (task->arch.iomap.bits < bits) { - bitmap_t oldiomap; - uint8_t *newmap; - /* * The I/O permission bitmap is too small and needs to be grown. */ - newmap = (uint8_t *) malloc(BITS2BYTES(bits), FRAME_ATOMIC); + uint8_t *newmap = (uint8_t *) malloc(BITS2BYTES(bits), FRAME_ATOMIC); if (!newmap) return ENOMEM; + bitmap_t oldiomap; bitmap_initialize(&oldiomap, task->arch.iomap.map, task->arch.iomap.bits); @@ -115,23 +112,20 @@ * * Interrupts must be disabled prior this call. + * */ void io_perm_bitmap_install(void) { - size_t bits; - ptr_16_64_t cpugdtr; - descriptor_t *gdt_p; - tss_descriptor_t *tss_desc; - size_t ver; - /* First, copy the I/O Permission Bitmap. */ - spinlock_lock(&TASK->lock); - ver = TASK->arch.iomapver; - if ((bits = TASK->arch.iomap.bits)) { + irq_spinlock_lock(&TASK->lock, false); + size_t ver = TASK->arch.iomapver; + size_t bits = TASK->arch.iomap.bits; + if (bits) { + ASSERT(TASK->arch.iomap.map); + bitmap_t iomap; - - ASSERT(TASK->arch.iomap.map); bitmap_initialize(&iomap, CPU->arch.tss->iomap, TSS_IOMAP_SIZE * 8); bitmap_copy(&iomap, &TASK->arch.iomap, TASK->arch.iomap.bits); + /* * It is safe to set the trailing eight bits because of the @@ -140,5 +134,5 @@ bitmap_set_range(&iomap, ALIGN_UP(TASK->arch.iomap.bits, 8), 8); } - spinlock_unlock(&TASK->lock); + irq_spinlock_unlock(&TASK->lock, false); /* @@ -146,6 +140,8 @@ * Take the extra ending byte will all bits set into account. */ + ptr_16_64_t cpugdtr; gdtr_store(&cpugdtr); - gdt_p = (descriptor_t *) cpugdtr.base; + + descriptor_t *gdt_p = (descriptor_t *) cpugdtr.base; gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + BITS2BYTES(bits)); gdtr_load(&cpugdtr); @@ -155,5 +151,5 @@ * type must be changed to describe inactive TSS. */ - tss_desc = (tss_descriptor_t *) &gdt_p[TSS_DES]; + tss_descriptor_t *tss_desc = (tss_descriptor_t *) &gdt_p[TSS_DES]; tss_desc->type = AR_TSS; tr_load(gdtselector(TSS_DES)); Index: kernel/arch/amd64/src/debugger.c =================================================================== --- kernel/arch/amd64/src/debugger.c (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/amd64/src/debugger.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -46,16 +46,27 @@ #include +#ifdef __64_BITS__ + #define getip(x) ((x)->rip) +#endif + +#ifdef __32_BITS__ + #define getip(x) ((x)->eip) +#endif + typedef struct { - uintptr_t address; /**< Breakpoint address */ - int flags; /**< Flags regarding breakpoint */ - int counter; /**< How many times the exception occured */ + uintptr_t address; /**< Breakpoint address */ + unsigned int flags; /**< Flags regarding breakpoint */ + size_t counter; /**< How many times the exception occured */ } bpinfo_t; static bpinfo_t breakpoints[BKPOINTS_MAX]; -SPINLOCK_INITIALIZE(bkpoint_lock); +IRQ_SPINLOCK_STATIC_INITIALIZE(bkpoint_lock); #ifdef CONFIG_KCONSOLE -static int cmd_print_breakpoints(cmd_arg_t *argv); +static int cmd_print_breakpoints(cmd_arg_t *); +static int cmd_del_breakpoint(cmd_arg_t *); +static int cmd_add_breakpoint(cmd_arg_t *); + static cmd_info_t bkpts_info = { .name = "bkpts", @@ -65,11 +76,11 @@ }; -static int cmd_del_breakpoint(cmd_arg_t *argv); static cmd_arg_t del_argv = { .type = ARG_TYPE_INT }; + static cmd_info_t delbkpt_info = { .name = "delbkpt", - .description = "delbkpt - Delete breakpoint.", + .description = "Delete breakpoint.", .func = cmd_del_breakpoint, .argc = 1, @@ -77,11 +88,11 @@ }; -static int cmd_add_breakpoint(cmd_arg_t *argv); static cmd_arg_t add_argv = { .type = ARG_TYPE_INT }; + static cmd_info_t addbkpt_info = { .name = "addbkpt", - .description = "addbkpt <&symbol> - new breakpoint.", + .description = "Add breakpoint.", .func = cmd_add_breakpoint, .argc = 1, @@ -92,7 +103,8 @@ .type = ARG_TYPE_INT }; + static cmd_info_t addwatchp_info = { .name = "addwatchp", - .description = "addbwatchp <&symbol> - new write watchpoint.", + .description = "Add write watchpoint.", .func = cmd_add_breakpoint, .argc = 1, @@ -102,16 +114,20 @@ #endif /* CONFIG_KCONSOLE */ -/* Setup DR register according to table */ +/** Setup DR register according to table + * + */ static void setup_dr(int curidx) { - unative_t dr7; + ASSERT(curidx >= 0); + bpinfo_t *cur = &breakpoints[curidx]; - int flags = breakpoints[curidx].flags; - + unsigned int flags = breakpoints[curidx].flags; + /* Disable breakpoint in DR7 */ - dr7 = read_dr7(); - dr7 &= ~(0x2 << (curidx*2)); - - if (cur->address) { /* Setup DR register */ + unative_t dr7 = read_dr7(); + dr7 &= ~(0x2 << (curidx * 2)); + + /* Setup DR register */ + if (cur->address) { /* Set breakpoint to debug registers */ switch (curidx) { @@ -129,15 +145,14 @@ break; } + /* Set type to requested breakpoint & length*/ - dr7 &= ~ (0x3 << (16 + 4*curidx)); - dr7 &= ~ (0x3 << (18 + 4*curidx)); - if ((flags & BKPOINT_INSTR)) { - ; - } else { + dr7 &= ~(0x3 << (16 + 4 * curidx)); + dr7 &= ~(0x3 << (18 + 4 * curidx)); + if (!(flags & BKPOINT_INSTR)) { #ifdef __32_BITS__ dr7 |= ((unative_t) 0x3) << (18 + 4 * curidx); #endif - + #ifdef __64_BITS__ dr7 |= ((unative_t) 0x2) << (18 + 4 * curidx); @@ -149,76 +164,70 @@ dr7 |= ((unative_t) 0x3) << (16 + 4 * curidx); } - + /* Enable global breakpoint */ dr7 |= 0x2 << (curidx * 2); - + write_dr7(dr7); - - } -} - + } +} + /** Enable hardware breakpoint * * @param where Address of HW breakpoint * @param flags Type of breakpoint (EXECUTE, WRITE) + * * @return Debug slot on success, -1 - no available HW breakpoint - */ -int breakpoint_add(const void *where, const int flags, int curidx) -{ - ipl_t ipl; - int i; - bpinfo_t *cur; - + * + */ +int breakpoint_add(const void *where, const unsigned int flags, int curidx) +{ ASSERT(flags & (BKPOINT_INSTR | BKPOINT_WRITE | BKPOINT_READ_WRITE)); - - ipl = interrupts_disable(); - spinlock_lock(&bkpoint_lock); + + irq_spinlock_lock(&bkpoint_lock, true); if (curidx == -1) { /* Find free space in slots */ - for (i = 0; i < BKPOINTS_MAX; i++) + unsigned int i; + for (i = 0; i < BKPOINTS_MAX; i++) { if (!breakpoints[i].address) { curidx = i; break; } + } + if (curidx == -1) { /* Too many breakpoints */ - spinlock_unlock(&bkpoint_lock); - interrupts_restore(ipl); + irq_spinlock_unlock(&bkpoint_lock, true); return -1; } } - cur = &breakpoints[curidx]; - + + bpinfo_t *cur = &breakpoints[curidx]; + cur->address = (uintptr_t) where; cur->flags = flags; cur->counter = 0; - + setup_dr(curidx); - - spinlock_unlock(&bkpoint_lock); - interrupts_restore(ipl); - + + irq_spinlock_unlock(&bkpoint_lock, true); + /* Send IPI */ // ipi_broadcast(VECTOR_DEBUG_IPI); - + return curidx; } -#ifdef __64_BITS__ - #define getip(x) ((x)->rip) -#else - #define getip(x) ((x)->eip) -#endif - static void handle_exception(int slot, istate_t *istate) { + ASSERT(slot >= 0); ASSERT(breakpoints[slot].address); - + /* Handle zero checker */ - if (! (breakpoints[slot].flags & BKPOINT_INSTR)) { + if (!(breakpoints[slot].flags & BKPOINT_INSTR)) { if ((breakpoints[slot].flags & BKPOINT_CHECK_ZERO)) { if (*((unative_t *) breakpoints[slot].address) != 0) return; + printf("*** Found ZERO on address %lx (slot %d) ***\n", breakpoints[slot].address, slot); @@ -228,8 +237,8 @@ } } - + printf("Reached breakpoint %d:%lx (%s)\n", slot, getip(istate), symtab_fmt_name_lookup(getip(istate))); - + #ifdef CONFIG_KCONSOLE atomic_set(&haltstate, 1); @@ -241,42 +250,37 @@ void breakpoint_del(int slot) { - bpinfo_t *cur; - ipl_t ipl; - - ipl = interrupts_disable(); - spinlock_lock(&bkpoint_lock); - - cur = &breakpoints[slot]; + ASSERT(slot >= 0); + + irq_spinlock_lock(&bkpoint_lock, true); + + bpinfo_t *cur = &breakpoints[slot]; if (!cur->address) { - spinlock_unlock(&bkpoint_lock); - interrupts_restore(ipl); + irq_spinlock_unlock(&bkpoint_lock, true); return; } - + cur->address = NULL; - + setup_dr(slot); - - spinlock_unlock(&bkpoint_lock); - interrupts_restore(ipl); + + irq_spinlock_unlock(&bkpoint_lock, true); // ipi_broadcast(VECTOR_DEBUG_IPI); } - - static void debug_exception(int n __attribute__((unused)), istate_t *istate) { - unative_t dr6; - int i; - /* Set RF to restart the instruction */ #ifdef __64_BITS__ istate->rflags |= RFLAGS_RF; -#else +#endif + +#ifdef __32_BITS__ istate->eflags |= EFLAGS_RF; #endif - - dr6 = read_dr6(); - for (i=0; i < BKPOINTS_MAX; i++) { + + unative_t dr6 = read_dr6(); + + unsigned int i; + for (i = 0; i < BKPOINTS_MAX; i++) { if (dr6 & (1 << i)) { dr6 &= ~ (1 << i); @@ -289,38 +293,39 @@ #ifdef CONFIG_SMP -static void -debug_ipi(int n __attribute__((unused)), +static void debug_ipi(int n __attribute__((unused)), istate_t *istate __attribute__((unused))) { - int i; - - spinlock_lock(&bkpoint_lock); + irq_spinlock_lock(&bkpoint_lock, false); + + unsigned int i; for (i = 0; i < BKPOINTS_MAX; i++) setup_dr(i); - spinlock_unlock(&bkpoint_lock); -} -#endif - -/** Initialize debugger */ + + irq_spinlock_unlock(&bkpoint_lock, false); +} +#endif /* CONFIG_SMP */ + +/** Initialize debugger + * + */ void debugger_init() { - int i; - + unsigned int i; for (i = 0; i < BKPOINTS_MAX; i++) breakpoints[i].address = NULL; - + #ifdef CONFIG_KCONSOLE cmd_initialize(&bkpts_info); if (!cmd_register(&bkpts_info)) printf("Cannot register command %s\n", bkpts_info.name); - + cmd_initialize(&delbkpt_info); if (!cmd_register(&delbkpt_info)) printf("Cannot register command %s\n", delbkpt_info.name); - + cmd_initialize(&addbkpt_info); if (!cmd_register(&addbkpt_info)) printf("Cannot register command %s\n", addbkpt_info.name); - + cmd_initialize(&addwatchp_info); if (!cmd_register(&addwatchp_info)) @@ -331,18 +336,18 @@ #ifdef CONFIG_SMP exc_register(VECTOR_DEBUG_IPI, "debugger_smp", debug_ipi); -#endif +#endif /* CONFIG_SMP */ } #ifdef CONFIG_KCONSOLE -/** Print table of active breakpoints */ +/** Print table of active breakpoints + * + */ int cmd_print_breakpoints(cmd_arg_t *argv __attribute__((unused))) { - unsigned int i; - #ifdef __32_BITS__ printf("# Count Address In symbol\n"); printf("-- ----- ---------- ---------\n"); #endif - + #ifdef __64_BITS__ printf("# Count Address In symbol\n"); @@ -350,26 +355,30 @@ #endif - for (i = 0; i < BKPOINTS_MAX; i++) + unsigned int i; + for (i = 0; i < BKPOINTS_MAX; i++) { if (breakpoints[i].address) { const char *symbol = symtab_fmt_name_lookup( breakpoints[i].address); - + #ifdef __32_BITS__ - printf("%-2u %-5d %#10zx %s\n", i, + printf("%-2u %-5" PRIs " %p %s\n", i, breakpoints[i].counter, breakpoints[i].address, symbol); #endif - + #ifdef __64_BITS__ - printf("%-2u %-5d %#18zx %s\n", i, + printf("%-2u %-5" PRIs " %p %s\n", i, breakpoints[i].counter, breakpoints[i].address, symbol); #endif - - } + } + } + return 1; } -/** Remove breakpoint from table */ +/** Remove breakpoint from table + * + */ int cmd_del_breakpoint(cmd_arg_t *argv) { @@ -379,21 +388,23 @@ return 0; } + breakpoint_del(argv->intval); return 1; } -/** Add new breakpoint to table */ +/** Add new breakpoint to table + * + */ static int cmd_add_breakpoint(cmd_arg_t *argv) { - int flags; - int id; - - if (argv == &add_argv) { + unsigned int flags; + if (argv == &add_argv) flags = BKPOINT_INSTR; - } else { /* addwatchp */ + else flags = BKPOINT_WRITE; - } + printf("Adding breakpoint on address: %p\n", argv->intval); - id = breakpoint_add((void *)argv->intval, flags, -1); + + int id = breakpoint_add((void *)argv->intval, flags, -1); if (id < 0) printf("Add breakpoint failed.\n"); Index: kernel/arch/amd64/src/interrupt.c =================================================================== --- kernel/arch/amd64/src/interrupt.c (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/amd64/src/interrupt.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -106,14 +106,14 @@ } -/** General Protection Fault. */ +/** General Protection Fault. + * + */ static void gp_fault(int n, istate_t *istate) { if (TASK) { - size_t ver; - - spinlock_lock(&TASK->lock); - ver = TASK->arch.iomapver; - spinlock_unlock(&TASK->lock); - + irq_spinlock_lock(&TASK->lock, false); + size_t ver = TASK->arch.iomapver; + irq_spinlock_unlock(&TASK->lock, false); + if (CPU->arch.iomapver_copy != ver) { /* @@ -129,5 +129,5 @@ fault_if_from_uspace(istate, "General protection fault."); } - + decode_istate(n, istate); panic("General protection fault."); @@ -159,5 +159,7 @@ #endif -/** Handler of IRQ exceptions */ +/** Handler of IRQ exceptions. + * + */ static void irq_interrupt(int n, istate_t *istate) { @@ -174,5 +176,5 @@ * The IRQ handler was found. */ - + if (irq->preack) { /* Send EOI before processing the interrupt */ @@ -181,5 +183,5 @@ } irq->handler(irq); - spinlock_unlock(&irq->lock); + irq_spinlock_unlock(&irq->lock, false); } else { /* Index: kernel/arch/ia32/include/smp/apic.h =================================================================== --- kernel/arch/ia32/include/smp/apic.h (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/ia32/include/smp/apic.h (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -27,5 +27,5 @@ */ -/** @addtogroup ia32 +/** @addtogroup ia32 * @{ */ @@ -39,87 +39,88 @@ #include -#define FIXED (0<<0) -#define LOPRI (1<<0) - -#define APIC_ID_COUNT 16 +#define FIXED (0 << 0) +#define LOPRI (1 << 0) + +#define APIC_ID_COUNT 16 /* local APIC macros */ -#define IPI_INIT 0 -#define IPI_STARTUP 0 +#define IPI_INIT 0 +#define IPI_STARTUP 0 /** Delivery modes. */ -#define DELMOD_FIXED 0x0 -#define DELMOD_LOWPRI 0x1 -#define DELMOD_SMI 0x2 +#define DELMOD_FIXED 0x0 +#define DELMOD_LOWPRI 0x1 +#define DELMOD_SMI 0x2 /* 0x3 reserved */ -#define DELMOD_NMI 0x4 -#define DELMOD_INIT 0x5 -#define DELMOD_STARTUP 0x6 -#define DELMOD_EXTINT 0x7 +#define DELMOD_NMI 0x4 +#define DELMOD_INIT 0x5 +#define DELMOD_STARTUP 0x6 +#define DELMOD_EXTINT 0x7 /** Destination modes. */ -#define DESTMOD_PHYS 0x0 -#define DESTMOD_LOGIC 0x1 +#define DESTMOD_PHYS 0x0 +#define DESTMOD_LOGIC 0x1 /** Trigger Modes. */ -#define TRIGMOD_EDGE 0x0 -#define TRIGMOD_LEVEL 0x1 +#define TRIGMOD_EDGE 0x0 +#define TRIGMOD_LEVEL 0x1 /** Levels. */ -#define LEVEL_DEASSERT 0x0 -#define LEVEL_ASSERT 0x1 +#define LEVEL_DEASSERT 0x0 +#define LEVEL_ASSERT 0x1 /** Destination Shorthands. */ -#define SHORTHAND_NONE 0x0 -#define SHORTHAND_SELF 0x1 -#define SHORTHAND_ALL_INCL 0x2 -#define SHORTHAND_ALL_EXCL 0x3 +#define SHORTHAND_NONE 0x0 +#define SHORTHAND_SELF 0x1 +#define SHORTHAND_ALL_INCL 0x2 +#define SHORTHAND_ALL_EXCL 0x3 /** Interrupt Input Pin Polarities. */ -#define POLARITY_HIGH 0x0 -#define POLARITY_LOW 0x1 +#define POLARITY_HIGH 0x0 +#define POLARITY_LOW 0x1 /** Divide Values. (Bit 2 is always 0) */ -#define DIVIDE_2 0x0 -#define DIVIDE_4 0x1 -#define DIVIDE_8 0x2 -#define DIVIDE_16 0x3 -#define DIVIDE_32 0x8 -#define DIVIDE_64 0x9 -#define DIVIDE_128 0xa -#define DIVIDE_1 0xb +#define DIVIDE_2 0x0 +#define DIVIDE_4 0x1 +#define DIVIDE_8 0x2 +#define DIVIDE_16 0x3 +#define DIVIDE_32 0x8 +#define DIVIDE_64 0x9 +#define DIVIDE_128 0xa +#define DIVIDE_1 0xb /** Timer Modes. */ -#define TIMER_ONESHOT 0x0 -#define TIMER_PERIODIC 0x1 +#define TIMER_ONESHOT 0x0 +#define TIMER_PERIODIC 0x1 /** Delivery status. */ -#define DELIVS_IDLE 0x0 -#define DELIVS_PENDING 0x1 +#define DELIVS_IDLE 0x0 +#define DELIVS_PENDING 0x1 /** Destination masks. */ -#define DEST_ALL 0xff +#define DEST_ALL 0xff /** Dest format models. */ -#define MODEL_FLAT 0xf -#define MODEL_CLUSTER 0x0 +#define MODEL_FLAT 0xf +#define MODEL_CLUSTER 0x0 /** Interrupt Command Register. */ -#define ICRlo (0x300 / sizeof(uint32_t)) -#define ICRhi (0x310 / sizeof(uint32_t)) +#define ICRlo (0x300 / sizeof(uint32_t)) +#define ICRhi (0x310 / sizeof(uint32_t)) + typedef struct { union { uint32_t lo; struct { - uint8_t vector; /**< Interrupt Vector. */ - unsigned delmod : 3; /**< Delivery Mode. */ - unsigned destmod : 1; /**< Destination Mode. */ - unsigned delivs : 1; /**< Delivery status (RO). */ - unsigned : 1; /**< Reserved. */ - unsigned level : 1; /**< Level. */ - unsigned trigger_mode : 1; /**< Trigger Mode. */ - unsigned : 2; /**< Reserved. */ - unsigned shorthand : 2; /**< Destination Shorthand. */ - unsigned : 12; /**< Reserved. */ + uint8_t vector; /**< Interrupt Vector. */ + unsigned int delmod : 3; /**< Delivery Mode. */ + unsigned int destmod : 1; /**< Destination Mode. */ + unsigned int delivs : 1; /**< Delivery status (RO). */ + unsigned int : 1; /**< Reserved. */ + unsigned int level : 1; /**< Level. */ + unsigned int trigger_mode : 1; /**< Trigger Mode. */ + unsigned int : 2; /**< Reserved. */ + unsigned int shorthand : 2; /**< Destination Shorthand. */ + unsigned int : 12; /**< Reserved. */ } __attribute__ ((packed)); }; @@ -127,6 +128,6 @@ uint32_t hi; struct { - unsigned : 24; /**< Reserved. */ - uint8_t dest; /**< Destination field. */ + unsigned int : 24; /**< Reserved. */ + uint8_t dest; /**< Destination field. */ } __attribute__ ((packed)); }; @@ -134,154 +135,165 @@ /* End Of Interrupt. */ -#define EOI (0x0b0 / sizeof(uint32_t)) +#define EOI (0x0b0 / sizeof(uint32_t)) /** Error Status Register. */ -#define ESR (0x280 / sizeof(uint32_t)) +#define ESR (0x280 / sizeof(uint32_t)) + typedef union { uint32_t value; uint8_t err_bitmap; struct { - unsigned send_checksum_error : 1; - unsigned receive_checksum_error : 1; - unsigned send_accept_error : 1; - unsigned receive_accept_error : 1; - unsigned : 1; - unsigned send_illegal_vector : 1; - unsigned received_illegal_vector : 1; - unsigned illegal_register_address : 1; - unsigned : 24; + unsigned int send_checksum_error : 1; + unsigned int receive_checksum_error : 1; + unsigned int send_accept_error : 1; + unsigned int receive_accept_error : 1; + unsigned int : 1; + unsigned int send_illegal_vector : 1; + unsigned int received_illegal_vector : 1; + unsigned int illegal_register_address : 1; + unsigned int : 24; } __attribute__ ((packed)); } esr_t; /* Task Priority Register */ -#define TPR (0x080 / sizeof(uint32_t)) -typedef union { - uint32_t value; - struct { - unsigned pri_sc : 4; /**< Task Priority Sub-Class. */ - unsigned pri : 4; /**< Task Priority. */ +#define TPR (0x080 / sizeof(uint32_t)) + +typedef union { + uint32_t value; + struct { + unsigned int pri_sc : 4; /**< Task Priority Sub-Class. */ + unsigned int pri : 4; /**< Task Priority. */ } __attribute__ ((packed)); } tpr_t; /** Spurious-Interrupt Vector Register. */ -#define SVR (0x0f0 / sizeof(uint32_t)) -typedef union { - uint32_t value; - struct { - uint8_t vector; /**< Spurious Vector. */ - unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable. */ - unsigned focus_checking : 1; /**< Focus Processor Checking. */ - unsigned : 22; /**< Reserved. */ +#define SVR (0x0f0 / sizeof(uint32_t)) + +typedef union { + uint32_t value; + struct { + uint8_t vector; /**< Spurious Vector. */ + unsigned int lapic_enabled : 1; /**< APIC Software Enable/Disable. */ + unsigned int focus_checking : 1; /**< Focus Processor Checking. */ + unsigned int : 22; /**< Reserved. */ } __attribute__ ((packed)); } svr_t; /** Time Divide Configuration Register. */ -#define TDCR (0x3e0 / sizeof(uint32_t)) -typedef union { - uint32_t value; - struct { - unsigned div_value : 4; /**< Divide Value, bit 2 is always 0. */ - unsigned : 28; /**< Reserved. */ +#define TDCR (0x3e0 / sizeof(uint32_t)) + +typedef union { + uint32_t value; + struct { + unsigned int div_value : 4; /**< Divide Value, bit 2 is always 0. */ + unsigned int : 28; /**< Reserved. */ } __attribute__ ((packed)); } tdcr_t; /* Initial Count Register for Timer */ -#define ICRT (0x380 / sizeof(uint32_t)) +#define ICRT (0x380 / sizeof(uint32_t)) /* Current Count Register for Timer */ -#define CCRT (0x390 / sizeof(uint32_t)) +#define CCRT (0x390 / sizeof(uint32_t)) /** LVT Timer register. */ -#define LVT_Tm (0x320 / sizeof(uint32_t)) -typedef union { - uint32_t value; - struct { - uint8_t vector; /**< Local Timer Interrupt vector. */ - unsigned : 4; /**< Reserved. */ - unsigned delivs : 1; /**< Delivery status (RO). */ - unsigned : 3; /**< Reserved. */ - unsigned masked : 1; /**< Interrupt Mask. */ - unsigned mode : 1; /**< Timer Mode. */ - unsigned : 14; /**< Reserved. */ +#define LVT_Tm (0x320 / sizeof(uint32_t)) + +typedef union { + uint32_t value; + struct { + uint8_t vector; /**< Local Timer Interrupt vector. */ + unsigned int : 4; /**< Reserved. */ + unsigned int delivs : 1; /**< Delivery status (RO). */ + unsigned int : 3; /**< Reserved. */ + unsigned int masked : 1; /**< Interrupt Mask. */ + unsigned int mode : 1; /**< Timer Mode. */ + unsigned int : 14; /**< Reserved. */ } __attribute__ ((packed)); } lvt_tm_t; /** LVT LINT registers. */ -#define LVT_LINT0 (0x350 / sizeof(uint32_t)) -#define LVT_LINT1 (0x360 / sizeof(uint32_t)) -typedef union { - uint32_t value; - struct { - uint8_t vector; /**< LINT Interrupt vector. */ - unsigned delmod : 3; /**< Delivery Mode. */ - unsigned : 1; /**< Reserved. */ - unsigned delivs : 1; /**< Delivery status (RO). */ - unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ - unsigned irr : 1; /**< Remote IRR (RO). */ - unsigned trigger_mode : 1; /**< Trigger Mode. */ - unsigned masked : 1; /**< Interrupt Mask. */ - unsigned : 15; /**< Reserved. */ +#define LVT_LINT0 (0x350 / sizeof(uint32_t)) +#define LVT_LINT1 (0x360 / sizeof(uint32_t)) + +typedef union { + uint32_t value; + struct { + uint8_t vector; /**< LINT Interrupt vector. */ + unsigned int delmod : 3; /**< Delivery Mode. */ + unsigned int : 1; /**< Reserved. */ + unsigned int delivs : 1; /**< Delivery status (RO). */ + unsigned int intpol : 1; /**< Interrupt Input Pin Polarity. */ + unsigned int irr : 1; /**< Remote IRR (RO). */ + unsigned int trigger_mode : 1; /**< Trigger Mode. */ + unsigned int masked : 1; /**< Interrupt Mask. */ + unsigned int : 15; /**< Reserved. */ } __attribute__ ((packed)); } lvt_lint_t; /** LVT Error register. */ -#define LVT_Err (0x370 / sizeof(uint32_t)) -typedef union { - uint32_t value; - struct { - uint8_t vector; /**< Local Timer Interrupt vector. */ - unsigned : 4; /**< Reserved. */ - unsigned delivs : 1; /**< Delivery status (RO). */ - unsigned : 3; /**< Reserved. */ - unsigned masked : 1; /**< Interrupt Mask. */ - unsigned : 15; /**< Reserved. */ +#define LVT_Err (0x370 / sizeof(uint32_t)) + +typedef union { + uint32_t value; + struct { + uint8_t vector; /**< Local Timer Interrupt vector. */ + unsigned int : 4; /**< Reserved. */ + unsigned int delivs : 1; /**< Delivery status (RO). */ + unsigned int : 3; /**< Reserved. */ + unsigned int masked : 1; /**< Interrupt Mask. */ + unsigned int : 15; /**< Reserved. */ } __attribute__ ((packed)); } lvt_error_t; /** Local APIC ID Register. */ -#define L_APIC_ID (0x020 / sizeof(uint32_t)) -typedef union { - uint32_t value; - struct { - unsigned : 24; /**< Reserved. */ - uint8_t apic_id; /**< Local APIC ID. */ +#define L_APIC_ID (0x020 / sizeof(uint32_t)) + +typedef union { + uint32_t value; + struct { + unsigned int : 24; /**< Reserved. */ + uint8_t apic_id; /**< Local APIC ID. */ } __attribute__ ((packed)); } l_apic_id_t; /** Local APIC Version Register */ -#define LAVR (0x030 / sizeof(uint32_t)) -#define LAVR_Mask 0xff -#define is_local_apic(x) (((x) & LAVR_Mask & 0xf0) == 0x1) -#define is_82489DX_apic(x) ((((x) & LAVR_Mask & 0xf0) == 0x0)) -#define is_local_xapic(x) (((x) & LAVR_Mask) == 0x14) +#define LAVR (0x030 / sizeof(uint32_t)) +#define LAVR_Mask 0xff + +#define is_local_apic(x) (((x) & LAVR_Mask & 0xf0) == 0x1) +#define is_82489DX_apic(x) ((((x) & LAVR_Mask & 0xf0) == 0x0)) +#define is_local_xapic(x) (((x) & LAVR_Mask) == 0x14) /** Logical Destination Register. */ -#define LDR (0x0d0 / sizeof(uint32_t)) -typedef union { - uint32_t value; - struct { - unsigned : 24; /**< Reserved. */ - uint8_t id; /**< Logical APIC ID. */ +#define LDR (0x0d0 / sizeof(uint32_t)) + +typedef union { + uint32_t value; + struct { + unsigned int : 24; /**< Reserved. */ + uint8_t id; /**< Logical APIC ID. */ } __attribute__ ((packed)); } ldr_t; /** Destination Format Register. */ -#define DFR (0x0e0 / sizeof(uint32_t)) -typedef union { - uint32_t value; - struct { - unsigned : 28; /**< Reserved, all ones. */ - unsigned model : 4; /**< Model. */ +#define DFR (0x0e0 / sizeof(uint32_t)) + +typedef union { + uint32_t value; + struct { + unsigned int : 28; /**< Reserved, all ones. */ + unsigned int model : 4; /**< Model. */ } __attribute__ ((packed)); } dfr_t; /* IO APIC */ -#define IOREGSEL (0x00 / sizeof(uint32_t)) -#define IOWIN (0x10 / sizeof(uint32_t)) - -#define IOAPICID 0x00 -#define IOAPICVER 0x01 -#define IOAPICARB 0x02 -#define IOREDTBL 0x10 +#define IOREGSEL (0x00 / sizeof(uint32_t)) +#define IOWIN (0x10 / sizeof(uint32_t)) + +#define IOAPICID 0x00 +#define IOAPICVER 0x01 +#define IOAPICARB 0x02 +#define IOREDTBL 0x10 /** I/O Register Select Register. */ @@ -289,6 +301,6 @@ uint32_t value; struct { - uint8_t reg_addr; /**< APIC Register Address. */ - unsigned : 24; /**< Reserved. */ + uint8_t reg_addr; /**< APIC Register Address. */ + unsigned int : 24; /**< Reserved. */ } __attribute__ ((packed)); } io_regsel_t; @@ -299,13 +311,13 @@ uint32_t lo; struct { - uint8_t intvec; /**< Interrupt Vector. */ - unsigned delmod : 3; /**< Delivery Mode. */ - unsigned destmod : 1; /**< Destination mode. */ - unsigned delivs : 1; /**< Delivery status (RO). */ - unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ - unsigned irr : 1; /**< Remote IRR (RO). */ - unsigned trigger_mode : 1; /**< Trigger Mode. */ - unsigned masked : 1; /**< Interrupt Mask. */ - unsigned : 15; /**< Reserved. */ + uint8_t intvec; /**< Interrupt Vector. */ + unsigned int delmod : 3; /**< Delivery Mode. */ + unsigned int destmod : 1; /**< Destination mode. */ + unsigned int delivs : 1; /**< Delivery status (RO). */ + unsigned int intpol : 1; /**< Interrupt Input Pin Polarity. */ + unsigned int irr : 1; /**< Remote IRR (RO). */ + unsigned int trigger_mode : 1; /**< Trigger Mode. */ + unsigned int masked : 1; /**< Interrupt Mask. */ + unsigned int : 15; /**< Reserved. */ } __attribute__ ((packed)); }; @@ -313,6 +325,6 @@ uint32_t hi; struct { - unsigned : 24; /**< Reserved. */ - uint8_t dest : 8; /**< Destination Field. */ + unsigned int : 24; /**< Reserved. */ + uint8_t dest : 8; /**< Destination Field. */ } __attribute__ ((packed)); }; @@ -325,7 +337,7 @@ uint32_t value; struct { - unsigned : 24; /**< Reserved. */ - unsigned apic_id : 4; /**< IO APIC ID. */ - unsigned : 4; /**< Reserved. */ + unsigned int : 24; /**< Reserved. */ + unsigned int apic_id : 4; /**< IO APIC ID. */ + unsigned int : 4; /**< Reserved. */ } __attribute__ ((packed)); } io_apic_id_t; @@ -340,14 +352,14 @@ extern void l_apic_init(void); extern void l_apic_eoi(void); -extern int l_apic_broadcast_custom_ipi(uint8_t vector); -extern int l_apic_send_init_ipi(uint8_t apicid); +extern int l_apic_broadcast_custom_ipi(uint8_t); +extern int l_apic_send_init_ipi(uint8_t); extern void l_apic_debug(void); extern uint8_t l_apic_id(void); -extern uint32_t io_apic_read(uint8_t address); -extern void io_apic_write(uint8_t address , uint32_t x); -extern void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t v, int flags); -extern void io_apic_disable_irqs(uint16_t irqmask); -extern void io_apic_enable_irqs(uint16_t irqmask); +extern uint32_t io_apic_read(uint8_t); +extern void io_apic_write(uint8_t, uint32_t); +extern void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t v, unsigned int); +extern void io_apic_disable_irqs(uint16_t); +extern void io_apic_enable_irqs(uint16_t); #endif Index: kernel/arch/ia32/src/ddi/ddi.c =================================================================== --- kernel/arch/ia32/src/ddi/ddi.c (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/ia32/src/ddi/ddi.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -50,34 +50,31 @@ * Interrupts are disabled and task is locked. * - * @param task Task. + * @param task Task. * @param ioaddr Startign I/O space address. - * @param size Size of the enabled I/O range. + * @param size Size of the enabled I/O range. * * @return 0 on success or an error code from errno.h. + * */ int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size) { - size_t bits; - - bits = ioaddr + size; + size_t bits = ioaddr + size; if (bits > IO_PORTS) return ENOENT; - + if (task->arch.iomap.bits < bits) { - bitmap_t oldiomap; - uint8_t *newmap; - /* * The I/O permission bitmap is too small and needs to be grown. */ - newmap = (uint8_t *) malloc(BITS2BYTES(bits), FRAME_ATOMIC); + uint8_t *newmap = (uint8_t *) malloc(BITS2BYTES(bits), FRAME_ATOMIC); if (!newmap) return ENOMEM; + bitmap_t oldiomap; bitmap_initialize(&oldiomap, task->arch.iomap.map, task->arch.iomap.bits); bitmap_initialize(&task->arch.iomap, newmap, bits); - + /* * Mark the new range inaccessible. @@ -85,9 +82,9 @@ bitmap_set_range(&task->arch.iomap, oldiomap.bits, bits - oldiomap.bits); - + /* * In case there really existed smaller iomap, * copy its contents and deallocate it. - */ + */ if (oldiomap.bits) { bitmap_copy(&task->arch.iomap, &oldiomap, @@ -96,15 +93,15 @@ } } - + /* * Enable the range and we are done. */ bitmap_clear_range(&task->arch.iomap, (size_t) ioaddr, (size_t) size); - + /* * Increment I/O Permission bitmap generation counter. */ task->arch.iomapver++; - + return 0; } @@ -116,23 +113,20 @@ * * Interrupts must be disabled prior this call. + * */ void io_perm_bitmap_install(void) { - size_t bits; - ptr_16_32_t cpugdtr; - descriptor_t *gdt_p; - size_t ver; - /* First, copy the I/O Permission Bitmap. */ - spinlock_lock(&TASK->lock); - ver = TASK->arch.iomapver; - if ((bits = TASK->arch.iomap.bits)) { + irq_spinlock_lock(&TASK->lock, false); + size_t ver = TASK->arch.iomapver; + size_t bits = TASK->arch.iomap.bits; + if (bits) { + ASSERT(TASK->arch.iomap.map); + bitmap_t iomap; - task_t *task = TASK; - - ASSERT(TASK->arch.iomap.map); bitmap_initialize(&iomap, CPU->arch.tss->iomap, TSS_IOMAP_SIZE * 8); - bitmap_copy(&iomap, &task->arch.iomap, task->arch.iomap.bits); + bitmap_copy(&iomap, &TASK->arch.iomap, TASK->arch.iomap.bits); + /* * It is safe to set the trailing eight bits because of the @@ -141,15 +135,17 @@ bitmap_set_range(&iomap, ALIGN_UP(TASK->arch.iomap.bits, 8), 8); } - spinlock_unlock(&TASK->lock); - + irq_spinlock_unlock(&TASK->lock, false); + /* * Second, adjust TSS segment limit. * Take the extra ending byte with all bits set into account. */ + ptr_16_32_t cpugdtr; gdtr_store(&cpugdtr); - gdt_p = (descriptor_t *) cpugdtr.base; + + descriptor_t *gdt_p = (descriptor_t *) cpugdtr.base; gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + BITS2BYTES(bits)); gdtr_load(&cpugdtr); - + /* * Before we load new TSS limit, the current TSS descriptor Index: kernel/arch/ia32/src/drivers/i8254.c =================================================================== --- kernel/arch/ia32/src/drivers/i8254.c (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/ia32/src/drivers/i8254.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -54,9 +54,12 @@ #include -#define CLK_PORT1 ((ioport8_t *)0x40) -#define CLK_PORT4 ((ioport8_t *)0x43) +#define CLK_PORT1 ((ioport8_t *) 0x40) +#define CLK_PORT4 ((ioport8_t *) 0x43) -#define CLK_CONST 1193180 -#define MAGIC_NUMBER 1194 +#define CLK_CONST 1193180 +#define MAGIC_NUMBER 1194 + +#define LOOPS 150000 +#define SHIFT 11 static irq_t i8254_irq; @@ -75,7 +78,7 @@ * lock. We just release it, call clock() and then reacquire it again. */ - spinlock_unlock(&irq->lock); + irq_spinlock_unlock(&irq->lock, false); clock(); - spinlock_lock(&irq->lock); + irq_spinlock_lock(&irq->lock, false); } @@ -102,13 +105,6 @@ } -#define LOOPS 150000 -#define SHIFT 11 void i8254_calibrate_delay_loop(void) { - uint64_t clk1, clk2; - uint32_t t1, t2, o1, o2; - uint8_t not_ok; - - /* * One-shot timer. Count-down from 0xffff at 1193180Hz @@ -118,5 +114,9 @@ pio_write_8(CLK_PORT1, 0xff); pio_write_8(CLK_PORT1, 0xff); - + + uint8_t not_ok; + uint32_t t1; + uint32_t t2; + do { /* will read both status and count */ @@ -126,34 +126,34 @@ t1 |= pio_read_8(CLK_PORT1) << 8; } while (not_ok); - + asm_delay_loop(LOOPS); - + pio_write_8(CLK_PORT4, 0xd2); t2 = pio_read_8(CLK_PORT1); t2 |= pio_read_8(CLK_PORT1) << 8; - + /* * We want to determine the overhead of the calibrating mechanism. */ pio_write_8(CLK_PORT4, 0xd2); - o1 = pio_read_8(CLK_PORT1); + uint32_t o1 = pio_read_8(CLK_PORT1); o1 |= pio_read_8(CLK_PORT1) << 8; - + asm_fake_loop(LOOPS); - + pio_write_8(CLK_PORT4, 0xd2); - o2 = pio_read_8(CLK_PORT1); + uint32_t o2 = pio_read_8(CLK_PORT1); o2 |= pio_read_8(CLK_PORT1) << 8; - + CPU->delay_loop_const = ((MAGIC_NUMBER * LOOPS) / 1000) / ((t1 - t2) - (o1 - o2)) + (((MAGIC_NUMBER * LOOPS) / 1000) % ((t1 - t2) - (o1 - o2)) ? 1 : 0); - - clk1 = get_cycle(); + + uint64_t clk1 = get_cycle(); delay(1 << SHIFT); - clk2 = get_cycle(); + uint64_t clk2 = get_cycle(); CPU->frequency_mhz = (clk2 - clk1) >> SHIFT; - + return; } Index: kernel/arch/ia32/src/interrupt.c =================================================================== --- kernel/arch/ia32/src/interrupt.c (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/ia32/src/interrupt.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -94,5 +94,5 @@ { fault_if_from_uspace(istate, "Unserviced interrupt: %d.", n); - + decode_istate(istate); panic("Unserviced interrupt: %d.", n); @@ -102,5 +102,5 @@ { fault_if_from_uspace(istate, "Divide error."); - + decode_istate(istate); panic("Divide error."); @@ -111,10 +111,8 @@ { if (TASK) { - size_t ver; + irq_spinlock_lock(&TASK->lock, false); + size_t ver = TASK->arch.iomapver; + irq_spinlock_unlock(&TASK->lock, false); - spinlock_lock(&TASK->lock); - ver = TASK->arch.iomapver; - spinlock_unlock(&TASK->lock); - if (CPU->arch.iomapver_copy != ver) { /* @@ -130,5 +128,5 @@ fault_if_from_uspace(istate, "General protection fault."); } - + decode_istate(istate); panic("General protection fault."); @@ -138,5 +136,5 @@ { fault_if_from_uspace(istate, "Stack fault."); - + decode_istate(istate); panic("Stack fault."); @@ -146,8 +144,9 @@ { uint32_t mxcsr; - asm ( + asm volatile ( "stmxcsr %[mxcsr]\n" : [mxcsr] "=m" (mxcsr) ); + fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR: %#zx.", (unative_t) mxcsr); @@ -158,7 +157,8 @@ } -static void nm_fault(int n __attribute__((unused)), istate_t *istate __attribute__((unused))) -{ -#ifdef CONFIG_FPU_LAZY +static void nm_fault(int n __attribute__((unused)), + istate_t *istate __attribute__((unused))) +{ +#ifdef CONFIG_FPU_LAZY scheduler_fpu_lazy_request(); #else @@ -169,5 +169,6 @@ #ifdef CONFIG_SMP -static void tlb_shootdown_ipi(int n __attribute__((unused)), istate_t *istate __attribute__((unused))) +static void tlb_shootdown_ipi(int n __attribute__((unused)), + istate_t *istate __attribute__((unused))) { trap_virtual_eoi(); @@ -191,5 +192,5 @@ * The IRQ handler was found. */ - + if (irq->preack) { /* Send EOI before processing the interrupt */ @@ -198,5 +199,5 @@ } irq->handler(irq); - spinlock_unlock(&irq->lock); + irq_spinlock_unlock(&irq->lock, false); } else { /* Index: kernel/arch/ia32/src/smp/apic.c =================================================================== --- kernel/arch/ia32/src/smp/apic.c (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/ia32/src/smp/apic.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -53,11 +53,12 @@ * Advanced Programmable Interrupt Controller for SMP systems. * Tested on: - * Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs - * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs - * VMware Workstation 5.5 with 2 CPUs - * QEMU 0.8.0 with 2-15 CPUs - * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs - * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs - * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs + * Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs + * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs + * VMware Workstation 5.5 with 2 CPUs + * QEMU 0.8.0 with 2-15 CPUs + * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs + * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs + * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs + * */ @@ -69,4 +70,5 @@ * optimize the code too much and accesses to l_apic and io_apic, that must * always be 32-bit, would use byte oriented instructions. + * */ volatile uint32_t *l_apic = (uint32_t *) 0xfee00000; @@ -79,5 +81,5 @@ #ifdef LAPIC_VERBOSE -static char *delmod_str[] = { +static const char *delmod_str[] = { "Fixed", "Lowest Priority", @@ -90,30 +92,30 @@ }; -static char *destmod_str[] = { +static const char *destmod_str[] = { "Physical", "Logical" }; -static char *trigmod_str[] = { +static const char *trigmod_str[] = { "Edge", "Level" }; -static char *mask_str[] = { +static const char *mask_str[] = { "Unmasked", "Masked" }; -static char *delivs_str[] = { +static const char *delivs_str[] = { "Idle", "Send Pending" }; -static char *tm_mode_str[] = { +static const char *tm_mode_str[] = { "One-shot", "Periodic" }; -static char *intpol_str[] = { +static const char *intpol_str[] = { "Polarity High", "Polarity Low" @@ -123,8 +125,10 @@ /** APIC spurious interrupt handler. * - * @param n Interrupt vector. + * @param n Interrupt vector. * @param istate Interrupted state. - */ -static void apic_spurious(int n __attribute__((unused)), istate_t *istate __attribute__((unused))) + * + */ +static void apic_spurious(int n __attribute__((unused)), + istate_t *istate __attribute__((unused))) { #ifdef CONFIG_DEBUG @@ -145,7 +149,7 @@ * irq->lock so we just unlock it and then lock it again. */ - spinlock_unlock(&irq->lock); + irq_spinlock_unlock(&irq->lock, false); clock(); - spinlock_lock(&irq->lock); + irq_spinlock_lock(&irq->lock, false); } @@ -153,8 +157,6 @@ void apic_init(void) { - io_apic_id_t idreg; - exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious); - + enable_irqs_function = io_apic_enable_irqs; disable_irqs_function = io_apic_disable_irqs; @@ -179,5 +181,5 @@ for (i = 0; i < IRQ_COUNT; i++) { int pin; - + if ((pin = smp_irq_to_pin(i)) != -1) io_apic_change_ioredtbl((uint8_t) pin, DEST_ALL, (uint8_t) (IVT_IRQBASE + i), LOPRI); @@ -187,6 +189,8 @@ * Ensure that io_apic has unique ID. */ + io_apic_id_t idreg; + idreg.value = io_apic_read(IOAPICID); - if ((1 << idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ + if ((1 << idreg.apic_id) & apic_id_mask) { /* See if IO APIC ID is used already */ for (i = 0; i < APIC_ID_COUNT; i++) { if (!((1 << i) & apic_id_mask)) { @@ -197,11 +201,10 @@ } } - + /* * Configure the BSP's lapic. */ l_apic_init(); - - l_apic_debug(); + l_apic_debug(); } @@ -211,4 +214,5 @@ * * @return 0 on error, 1 on success. + * */ int apic_poll_errors(void) @@ -232,5 +236,5 @@ if (esr.illegal_register_address) printf("Illegal Register Address\n"); - + return !esr.err_bitmap; } @@ -241,9 +245,10 @@ * * @return 0 on failure, 1 on success. + * */ int l_apic_broadcast_custom_ipi(uint8_t vector) { icr_t icr; - + icr.lo = l_apic[ICRlo]; icr.delmod = DELMOD_FIXED; @@ -253,7 +258,7 @@ icr.trigger_mode = TRIGMOD_LEVEL; icr.vector = vector; - + l_apic[ICRlo] = icr.lo; - + icr.lo = l_apic[ICRlo]; if (icr.delivs == DELIVS_PENDING) { @@ -262,5 +267,5 @@ #endif } - + return apic_poll_errors(); } @@ -271,13 +276,13 @@ * * @return 0 on failure, 1 on success. + * */ int l_apic_send_init_ipi(uint8_t apicid) { + /* + * Read the ICR register in and zero all non-reserved fields. + */ icr_t icr; - int i; - - /* - * Read the ICR register in and zero all non-reserved fields. - */ + icr.lo = l_apic[ICRlo]; icr.hi = l_apic[ICRhi]; @@ -293,5 +298,5 @@ l_apic[ICRhi] = icr.hi; l_apic[ICRlo] = icr.lo; - + /* * According to MP Specification, 20us should be enough to @@ -299,8 +304,8 @@ */ delay(20); - + if (!apic_poll_errors()) return 0; - + icr.lo = l_apic[ICRlo]; if (icr.delivs == DELIVS_PENDING) { @@ -309,5 +314,5 @@ #endif } - + icr.delmod = DELMOD_INIT; icr.destmod = DESTMOD_PHYS; @@ -317,15 +322,16 @@ icr.vector = 0; l_apic[ICRlo] = icr.lo; - + /* * Wait 10ms as MP Specification specifies. */ delay(10000); - + if (!is_82489DX_apic(l_apic[LAVR])) { /* * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. */ - for (i = 0; i<2; i++) { + unsigned int i; + for (i = 0; i < 2; i++) { icr.lo = l_apic[ICRlo]; icr.vector = (uint8_t) (((uintptr_t) ap_boot) >> 12); /* calculate the reset vector */ @@ -346,31 +352,26 @@ void l_apic_init(void) { + /* Initialize LVT Error register. */ lvt_error_t error; - lvt_lint_t lint; - tpr_t tpr; - svr_t svr; - icr_t icr; - tdcr_t tdcr; - lvt_tm_t tm; - ldr_t ldr; - dfr_t dfr; - uint32_t t1, t2; - - /* Initialize LVT Error register. */ + error.value = l_apic[LVT_Err]; error.masked = true; l_apic[LVT_Err] = error.value; - + /* Initialize LVT LINT0 register. */ + lvt_lint_t lint; + lint.value = l_apic[LVT_LINT0]; lint.masked = true; l_apic[LVT_LINT0] = lint.value; - + /* Initialize LVT LINT1 register. */ lint.value = l_apic[LVT_LINT1]; lint.masked = true; l_apic[LVT_LINT1] = lint.value; - + /* Task Priority Register initialization. */ + tpr_t tpr; + tpr.value = l_apic[TPR]; tpr.pri_sc = 0; @@ -379,4 +380,6 @@ /* Spurious-Interrupt Vector Register initialization. */ + svr_t svr; + svr.value = l_apic[SVR]; svr.vector = VECTOR_APIC_SPUR; @@ -384,9 +387,11 @@ svr.focus_checking = true; l_apic[SVR] = svr.value; - + if (CPU->arch.family >= 6) enable_l_apic_in_msr(); /* Interrupt Command Register initialization. */ + icr_t icr; + icr.lo = l_apic[ICRlo]; icr.delmod = DELMOD_INIT; @@ -398,9 +403,13 @@ /* Timer Divide Configuration Register initialization. */ + tdcr_t tdcr; + tdcr.value = l_apic[TDCR]; tdcr.div_value = DIVIDE_1; l_apic[TDCR] = tdcr.value; - + /* Program local timer. */ + lvt_tm_t tm; + tm.value = l_apic[LVT_Tm]; tm.vector = VECTOR_CLK; @@ -408,23 +417,24 @@ tm.masked = false; l_apic[LVT_Tm] = tm.value; - + /* * Measure and configure the timer to generate timer * interrupt with period 1s/HZ seconds. */ + uint32_t t1 = l_apic[CCRT]; + l_apic[ICRT] = 0xffffffff; + + while (l_apic[CCRT] == t1); + t1 = l_apic[CCRT]; - l_apic[ICRT] = 0xffffffff; - - while (l_apic[CCRT] == t1) - ; - - t1 = l_apic[CCRT]; - delay(1000000/HZ); - t2 = l_apic[CCRT]; - - l_apic[ICRT] = t1-t2; + delay(1000000 / HZ); + uint32_t t2 = l_apic[CCRT]; + + l_apic[ICRT] = t1 - t2; /* Program Logical Destination Register. */ ASSERT(CPU->id < 8); + ldr_t ldr; + ldr.value = l_apic[LDR]; ldr.id = (uint8_t) (1 << CPU->id); @@ -432,4 +442,6 @@ /* Program Destination Format Register for Flat mode. */ + dfr_t dfr; + dfr.value = l_apic[DFR]; dfr.model = MODEL_FLAT; @@ -447,16 +459,17 @@ { #ifdef LAPIC_VERBOSE + printf("LVT on cpu%" PRIs ", LAPIC ID: %" PRIu8 "\n", CPU->id, l_apic_id()); + lvt_tm_t tm; - lvt_lint_t lint; - lvt_error_t error; - - printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); - tm.value = l_apic[LVT_Tm]; printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); + + lvt_lint_t lint; lint.value = l_apic[LVT_LINT0]; printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); lint.value = l_apic[LVT_LINT1]; printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); + + lvt_error_t error; error.value = l_apic[LVT_Err]; printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); @@ -467,4 +480,5 @@ * * @return Local APIC ID. + * */ uint8_t l_apic_id(void) @@ -481,4 +495,5 @@ * * @return Content of the addressed IO APIC register. + * */ uint32_t io_apic_read(uint8_t address) @@ -495,7 +510,8 @@ * * @param address IO APIC register address. - * @param x Content to be written to the addressed IO APIC register. - */ -void io_apic_write(uint8_t address, uint32_t x) + * @param val Content to be written to the addressed IO APIC register. + * + */ +void io_apic_write(uint8_t address, uint32_t val) { io_regsel_t regsel; @@ -504,22 +520,26 @@ regsel.reg_addr = address; io_apic[IOREGSEL] = regsel.value; - io_apic[IOWIN] = x; + io_apic[IOWIN] = val; } /** Change some attributes of one item in I/O Redirection Table. * - * @param pin IO APIC pin number. - * @param dest Interrupt destination address. - * @param v Interrupt vector to trigger. + * @param pin IO APIC pin number. + * @param dest Interrupt destination address. + * @param vec Interrupt vector to trigger. * @param flags Flags. - */ -void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t v, int flags) -{ - io_redirection_reg_t reg; - int dlvr = DELMOD_FIXED; + * + */ +void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t vec, + unsigned int flags) +{ + unsigned int dlvr; if (flags & LOPRI) dlvr = DELMOD_LOWPRI; - + else + dlvr = DELMOD_FIXED; + + io_redirection_reg_t reg; reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2)); reg.hi = io_apic_read((uint8_t) (IOREDTBL + pin * 2 + 1)); @@ -530,6 +550,6 @@ reg.intpol = POLARITY_HIGH; reg.delmod = dlvr; - reg.intvec = v; - + reg.intvec = vec; + io_apic_write((uint8_t) (IOREDTBL + pin * 2), reg.lo); io_apic_write((uint8_t) (IOREDTBL + pin * 2 + 1), reg.hi); @@ -539,11 +559,9 @@ * * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). + * */ void io_apic_disable_irqs(uint16_t irqmask) { - io_redirection_reg_t reg; unsigned int i; - int pin; - for (i = 0; i < 16; i++) { if (irqmask & (1 << i)) { @@ -552,6 +570,8 @@ * mapping for the respective IRQ number. */ - pin = smp_irq_to_pin(i); + int pin = smp_irq_to_pin(i); if (pin != -1) { + io_redirection_reg_t reg; + reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2)); reg.masked = true; @@ -566,11 +586,9 @@ * * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). + * */ void io_apic_enable_irqs(uint16_t irqmask) { unsigned int i; - int pin; - io_redirection_reg_t reg; - for (i = 0; i < 16; i++) { if (irqmask & (1 << i)) { @@ -579,6 +597,8 @@ * mapping for the respective IRQ number. */ - pin = smp_irq_to_pin(i); + int pin = smp_irq_to_pin(i); if (pin != -1) { + io_redirection_reg_t reg; + reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2)); reg.masked = false; Index: kernel/arch/ia64/src/drivers/it.c =================================================================== --- kernel/arch/ia64/src/drivers/it.c (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/ia64/src/drivers/it.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -34,5 +34,5 @@ /** Interval Timer driver. */ - + #include #include @@ -45,11 +45,11 @@ #include -#define IT_SERVICE_CLOCKS 64 +#define IT_SERVICE_CLOCKS 64 -#define FREQ_NUMERATOR_SHIFT 32 -#define FREQ_NUMERATOR_MASK 0xffffffff00000000ULL +#define FREQ_NUMERATOR_SHIFT 32 +#define FREQ_NUMERATOR_MASK 0xffffffff00000000ULL -#define FREQ_DENOMINATOR_SHIFT 0 -#define FREQ_DENOMINATOR_MASK 0xffffffffULL +#define FREQ_DENOMINATOR_SHIFT 0 +#define FREQ_DENOMINATOR_MASK 0xffffffffULL uint64_t it_delta; @@ -63,6 +63,4 @@ void it_init(void) { - cr_itv_t itv; - if (config.cpu_active == 1) { irq_initialize(&it_irq); @@ -83,17 +81,19 @@ } - /* initialize Interval Timer external interrupt vector */ + /* Initialize Interval Timer external interrupt vector */ + cr_itv_t itv; + itv.value = itv_read(); itv.vector = INTERRUPT_TIMER; itv.m = 0; itv_write(itv.value); - - /* set Interval Timer Counter to zero */ + + /* Set Interval Timer Counter to zero */ itc_write(0); - /* generate first Interval Timer interrupt in IT_DELTA ticks */ + /* Generate first Interval Timer interrupt in IT_DELTA ticks */ itm_write(IT_DELTA); - - /* propagate changes */ + + /* Propagate changes */ srlz_d(); } @@ -104,4 +104,5 @@ * * @return Always IRQ_ACCEPT. + * */ irq_ownership_t it_claim(irq_t *irq) @@ -113,17 +114,14 @@ void it_interrupt(irq_t *irq) { - int64_t c; - int64_t m; - eoi_write(EOI); - m = itm_read(); + int64_t itm = itm_read(); - while (1) { - c = itc_read(); - c += IT_SERVICE_CLOCKS; - - m += IT_DELTA; - if (m - c < 0) + while (true) { + int64_t itc = itc_read(); + itc += IT_SERVICE_CLOCKS; + + itm += IT_DELTA; + if (itm - itc < 0) CPU->missed_clock_ticks++; else @@ -131,14 +129,14 @@ } - itm_write(m); - srlz_d(); /* propagate changes */ - + itm_write(itm); + srlz_d(); /* Propagate changes */ + /* * We are holding a lock which prevents preemption. * Release the lock, call clock() and reacquire the lock again. */ - spinlock_unlock(&irq->lock); + irq_spinlock_unlock(&irq->lock, false); clock(); - spinlock_lock(&irq->lock); + irq_spinlock_lock(&irq->lock, false); } Index: kernel/arch/ia64/src/interrupt.c =================================================================== --- kernel/arch/ia64/src/interrupt.c (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/ia64/src/interrupt.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -57,10 +57,11 @@ #include -#define VECTORS_64_BUNDLE 20 -#define VECTORS_16_BUNDLE 48 -#define VECTORS_16_BUNDLE_START 0x5000 -#define VECTOR_MAX 0x7f00 - -#define BUNDLE_SIZE 16 +#define VECTORS_64_BUNDLE 20 +#define VECTORS_16_BUNDLE 48 +#define VECTORS_16_BUNDLE_START 0x5000 + +#define VECTOR_MAX 0x7f00 + +#define BUNDLE_SIZE 16 static const char *vector_names_64_bundle[VECTORS_64_BUNDLE] = { @@ -134,8 +135,4 @@ static void dump_interrupted_context(istate_t *istate) { - const char *ifa = symtab_fmt_name_lookup(istate->cr_ifa); - const char *iipa = symtab_fmt_name_lookup(istate->cr_iipa); - const char *iip = symtab_fmt_name_lookup(istate->cr_iip); - putchar('\n'); printf("Interrupted context dump:\n"); @@ -149,8 +146,10 @@ istate->cr_ipsr); - printf("cr.iip=%#018llx, #%d\t(%s)\n", istate->cr_iip, - istate->cr_isr.ei, iip); - printf("cr.iipa=%#018llx\t(%s)\n", istate->cr_iipa, iipa); - printf("cr.ifa=%#018llx\t(%s)\n", istate->cr_ifa, ifa); + printf("cr.iip=%#018llx, #%d\t(%s)\n", istate->cr_iip, istate->cr_isr.ei, + symtab_fmt_name_lookup(istate->cr_iip)); + printf("cr.iipa=%#018llx\t(%s)\n", istate->cr_iipa, + symtab_fmt_name_lookup(istate->cr_iipa)); + printf("cr.ifa=%#018llx\t(%s)\n", istate->cr_ifa, + symtab_fmt_name_lookup(istate->cr_ifa)); } @@ -218,5 +217,5 @@ istate->cr_ipsr.ri++; } - + return syscall_handler(istate->in0, istate->in1, istate->in2, istate->in3, istate->in4, istate->in5, istate->in6); @@ -234,16 +233,18 @@ static void end_of_local_irq(void) { - asm volatile ("mov cr.eoi=r0;;"); -} - + asm volatile ( + "mov cr.eoi=r0;;" + ); +} void external_interrupt(uint64_t vector, istate_t *istate) { cr_ivr_t ivr; - irq_t *irq; ivr.value = ivr_read(); srlz_d(); - + + irq_t *irq; + switch (ivr.vector) { case INTERRUPT_SPURIOUS: @@ -252,5 +253,5 @@ #endif break; - + #ifdef CONFIG_SMP case VECTOR_TLB_SHOOTDOWN_IPI: @@ -259,10 +260,10 @@ break; #endif - + case INTERRUPT_TIMER: irq = irq_dispatch_and_lock(ivr.vector); if (irq) { irq->handler(irq); - spinlock_unlock(&irq->lock); + irq_spinlock_unlock(&irq->lock, false); } else { panic("Unhandled Internal Timer Interrupt (%d).", @@ -283,5 +284,5 @@ if (!irq->preack) end_of_local_irq(); - spinlock_unlock(&irq->lock); + irq_spinlock_unlock(&irq->lock, false); } else { /* Index: kernel/arch/mips32/include/asm.h =================================================================== --- kernel/arch/mips32/include/asm.h (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/mips32/include/asm.h (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -39,5 +39,4 @@ #include - static inline void cpu_sleep(void) { @@ -47,20 +46,21 @@ /** Return base address of current stack - * + * * Return the base address of the current stack. * The stack is assumed to be STACK_SIZE bytes long. * The stack must start on page boundary. + * */ static inline uintptr_t get_stack_base(void) { - uintptr_t v; + uintptr_t base; asm volatile ( - "and %0, $29, %1\n" - : "=r" (v) - : "r" (~(STACK_SIZE-1)) + "and %[base], $29, %[mask]\n" + : [base] "=r" (base) + : [mask] "r" (~(STACK_SIZE - 1)) ); - return v; + return base; } @@ -78,15 +78,15 @@ static inline void pio_write_8(ioport8_t *port, uint8_t v) { - *port = v; + *port = v; } static inline void pio_write_16(ioport16_t *port, uint16_t v) { - *port = v; + *port = v; } static inline void pio_write_32(ioport32_t *port, uint32_t v) { - *port = v; + *port = v; } Index: kernel/arch/mips32/include/debugger.h =================================================================== --- kernel/arch/mips32/include/debugger.h (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/mips32/include/debugger.h (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -41,25 +41,33 @@ #define BKPOINTS_MAX 10 -#define BKPOINT_INPROG (1 << 0) /**< Breakpoint was shot */ -#define BKPOINT_ONESHOT (1 << 1) /**< One-time breakpoint,mandatory for j/b - instructions */ -#define BKPOINT_REINST (1 << 2) /**< Breakpoint is set on the next - instruction, so that it could be - reinstalled on the previous one */ -#define BKPOINT_FUNCCALL (1 << 3) /**< Call a predefined function */ +/** Breakpoint was shot */ +#define BKPOINT_INPROG (1 << 0) + +/** One-time breakpoint, mandatory for j/b instructions */ +#define BKPOINT_ONESHOT (1 << 1) + +/** + * Breakpoint is set on the next instruction, so that it + * could be reinstalled on the previous one + */ +#define BKPOINT_REINST (1 << 2) + +/** Call a predefined function */ +#define BKPOINT_FUNCCALL (1 << 3) + typedef struct { - uintptr_t address; /**< Breakpoint address */ - unative_t instruction; /**< Original instruction */ + uintptr_t address; /**< Breakpoint address */ + unative_t instruction; /**< Original instruction */ unative_t nextinstruction; /**< Original instruction following break */ - int flags; /**< Flags regarding breakpoint */ + unsigned int flags; /**< Flags regarding breakpoint */ size_t counter; - void (*bkfunc)(void *b, istate_t *istate); + void (*bkfunc)(void *, istate_t *); } bpinfo_t; +extern bpinfo_t breakpoints[BKPOINTS_MAX]; + extern void debugger_init(void); -void debugger_bpoint(istate_t *istate); - -extern bpinfo_t breakpoints[BKPOINTS_MAX]; +extern void debugger_bpoint(istate_t *); #endif Index: kernel/arch/mips32/include/mm/as.h =================================================================== --- kernel/arch/mips32/include/mm/as.h (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/mips32/include/mm/as.h (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -27,5 +27,5 @@ */ -/** @addtogroup mips32mm +/** @addtogroup mips32mm * @{ */ @@ -36,5 +36,5 @@ #define KERN_mips32_AS_H_ -#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0 +#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0 #define KERNEL_ADDRESS_SPACE_START_ARCH (unsigned long) 0x80000000 Index: kernel/arch/mips32/src/debugger.c =================================================================== --- kernel/arch/mips32/src/debugger.c (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/mips32/src/debugger.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -46,9 +46,12 @@ bpinfo_t breakpoints[BKPOINTS_MAX]; -SPINLOCK_INITIALIZE(bkpoint_lock); +IRQ_SPINLOCK_STATIC_INITIALIZE(bkpoint_lock); #ifdef CONFIG_KCONSOLE -static int cmd_print_breakpoints(cmd_arg_t *argv); +static int cmd_print_breakpoints(cmd_arg_t *); +static int cmd_del_breakpoint(cmd_arg_t *); +static int cmd_add_breakpoint(cmd_arg_t *); + static cmd_info_t bkpts_info = { .name = "bkpts", @@ -58,11 +61,11 @@ }; -static int cmd_del_breakpoint(cmd_arg_t *argv); static cmd_arg_t del_argv = { .type = ARG_TYPE_INT }; + static cmd_info_t delbkpt_info = { .name = "delbkpt", - .description = "delbkpt - Delete breakpoint.", + .description = "Delete breakpoint.", .func = cmd_del_breakpoint, .argc = 1, @@ -70,12 +73,11 @@ }; -static int cmd_add_breakpoint(cmd_arg_t *argv); static cmd_arg_t add_argv = { .type = ARG_TYPE_INT }; + static cmd_info_t addbkpt_info = { .name = "addbkpt", - .description = "addbkpt <&symbol> - new bkpoint. Break on J/Branch " - "insts unsupported.", + .description = "Add bkpoint (break on J/Branch insts unsupported).", .func = cmd_add_breakpoint, .argc = 1, @@ -89,6 +91,5 @@ static cmd_info_t addbkpte_info = { .name = "addbkpte", - .description = "addebkpte <&symbol> <&func> - new bkpoint. Call " - "func(or Nothing if 0).", + .description = "Add bkpoint with a trigger function.", .func = cmd_add_breakpoint, .argc = 2, @@ -100,156 +101,159 @@ uint32_t value; } jmpinstr[] = { - {0xf3ff0000, 0x41000000}, /* BCzF */ - {0xf3ff0000, 0x41020000}, /* BCzFL */ - {0xf3ff0000, 0x41010000}, /* BCzT */ - {0xf3ff0000, 0x41030000}, /* BCzTL */ - {0xfc000000, 0x10000000}, /* BEQ */ - {0xfc000000, 0x50000000}, /* BEQL */ - {0xfc1f0000, 0x04010000}, /* BEQL */ - {0xfc1f0000, 0x04110000}, /* BGEZAL */ - {0xfc1f0000, 0x04130000}, /* BGEZALL */ - {0xfc1f0000, 0x04030000}, /* BGEZL */ - {0xfc1f0000, 0x1c000000}, /* BGTZ */ - {0xfc1f0000, 0x5c000000}, /* BGTZL */ - {0xfc1f0000, 0x18000000}, /* BLEZ */ - {0xfc1f0000, 0x58000000}, /* BLEZL */ - {0xfc1f0000, 0x04000000}, /* BLTZ */ - {0xfc1f0000, 0x04100000}, /* BLTZAL */ - {0xfc1f0000, 0x04120000}, /* BLTZALL */ - {0xfc1f0000, 0x04020000}, /* BLTZL */ - {0xfc000000, 0x14000000}, /* BNE */ - {0xfc000000, 0x54000000}, /* BNEL */ - {0xfc000000, 0x08000000}, /* J */ - {0xfc000000, 0x0c000000}, /* JAL */ - {0xfc1f07ff, 0x00000009}, /* JALR */ - {0, 0} /* EndOfTable */ -}; - + {0xf3ff0000, 0x41000000}, /* BCzF */ + {0xf3ff0000, 0x41020000}, /* BCzFL */ + {0xf3ff0000, 0x41010000}, /* BCzT */ + {0xf3ff0000, 0x41030000}, /* BCzTL */ + {0xfc000000, 0x10000000}, /* BEQ */ + {0xfc000000, 0x50000000}, /* BEQL */ + {0xfc1f0000, 0x04010000}, /* BEQL */ + {0xfc1f0000, 0x04110000}, /* BGEZAL */ + {0xfc1f0000, 0x04130000}, /* BGEZALL */ + {0xfc1f0000, 0x04030000}, /* BGEZL */ + {0xfc1f0000, 0x1c000000}, /* BGTZ */ + {0xfc1f0000, 0x5c000000}, /* BGTZL */ + {0xfc1f0000, 0x18000000}, /* BLEZ */ + {0xfc1f0000, 0x58000000}, /* BLEZL */ + {0xfc1f0000, 0x04000000}, /* BLTZ */ + {0xfc1f0000, 0x04100000}, /* BLTZAL */ + {0xfc1f0000, 0x04120000}, /* BLTZALL */ + {0xfc1f0000, 0x04020000}, /* BLTZL */ + {0xfc000000, 0x14000000}, /* BNE */ + {0xfc000000, 0x54000000}, /* BNEL */ + {0xfc000000, 0x08000000}, /* J */ + {0xfc000000, 0x0c000000}, /* JAL */ + {0xfc1f07ff, 0x00000009}, /* JALR */ + {0, 0} /* end of table */ +}; /** Test, if the given instruction is a jump or branch instruction * * @param instr Instruction code - * @return true - it is jump instruction, false otherwise + * + * @return true if it is jump instruction, false otherwise * */ static bool is_jump(unative_t instr) { - int i; - + unsigned int i; + for (i = 0; jmpinstr[i].andmask; i++) { if ((instr & jmpinstr[i].andmask) == jmpinstr[i].value) return true; } - + return false; } -/** Add new breakpoint to table */ +/** Add new breakpoint to table + * + */ int cmd_add_breakpoint(cmd_arg_t *argv) { - bpinfo_t *cur = NULL; - ipl_t ipl; - int i; - if (argv->intval & 0x3) { printf("Not aligned instruction, forgot to use &symbol?\n"); return 1; } - ipl = interrupts_disable(); - spinlock_lock(&bkpoint_lock); - + + irq_spinlock_lock(&bkpoint_lock, true); + /* Check, that the breakpoints do not conflict */ + unsigned int i; for (i = 0; i < BKPOINTS_MAX; i++) { - if (breakpoints[i].address == (uintptr_t)argv->intval) { + if (breakpoints[i].address == (uintptr_t) argv->intval) { printf("Duplicate breakpoint %d.\n", i); - spinlock_unlock(&bkpoint_lock); - interrupts_restore(ipl); + irq_spinlock_unlock(&bkpoint_lock, true); return 0; - } else if (breakpoints[i].address == (uintptr_t)argv->intval + - sizeof(unative_t) || breakpoints[i].address == - (uintptr_t)argv->intval - sizeof(unative_t)) { + } else if ((breakpoints[i].address == (uintptr_t) argv->intval + + sizeof(unative_t)) || (breakpoints[i].address == + (uintptr_t) argv->intval - sizeof(unative_t))) { printf("Adjacent breakpoints not supported, conflict " "with %d.\n", i); - spinlock_unlock(&bkpoint_lock); - interrupts_restore(ipl); + irq_spinlock_unlock(&bkpoint_lock, true); return 0; } } - - for (i = 0; i < BKPOINTS_MAX; i++) + + bpinfo_t *cur = NULL; + + for (i = 0; i < BKPOINTS_MAX; i++) { if (!breakpoints[i].address) { cur = &breakpoints[i]; break; } + } + if (!cur) { printf("Too many breakpoints.\n"); - spinlock_unlock(&bkpoint_lock); - interrupts_restore(ipl); + irq_spinlock_unlock(&bkpoint_lock, true); return 0; } + + printf("Adding breakpoint on address %p\n", argv->intval); + cur->address = (uintptr_t) argv->intval; - printf("Adding breakpoint on address: %p\n", argv->intval); - cur->instruction = ((unative_t *)cur->address)[0]; - cur->nextinstruction = ((unative_t *)cur->address)[1]; + cur->instruction = ((unative_t *) cur->address)[0]; + cur->nextinstruction = ((unative_t *) cur->address)[1]; if (argv == &add_argv) { cur->flags = 0; - } else { /* We are add extended */ + } else { /* We are add extended */ cur->flags = BKPOINT_FUNCCALL; cur->bkfunc = (void (*)(void *, istate_t *)) argv[1].intval; } + if (is_jump(cur->instruction)) cur->flags |= BKPOINT_ONESHOT; + cur->counter = 0; - + /* Set breakpoint */ - *((unative_t *)cur->address) = 0x0d; + *((unative_t *) cur->address) = 0x0d; smc_coherence(cur->address); - - spinlock_unlock(&bkpoint_lock); - interrupts_restore(ipl); - + + irq_spinlock_unlock(&bkpoint_lock, true); + return 1; } -/** Remove breakpoint from table */ +/** Remove breakpoint from table + * + */ int cmd_del_breakpoint(cmd_arg_t *argv) { - bpinfo_t *cur; - ipl_t ipl; - if (argv->intval > BKPOINTS_MAX) { printf("Invalid breakpoint number.\n"); return 0; } - ipl = interrupts_disable(); - spinlock_lock(&bkpoint_lock); - - cur = &breakpoints[argv->intval]; + + irq_spinlock_lock(&bkpoint_lock, true); + + bpinfo_t *cur = &breakpoints[argv->intval]; if (!cur->address) { printf("Breakpoint does not exist.\n"); - spinlock_unlock(&bkpoint_lock); - interrupts_restore(ipl); + irq_spinlock_unlock(&bkpoint_lock, true); return 0; } + if ((cur->flags & BKPOINT_INPROG) && (cur->flags & BKPOINT_ONESHOT)) { printf("Cannot remove one-shot breakpoint in-progress\n"); - spinlock_unlock(&bkpoint_lock); - interrupts_restore(ipl); + irq_spinlock_unlock(&bkpoint_lock, true); return 0; } - ((uint32_t *)cur->address)[0] = cur->instruction; - smc_coherence(((uint32_t *)cur->address)[0]); - ((uint32_t *)cur->address)[1] = cur->nextinstruction; - smc_coherence(((uint32_t *)cur->address)[1]); - + + ((uint32_t *) cur->address)[0] = cur->instruction; + smc_coherence(((uint32_t *) cur->address)[0]); + ((uint32_t *) cur->address)[1] = cur->nextinstruction; + smc_coherence(((uint32_t *) cur->address)[1]); + cur->address = NULL; - - spinlock_unlock(&bkpoint_lock); - interrupts_restore(ipl); + + irq_spinlock_unlock(&bkpoint_lock, true); return 1; } -/** Print table of active breakpoints */ +/** Print table of active breakpoints + * + */ int cmd_print_breakpoints(cmd_arg_t *argv) { @@ -276,59 +280,64 @@ } -#endif - -/** Initialize debugger */ +#endif /* CONFIG_KCONSOLE */ + +/** Initialize debugger + * + */ void debugger_init() { - int i; - + unsigned int i; + for (i = 0; i < BKPOINTS_MAX; i++) breakpoints[i].address = NULL; - + #ifdef CONFIG_KCONSOLE cmd_initialize(&bkpts_info); if (!cmd_register(&bkpts_info)) printf("Cannot register command %s\n", bkpts_info.name); - + cmd_initialize(&delbkpt_info); if (!cmd_register(&delbkpt_info)) printf("Cannot register command %s\n", delbkpt_info.name); - + cmd_initialize(&addbkpt_info); if (!cmd_register(&addbkpt_info)) printf("Cannot register command %s\n", addbkpt_info.name); - + cmd_initialize(&addbkpte_info); if (!cmd_register(&addbkpte_info)) printf("Cannot register command %s\n", addbkpte_info.name); -#endif +#endif /* CONFIG_KCONSOLE */ } /** Handle breakpoint * - * Find breakpoint in breakpoint table. + * Find breakpoint in breakpoint table. * If found, call kconsole, set break on next instruction and reexecute. * If we are on "next instruction", set it back on the first and reexecute. * If breakpoint not found in breakpoint table, call kconsole and start * next instruction. + * */ void debugger_bpoint(istate_t *istate) { - bpinfo_t *cur = NULL; - uintptr_t fireaddr = istate->epc; - int i; - /* test branch delay slot */ if (cp0_cause_read() & 0x80000000) panic("Breakpoint in branch delay slot not supported."); - - spinlock_lock(&bkpoint_lock); + + irq_spinlock_lock(&bkpoint_lock, false); + + bpinfo_t *cur = NULL; + uintptr_t fireaddr = istate->epc; + unsigned int i; + for (i = 0; i < BKPOINTS_MAX; i++) { /* Normal breakpoint */ - if (fireaddr == breakpoints[i].address && - !(breakpoints[i].flags & BKPOINT_REINST)) { + if ((fireaddr == breakpoints[i].address) && + (!(breakpoints[i].flags & BKPOINT_REINST))) { cur = &breakpoints[i]; break; } + /* Reinst only breakpoint */ if ((breakpoints[i].flags & BKPOINT_REINST) && @@ -338,24 +347,28 @@ } } + if (cur) { if (cur->flags & BKPOINT_REINST) { /* Set breakpoint on first instruction */ - ((uint32_t *)cur->address)[0] = 0x0d; + ((uint32_t *) cur->address)[0] = 0x0d; smc_coherence(((uint32_t *)cur->address)[0]); + /* Return back the second */ - ((uint32_t *)cur->address)[1] = cur->nextinstruction; - smc_coherence(((uint32_t *)cur->address)[1]); + ((uint32_t *) cur->address)[1] = cur->nextinstruction; + smc_coherence(((uint32_t *) cur->address)[1]); + cur->flags &= ~BKPOINT_REINST; - spinlock_unlock(&bkpoint_lock); + irq_spinlock_unlock(&bkpoint_lock, false); return; - } + } + if (cur->flags & BKPOINT_INPROG) printf("Warning: breakpoint recursion\n"); if (!(cur->flags & BKPOINT_FUNCCALL)) { - printf("***Breakpoint %d: %p in %s.\n", i, fireaddr, - symtab_fmt_name_lookup(istate->epc)); - } - + printf("***Breakpoint %u: %p in %s.\n", i, fireaddr, + symtab_fmt_name_lookup(fireaddr)); + } + /* Return first instruction back */ ((uint32_t *)cur->address)[0] = cur->instruction; @@ -371,10 +384,12 @@ printf("***Breakpoint %d: %p in %s.\n", i, fireaddr, symtab_fmt_name_lookup(fireaddr)); - + /* Move on to next instruction */ istate->epc += 4; } + if (cur) cur->counter++; + if (cur && (cur->flags & BKPOINT_FUNCCALL)) { /* Allow zero bkfunc, just for counting */ @@ -383,26 +398,31 @@ } else { #ifdef CONFIG_KCONSOLE - /* This disables all other processors - we are not SMP, + /* + * This disables all other processors - we are not SMP, * actually this gets us to cpu_halt, if scheduler() is run * - we generally do not want scheduler to be run from debug, * so this is a good idea - */ + */ atomic_set(&haltstate, 1); - spinlock_unlock(&bkpoint_lock); + irq_spinlock_unlock(&bkpoint_lock, false); kconsole("debug", "Debug console ready.\n", false); - spinlock_lock(&bkpoint_lock); + irq_spinlock_lock(&bkpoint_lock, false); atomic_set(&haltstate, 0); #endif } - if (cur && cur->address == fireaddr && (cur->flags & BKPOINT_INPROG)) { + + if ((cur) && (cur->address == fireaddr) + && ((cur->flags & BKPOINT_INPROG))) { /* Remove one-shot breakpoint */ if ((cur->flags & BKPOINT_ONESHOT)) cur->address = NULL; + /* Remove in-progress flag */ cur->flags &= ~BKPOINT_INPROG; - } - spinlock_unlock(&bkpoint_lock); + } + + irq_spinlock_unlock(&bkpoint_lock, false); } Index: kernel/arch/mips32/src/exception.c =================================================================== --- kernel/arch/mips32/src/exception.c (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/mips32/src/exception.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -27,5 +27,5 @@ */ -/** @addtogroup mips32 +/** @addtogroup mips32 * @{ */ @@ -67,5 +67,5 @@ "Floating Point", NULL, NULL, NULL, NULL, NULL, NULL, NULL, - "WatchHi/WatchLo", /* 23 */ + "WatchHi/WatchLo", /* 23 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, "Virtual Coherency - data", @@ -74,9 +74,7 @@ static void print_regdump(istate_t *istate) { - const char *pcsymbol = symtab_fmt_name_lookup(istate->epc); - const char *rasymbol = symtab_fmt_name_lookup(istate->ra); - - printf("PC: %#x(%s) RA: %#x(%s), SP(%p)\n", istate->epc, pcsymbol, - istate->ra, rasymbol, istate->sp); + printf("PC: %#x(%s) RA: %#x(%s), SP(%p)\n", istate->epc, + symtab_fmt_name_lookup(istate->epc), istate->ra, + symtab_fmt_name_lookup(istate->ra), istate->sp); } @@ -135,10 +133,8 @@ static void interrupt_exception(int n, istate_t *istate) { - uint32_t cause; - int i; + /* Decode interrupt number and process the interrupt */ + uint32_t cause = (cp0_cause_read() >> 8) & 0xff; - /* decode interrupt number and process the interrupt */ - cause = (cp0_cause_read() >> 8) & 0xff; - + unsigned int i; for (i = 0; i < 8; i++) { if (cause & (1 << i)) { @@ -149,5 +145,5 @@ */ irq->handler(irq); - spinlock_unlock(&irq->lock); + irq_spinlock_unlock(&irq->lock, false); } else { /* @@ -172,5 +168,5 @@ { int i; - + /* Clear exception table */ for (i = 0; i < IVT_ITEMS; i++) Index: kernel/arch/mips32/src/interrupt.c =================================================================== --- kernel/arch/mips32/src/interrupt.c (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/mips32/src/interrupt.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -48,4 +48,10 @@ function virtual_timer_fnc = NULL; static irq_t timer_irq; + +// TODO: This is SMP unsafe!!! + +uint32_t count_hi = 0; +static unsigned long nextcount; +static unsigned long lastcount; /** Disable interrupts. @@ -99,10 +105,7 @@ } -/* TODO: This is SMP unsafe!!! */ -uint32_t count_hi = 0; -static unsigned long nextcount; -static unsigned long lastcount; - -/** Start hardware clock */ +/** Start hardware clock + * + */ static void timer_start(void) { @@ -119,16 +122,16 @@ static void timer_irq_handler(irq_t *irq) { - unsigned long drift; - if (cp0_count_read() < lastcount) /* Count overflow detected */ count_hi++; + lastcount = cp0_count_read(); - drift = cp0_count_read() - nextcount; + unsigned long drift = cp0_count_read() - nextcount; while (drift > cp0_compare_value) { drift -= cp0_compare_value; CPU->missed_clock_ticks++; } + nextcount = cp0_count_read() + cp0_compare_value - drift; cp0_compare_write(nextcount); @@ -138,7 +141,7 @@ * Release the lock, call clock() and reacquire the lock again. */ - spinlock_unlock(&irq->lock); + irq_spinlock_unlock(&irq->lock, false); clock(); - spinlock_lock(&irq->lock); + irq_spinlock_lock(&irq->lock, false); if (virtual_timer_fnc != NULL) Index: kernel/arch/ppc32/include/asm.h =================================================================== --- kernel/arch/ppc32/include/asm.h (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/ppc32/include/asm.h (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -39,4 +39,5 @@ #include #include +#include static inline uint32_t msr_read(void) @@ -58,4 +59,38 @@ :: [msr] "r" (msr) ); +} + +static inline void sr_set(uint32_t flags, asid_t asid, uint32_t sr) +{ + asm volatile ( + "mtsrin %[value], %[sr]\n" + :: [value] "r" ((flags << 16) + (asid << 4) + sr), + [sr] "r" (sr << 28) + ); +} + +static inline uint32_t sr_get(uint32_t vaddr) +{ + uint32_t vsid; + + asm volatile ( + "mfsrin %[vsid], %[vaddr]\n" + : [vsid] "=r" (vsid) + : [vaddr] "r" (vaddr) + ); + + return vsid; +} + +static inline uint32_t sdr1_get(void) +{ + uint32_t sdr1; + + asm volatile ( + "mfsdr1 %[sdr1]\n" + : [sdr1] "=r" (sdr1) + ); + + return sdr1; } Index: kernel/arch/ppc32/include/mm/frame.h =================================================================== --- kernel/arch/ppc32/include/mm/frame.h (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/ppc32/include/mm/frame.h (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -46,4 +46,16 @@ extern uintptr_t last_frame; +static inline uint32_t physmem_top(void) +{ + uint32_t physmem; + + asm volatile ( + "mfsprg3 %[physmem]\n" + : [physmem] "=r" (physmem) + ); + + return physmem; +} + extern void frame_arch_init(void); extern void physmem_print(void); Index: kernel/arch/ppc32/src/debug/stacktrace.c =================================================================== --- kernel/arch/ppc32/src/debug/stacktrace.c (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/ppc32/src/debug/stacktrace.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -66,10 +66,12 @@ bool uspace_frame_pointer_prev(uintptr_t fp, uintptr_t *prev) { - return false; + return !copy_from_uspace((void *) prev, + (uint32_t *) fp + FRAME_OFFSET_FP_PREV, sizeof(*prev)); } bool uspace_return_address_get(uintptr_t fp, uintptr_t *ra) { - return false; + return !copy_from_uspace((void *) ra, (uint32_t *) fp + FRAME_OFFSET_RA, + sizeof(*ra)); } Index: kernel/arch/ppc32/src/mm/as.c =================================================================== --- kernel/arch/ppc32/src/mm/as.c (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/ppc32/src/mm/as.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -55,26 +55,13 @@ void as_install_arch(as_t *as) { - asid_t asid; uint32_t sr; - - asid = as->asid; /* Lower 2 GB, user and supervisor access */ - for (sr = 0; sr < 8; sr++) { - asm volatile ( - "mtsrin %0, %1\n" - : - : "r" ((0x6000 << 16) + (asid << 4) + sr), "r" (sr << 28) - ); - } + for (sr = 0; sr < 8; sr++) + sr_set(0x6000, as->asid, sr); /* Upper 2 GB, only supervisor access */ - for (sr = 8; sr < 16; sr++) { - asm volatile ( - "mtsrin %0, %1\n" - : - : "r" ((0x4000 << 16) + (asid << 4) + sr), "r" (sr << 28) - ); - } + for (sr = 8; sr < 16; sr++) + sr_set(0x4000, as->asid, sr); } Index: kernel/arch/ppc32/src/mm/frame.c =================================================================== --- kernel/arch/ppc32/src/mm/frame.c (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/ppc32/src/mm/frame.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -45,12 +45,11 @@ void physmem_print(void) { - unsigned int i; - printf("Base Size\n"); printf("---------- ----------\n"); - + + size_t i; for (i = 0; i < memmap.cnt; i++) { printf("%#10x %#10x\n", memmap.zones[i].start, - memmap.zones[i].size); + memmap.zones[i].size); } } @@ -60,11 +59,11 @@ pfn_t minconf = 2; size_t i; - pfn_t start, conf; - size_t size; for (i = 0; i < memmap.cnt; i++) { - start = ADDR2PFN(ALIGN_UP((uintptr_t) memmap.zones[i].start, FRAME_SIZE)); - size = SIZE2FRAMES(ALIGN_DOWN(memmap.zones[i].size, FRAME_SIZE)); + pfn_t start = ADDR2PFN(ALIGN_UP((uintptr_t) memmap.zones[i].start, + FRAME_SIZE)); + size_t size = SIZE2FRAMES(ALIGN_DOWN(memmap.zones[i].size, FRAME_SIZE)); + pfn_t conf; if ((minconf < start) || (minconf >= start + size)) conf = start; @@ -73,6 +72,8 @@ zone_create(start, size, conf, 0); - if (last_frame < ALIGN_UP((uintptr_t) memmap.zones[i].start + memmap.zones[i].size, FRAME_SIZE)) - last_frame = ALIGN_UP((uintptr_t) memmap.zones[i].start + memmap.zones[i].size, FRAME_SIZE); + if (last_frame < ALIGN_UP((uintptr_t) memmap.zones[i].start + + memmap.zones[i].size, FRAME_SIZE)) + last_frame = ALIGN_UP((uintptr_t) memmap.zones[i].start + + memmap.zones[i].size, FRAME_SIZE); } @@ -82,10 +83,8 @@ /* Mark the Page Hash Table frames as unavailable */ - uint32_t sdr1; - asm volatile ( - "mfsdr1 %0\n" - : "=r" (sdr1) - ); - frame_mark_unavailable(ADDR2PFN(sdr1 & 0xffff000), 16); // FIXME + uint32_t sdr1 = sdr1_get(); + + // FIXME: compute size of PHT exactly + frame_mark_unavailable(ADDR2PFN(sdr1 & 0xffff000), 16); } Index: kernel/arch/ppc32/src/mm/tlb.c =================================================================== --- kernel/arch/ppc32/src/mm/tlb.c (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/ppc32/src/mm/tlb.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -45,6 +45,6 @@ static unsigned int seed = 10; -static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42; - +static unsigned int seed_real + __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42; /** Try to find PTE for faulting address @@ -54,21 +54,21 @@ * if lock is true. * - * @param as Address space. - * @param lock Lock/unlock the address space. - * @param badvaddr Faulting virtual address. - * @param access Access mode that caused the fault. - * @param istate Pointer to interrupted state. - * @param pfrc Pointer to variable where as_page_fault() return code - * will be stored. - * @return PTE on success, NULL otherwise. - * - */ -static pte_t * -find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access, - istate_t *istate, int *pfrc) + * @param as Address space. + * @param lock Lock/unlock the address space. + * @param badvaddr Faulting virtual address. + * @param access Access mode that caused the fault. + * @param istate Pointer to interrupted state. + * @param pfrc Pointer to variable where as_page_fault() return code + * will be stored. + * + * @return PTE on success, NULL otherwise. + * + */ +static pte_t *find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, + int access, istate_t *istate, int *pfrc) { /* * Check if the mapping exists in page tables. - */ + */ pte_t *pte = page_mapping_find(as, badvaddr); if ((pte) && (pte->present)) { @@ -79,6 +79,4 @@ return pte; } else { - int rc; - /* * Mapping not found in page tables. @@ -86,5 +84,7 @@ */ page_table_unlock(as, lock); - switch (rc = as_page_fault(badvaddr, access, istate)) { + + int rc = as_page_fault(badvaddr, access, istate); + switch (rc) { case AS_PF_OK: /* @@ -107,8 +107,7 @@ default: panic("Unexpected rc (%d).", rc); - } - } -} - + } + } +} static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) @@ -123,5 +122,4 @@ } - static void pht_insert(const uintptr_t vaddr, const pte_t *pte) { @@ -129,16 +127,8 @@ uint32_t api = (vaddr >> 22) & 0x3f; - uint32_t vsid; - asm volatile ( - "mfsrin %0, %1\n" - : "=r" (vsid) - : "r" (vaddr) - ); - - uint32_t sdr1; - asm volatile ( - "mfsdr1 %0\n" - : "=r" (sdr1) - ); + uint32_t vsid = sr_get(vaddr); + uint32_t sdr1 = sdr1_get(); + + // FIXME: compute size of PHT exactly phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); @@ -215,5 +205,4 @@ } - /** Process Instruction/Data Storage Exception * @@ -224,7 +213,4 @@ void pht_refill(int n, istate_t *istate) { - uintptr_t badvaddr; - pte_t *pte; - int pfrc; as_t *as; bool lock; @@ -238,13 +224,17 @@ } + uintptr_t badvaddr; + if (n == VECTOR_DATA_STORAGE) badvaddr = istate->dar; else badvaddr = istate->pc; - + page_table_lock(as, lock); - pte = find_mapping_and_check(as, lock, badvaddr, + int pfrc; + pte_t *pte = find_mapping_and_check(as, lock, badvaddr, PF_ACCESS_READ /* FIXME */, istate, &pfrc); + if (!pte) { switch (pfrc) { @@ -264,5 +254,6 @@ } - pte->accessed = 1; /* Record access to PTE */ + /* Record access to PTE */ + pte->accessed = 1; pht_insert(badvaddr, pte); @@ -274,5 +265,4 @@ pht_refill_fail(badvaddr, istate); } - /** Process Instruction/Data Storage Exception in Real Mode @@ -291,9 +281,5 @@ badvaddr = istate->pc; - uint32_t physmem; - asm volatile ( - "mfsprg3 %0\n" - : "=r" (physmem) - ); + uint32_t physmem = physmem_top(); if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) @@ -303,16 +289,8 @@ uint32_t api = (badvaddr >> 22) & 0x3f; - uint32_t vsid; - asm volatile ( - "mfsrin %0, %1\n" - : "=r" (vsid) - : "r" (badvaddr) - ); - - uint32_t sdr1; - asm volatile ( - "mfsdr1 %0\n" - : "=r" (sdr1) - ); + uint32_t vsid = sr_get(badvaddr); + uint32_t sdr1 = sdr1_get(); + + // FIXME: compute size of PHT exactly phte_t *phte_real = (phte_t *) (sdr1 & 0xffff0000); @@ -396,5 +374,4 @@ } - /** Process ITLB/DTLB Miss Exception in Real Mode * @@ -404,10 +381,5 @@ { uint32_t badvaddr = tlbmiss & 0xfffffffc; - - uint32_t physmem; - asm volatile ( - "mfsprg3 %0\n" - : "=r" (physmem) - ); + uint32_t physmem = physmem_top(); if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) @@ -420,15 +392,14 @@ uint32_t index = 0; asm volatile ( - "mtspr 981, %0\n" - "mtspr 982, %1\n" - "tlbld %2\n" - "tlbli %2\n" - : "=r" (index) - : "r" (ptehi), - "r" (ptelo) + "mtspr 981, %[ptehi]\n" + "mtspr 982, %[ptelo]\n" + "tlbld %[index]\n" + "tlbli %[index]\n" + : [index] "=r" (index) + : [ptehi] "r" (ptehi), + [ptelo] "r" (ptelo) ); } - void tlb_arch_init(void) { @@ -436,15 +407,15 @@ } - void tlb_invalidate_all(void) { uint32_t index; + asm volatile ( - "li %0, 0\n" + "li %[index], 0\n" "sync\n" ".rept 64\n" - "tlbie %0\n" - "addi %0, %0, 0x1000\n" + " tlbie %[index]\n" + " addi %[index], %[index], 0x1000\n" ".endr\n" @@ -452,19 +423,16 @@ "tlbsync\n" "sync\n" - : "=r" (index) + : [index] "=r" (index) ); } - void tlb_invalidate_asid(asid_t asid) { - uint32_t sdr1; - asm volatile ( - "mfsdr1 %0\n" - : "=r" (sdr1) - ); + uint32_t sdr1 = sdr1_get(); + + // FIXME: compute size of PHT exactly phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); - uint32_t i; + size_t i; for (i = 0; i < 8192; i++) { if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && @@ -472,7 +440,7 @@ phte[i].v = 0; } + tlb_invalidate_all(); } - void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt) @@ -482,15 +450,17 @@ } - #define PRINT_BAT(name, ureg, lreg) \ asm volatile ( \ - "mfspr %0," #ureg "\n" \ - "mfspr %1," #lreg "\n" \ - : "=r" (upper), "=r" (lower) \ + "mfspr %[upper], " #ureg "\n" \ + "mfspr %[lower], " #lreg "\n" \ + : [upper] "=r" (upper), \ + [lower] "=r" (lower) \ ); \ + \ mask = (upper & 0x1ffc) >> 2; \ if (upper & 3) { \ uint32_t tmp = mask; \ length = 128; \ + \ while (tmp) { \ if ((tmp & 1) == 0) { \ @@ -503,4 +473,5 @@ } else \ length = 0; \ + \ printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \ sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \ @@ -515,10 +486,6 @@ for (sr = 0; sr < 16; sr++) { - uint32_t vsid; - asm volatile ( - "mfsrin %0, %1\n" - : "=r" (vsid) - : "r" (sr << 28) - ); + uint32_t vsid = sr_get(sr << 28); + printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr, sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, Index: kernel/arch/sparc64/src/mm/sun4u/as.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4u/as.c (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/sparc64/src/mm/sun4u/as.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -41,4 +41,5 @@ #ifdef CONFIG_TSB + #include #include @@ -47,4 +48,5 @@ #include #include + #endif /* CONFIG_TSB */ @@ -58,5 +60,5 @@ } -int as_constructor_arch(as_t *as, int flags) +int as_constructor_arch(as_t *as, unsigned int flags) { #ifdef CONFIG_TSB @@ -64,20 +66,22 @@ * The order must be calculated with respect to the emulated * 16K page size. - */ - int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * + * + */ + uint8_t order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t)) >> FRAME_WIDTH); - + uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA); - + if (!tsb) return -1; - + as->arch.itsb = (tsb_entry_t *) tsb; as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT * sizeof(tsb_entry_t)); - + memsetb(as->arch.itsb, (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0); #endif + return 0; } @@ -93,4 +97,5 @@ sizeof(tsb_entry_t)) >> FRAME_WIDTH; frame_free(KA2PA((uintptr_t) as->arch.itsb)); + return cnt; #else @@ -99,9 +104,10 @@ } -int as_create_arch(as_t *as, int flags) +int as_create_arch(as_t *as, unsigned int flags) { #ifdef CONFIG_TSB tsb_invalidate(as, 0, (size_t) -1); #endif + return 0; } @@ -123,4 +129,5 @@ * * Moreover, the as->asid is protected by asidlock, which is being held. + * */ @@ -130,16 +137,17 @@ * secondary context register from the TL=1 code just before switch to * userspace. + * */ ctx.v = 0; ctx.context = as->asid; mmu_secondary_context_write(ctx.v); - -#ifdef CONFIG_TSB + +#ifdef CONFIG_TSB uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); - + ASSERT(as->arch.itsb && as->arch.dtsb); - + uintptr_t tsb = (uintptr_t) as->arch.itsb; - + if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { /* @@ -147,18 +155,20 @@ * by the locked 4M kernel DTLB entry. We need * to map both TSBs explicitly. + * */ dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true); } - + /* * Setup TSB Base registers. + * */ tsb_base_reg_t tsb_base; - + tsb_base.value = 0; tsb_base.size = TSB_SIZE; tsb_base.split = 0; - + tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH; itsb_base_write(tsb_base.value); @@ -175,5 +185,6 @@ * Clearing the extension registers will ensure that the value of the * TSB Base register will be used as an address of TSB, making the code - * compatible with the US port. + * compatible with the US port. + * */ itsb_primary_extension_write(0); @@ -195,5 +206,4 @@ void as_deinstall_arch(as_t *as) { - /* * Note that we don't and may not lock the address space. That's ok @@ -201,13 +211,14 @@ * * Moreover, the as->asid is protected by asidlock, which is being held. - */ - + * + */ + #ifdef CONFIG_TSB uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); - + ASSERT(as->arch.itsb && as->arch.dtsb); - + uintptr_t tsb = (uintptr_t) as->arch.itsb; - + if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { /* Index: kernel/arch/sparc64/src/mm/sun4v/as.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4v/as.c (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/sparc64/src/mm/sun4v/as.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -44,4 +44,5 @@ #ifdef CONFIG_TSB + #include #include @@ -50,4 +51,5 @@ #include #include + #endif /* CONFIG_TSB */ @@ -61,15 +63,15 @@ } -int as_constructor_arch(as_t *as, int flags) +int as_constructor_arch(as_t *as, unsigned int flags) { #ifdef CONFIG_TSB - int order = fnzb32( + uint8_t order = fnzb32( (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH); - + uintptr_t tsb = (uintptr_t) frame_alloc(order, flags); - + if (!tsb) return -1; - + as->arch.tsb_description.page_size = PAGESIZE_8K; as->arch.tsb_description.associativity = 1; @@ -79,8 +81,9 @@ as->arch.tsb_description.reserved = 0; as->arch.tsb_description.context = 0; - + memsetb((void *) PA2KA(as->arch.tsb_description.tsb_base), TSB_ENTRY_COUNT * sizeof(tsb_entry_t), 0); #endif + return 0; } @@ -91,4 +94,5 @@ size_t cnt = (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH; frame_free((uintptr_t) as->arch.tsb_description.tsb_base); + return cnt; #else @@ -97,9 +101,10 @@ } -int as_create_arch(as_t *as, int flags) +int as_create_arch(as_t *as, unsigned int flags) { #ifdef CONFIG_TSB tsb_invalidate(as, 0, (size_t) -1); #endif + return 0; } @@ -111,14 +116,16 @@ * * @param as Address space. + * */ void as_install_arch(as_t *as) { mmu_secondary_context_write(as->asid); -#ifdef CONFIG_TSB + +#ifdef CONFIG_TSB uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); - + ASSERT(as->arch.tsb_description.tsb_base); uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base); - + if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { /* @@ -126,11 +133,11 @@ * by the locked 4M kernel DTLB entry. We need * to map both TSBs explicitly. + * */ mmu_demap_page(tsb, 0, MMU_FLAG_DTLB); dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true); } - + __hypercall_fast2(MMU_TSB_CTXNON0, 1, KA2PA(&(as->arch.tsb_description))); - #endif } @@ -142,8 +149,8 @@ * * @param as Address space. + * */ void as_deinstall_arch(as_t *as) { - /* * Note that we don't and may not lock the address space. That's ok @@ -151,13 +158,14 @@ * * Moreover, the as->asid is protected by asidlock, which is being held. + * */ - + #ifdef CONFIG_TSB uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); - + ASSERT(as->arch.tsb_description.tsb_base); - + uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base); - + if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { /* @@ -165,4 +173,5 @@ * by the locked 4M kernel DTLB entry. We need * to demap the entry installed by as_install_arch(). + * */ __hypercall_fast3(MMU_UNMAP_PERM_ADDR, tsb, 0, MMU_FLAG_DTLB); Index: kernel/arch/sparc64/src/trap/sun4u/interrupt.c =================================================================== --- kernel/arch/sparc64/src/trap/sun4u/interrupt.c (revision 666f492f56681952d58041f88d5bbb968548091c) +++ kernel/arch/sparc64/src/trap/sun4u/interrupt.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -55,18 +55,15 @@ void interrupt(int n, istate_t *istate) { - uint64_t status; - uint64_t intrcv; - uint64_t data0; - status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0); + uint64_t status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0); if (status & (!INTR_DISPATCH_STATUS_BUSY)) panic("Interrupt Dispatch Status busy bit not set\n"); - - intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0); + + uint64_t intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0); #if defined (US) - data0 = asi_u64_read(ASI_INTR_R, ASI_UDB_INTR_R_DATA_0); + uint64_t data0 = asi_u64_read(ASI_INTR_R, ASI_UDB_INTR_R_DATA_0); #elif defined (US3) - data0 = asi_u64_read(ASI_INTR_R, VA_INTR_R_DATA_0); + uint64_t data0 = asi_u64_read(ASI_INTR_R, VA_INTR_R_DATA_0); #endif - + irq_t *irq = irq_dispatch_and_lock(data0); if (irq) { @@ -75,11 +72,12 @@ */ irq->handler(irq); + /* * See if there is a clear-interrupt-routine and call it. */ - if (irq->cir) { + if (irq->cir) irq->cir(irq->cir_arg, irq->inr); - } - spinlock_unlock(&irq->lock); + + irq_spinlock_unlock(&irq->lock, false); } else if (data0 > config.base) { /* @@ -90,7 +88,6 @@ */ #ifdef CONFIG_SMP - if (data0 == (uintptr_t) tlb_shootdown_ipi_recv) { + if (data0 == (uintptr_t) tlb_shootdown_ipi_recv) tlb_shootdown_ipi_recv(); - } #endif } else { @@ -101,7 +98,9 @@ printf("cpu%u: spurious interrupt (intrcv=%#" PRIx64 ", data0=%#" PRIx64 ")\n", CPU->id, intrcv, data0); +#else + (void) intrcv; #endif } - + membar(); asi_u64_write(ASI_INTR_RECEIVE, 0, 0);