Index: kernel/arch/sparc64/src/mm/sun4u/as.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4u/as.c (revision ba7371f9d732a62dea4383ffb0e509bccd9f4e4a) +++ kernel/arch/sparc64/src/mm/sun4u/as.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -41,4 +41,5 @@ #ifdef CONFIG_TSB + #include #include @@ -47,4 +48,5 @@ #include #include + #endif /* CONFIG_TSB */ @@ -58,5 +60,5 @@ } -int as_constructor_arch(as_t *as, int flags) +int as_constructor_arch(as_t *as, unsigned int flags) { #ifdef CONFIG_TSB @@ -64,20 +66,22 @@ * The order must be calculated with respect to the emulated * 16K page size. - */ - int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * + * + */ + uint8_t order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t)) >> FRAME_WIDTH); - + uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA); - + if (!tsb) return -1; - + as->arch.itsb = (tsb_entry_t *) tsb; as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT * sizeof(tsb_entry_t)); - + memsetb(as->arch.itsb, (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0); #endif + return 0; } @@ -93,4 +97,5 @@ sizeof(tsb_entry_t)) >> FRAME_WIDTH; frame_free(KA2PA((uintptr_t) as->arch.itsb)); + return cnt; #else @@ -99,9 +104,10 @@ } -int as_create_arch(as_t *as, int flags) +int as_create_arch(as_t *as, unsigned int flags) { #ifdef CONFIG_TSB tsb_invalidate(as, 0, (size_t) -1); #endif + return 0; } @@ -123,4 +129,5 @@ * * Moreover, the as->asid is protected by asidlock, which is being held. + * */ @@ -130,16 +137,17 @@ * secondary context register from the TL=1 code just before switch to * userspace. + * */ ctx.v = 0; ctx.context = as->asid; mmu_secondary_context_write(ctx.v); - -#ifdef CONFIG_TSB + +#ifdef CONFIG_TSB uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); - + ASSERT(as->arch.itsb && as->arch.dtsb); - + uintptr_t tsb = (uintptr_t) as->arch.itsb; - + if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { /* @@ -147,18 +155,20 @@ * by the locked 4M kernel DTLB entry. We need * to map both TSBs explicitly. + * */ dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true); } - + /* * Setup TSB Base registers. + * */ tsb_base_reg_t tsb_base; - + tsb_base.value = 0; tsb_base.size = TSB_SIZE; tsb_base.split = 0; - + tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH; itsb_base_write(tsb_base.value); @@ -175,5 +185,6 @@ * Clearing the extension registers will ensure that the value of the * TSB Base register will be used as an address of TSB, making the code - * compatible with the US port. + * compatible with the US port. + * */ itsb_primary_extension_write(0); @@ -195,5 +206,4 @@ void as_deinstall_arch(as_t *as) { - /* * Note that we don't and may not lock the address space. That's ok @@ -201,13 +211,14 @@ * * Moreover, the as->asid is protected by asidlock, which is being held. - */ - + * + */ + #ifdef CONFIG_TSB uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); - + ASSERT(as->arch.itsb && as->arch.dtsb); - + uintptr_t tsb = (uintptr_t) as->arch.itsb; - + if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { /* Index: kernel/arch/sparc64/src/mm/sun4v/as.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4v/as.c (revision ba7371f9d732a62dea4383ffb0e509bccd9f4e4a) +++ kernel/arch/sparc64/src/mm/sun4v/as.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -44,4 +44,5 @@ #ifdef CONFIG_TSB + #include #include @@ -50,4 +51,5 @@ #include #include + #endif /* CONFIG_TSB */ @@ -61,15 +63,15 @@ } -int as_constructor_arch(as_t *as, int flags) +int as_constructor_arch(as_t *as, unsigned int flags) { #ifdef CONFIG_TSB - int order = fnzb32( + uint8_t order = fnzb32( (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH); - + uintptr_t tsb = (uintptr_t) frame_alloc(order, flags); - + if (!tsb) return -1; - + as->arch.tsb_description.page_size = PAGESIZE_8K; as->arch.tsb_description.associativity = 1; @@ -79,8 +81,9 @@ as->arch.tsb_description.reserved = 0; as->arch.tsb_description.context = 0; - + memsetb((void *) PA2KA(as->arch.tsb_description.tsb_base), TSB_ENTRY_COUNT * sizeof(tsb_entry_t), 0); #endif + return 0; } @@ -91,4 +94,5 @@ size_t cnt = (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH; frame_free((uintptr_t) as->arch.tsb_description.tsb_base); + return cnt; #else @@ -97,9 +101,10 @@ } -int as_create_arch(as_t *as, int flags) +int as_create_arch(as_t *as, unsigned int flags) { #ifdef CONFIG_TSB tsb_invalidate(as, 0, (size_t) -1); #endif + return 0; } @@ -111,14 +116,16 @@ * * @param as Address space. + * */ void as_install_arch(as_t *as) { mmu_secondary_context_write(as->asid); -#ifdef CONFIG_TSB + +#ifdef CONFIG_TSB uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); - + ASSERT(as->arch.tsb_description.tsb_base); uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base); - + if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { /* @@ -126,11 +133,11 @@ * by the locked 4M kernel DTLB entry. We need * to map both TSBs explicitly. + * */ mmu_demap_page(tsb, 0, MMU_FLAG_DTLB); dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true); } - + __hypercall_fast2(MMU_TSB_CTXNON0, 1, KA2PA(&(as->arch.tsb_description))); - #endif } @@ -142,8 +149,8 @@ * * @param as Address space. + * */ void as_deinstall_arch(as_t *as) { - /* * Note that we don't and may not lock the address space. That's ok @@ -151,13 +158,14 @@ * * Moreover, the as->asid is protected by asidlock, which is being held. + * */ - + #ifdef CONFIG_TSB uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); - + ASSERT(as->arch.tsb_description.tsb_base); - + uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base); - + if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { /* @@ -165,4 +173,5 @@ * by the locked 4M kernel DTLB entry. We need * to demap the entry installed by as_install_arch(). + * */ __hypercall_fast3(MMU_UNMAP_PERM_ADDR, tsb, 0, MMU_FLAG_DTLB); Index: kernel/arch/sparc64/src/trap/sun4u/interrupt.c =================================================================== --- kernel/arch/sparc64/src/trap/sun4u/interrupt.c (revision ba7371f9d732a62dea4383ffb0e509bccd9f4e4a) +++ kernel/arch/sparc64/src/trap/sun4u/interrupt.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -55,18 +55,15 @@ void interrupt(int n, istate_t *istate) { - uint64_t status; - uint64_t intrcv; - uint64_t data0; - status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0); + uint64_t status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0); if (status & (!INTR_DISPATCH_STATUS_BUSY)) panic("Interrupt Dispatch Status busy bit not set\n"); - - intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0); + + uint64_t intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0); #if defined (US) - data0 = asi_u64_read(ASI_INTR_R, ASI_UDB_INTR_R_DATA_0); + uint64_t data0 = asi_u64_read(ASI_INTR_R, ASI_UDB_INTR_R_DATA_0); #elif defined (US3) - data0 = asi_u64_read(ASI_INTR_R, VA_INTR_R_DATA_0); + uint64_t data0 = asi_u64_read(ASI_INTR_R, VA_INTR_R_DATA_0); #endif - + irq_t *irq = irq_dispatch_and_lock(data0); if (irq) { @@ -75,11 +72,12 @@ */ irq->handler(irq); + /* * See if there is a clear-interrupt-routine and call it. */ - if (irq->cir) { + if (irq->cir) irq->cir(irq->cir_arg, irq->inr); - } - spinlock_unlock(&irq->lock); + + irq_spinlock_unlock(&irq->lock, false); } else if (data0 > config.base) { /* @@ -90,7 +88,6 @@ */ #ifdef CONFIG_SMP - if (data0 == (uintptr_t) tlb_shootdown_ipi_recv) { + if (data0 == (uintptr_t) tlb_shootdown_ipi_recv) tlb_shootdown_ipi_recv(); - } #endif } else { @@ -101,7 +98,9 @@ printf("cpu%u: spurious interrupt (intrcv=%#" PRIx64 ", data0=%#" PRIx64 ")\n", CPU->id, intrcv, data0); +#else + (void) intrcv; #endif } - + membar(); asi_u64_write(ASI_INTR_RECEIVE, 0, 0);