Index: kernel/arch/ia32/include/smp/apic.h =================================================================== --- kernel/arch/ia32/include/smp/apic.h (revision b8230b99f42baed609487cfaa5737fbb11968cc0) +++ kernel/arch/ia32/include/smp/apic.h (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -27,5 +27,5 @@ */ -/** @addtogroup ia32 +/** @addtogroup ia32 * @{ */ @@ -39,87 +39,88 @@ #include -#define FIXED (0<<0) -#define LOPRI (1<<0) - -#define APIC_ID_COUNT 16 +#define FIXED (0 << 0) +#define LOPRI (1 << 0) + +#define APIC_ID_COUNT 16 /* local APIC macros */ -#define IPI_INIT 0 -#define IPI_STARTUP 0 +#define IPI_INIT 0 +#define IPI_STARTUP 0 /** Delivery modes. */ -#define DELMOD_FIXED 0x0 -#define DELMOD_LOWPRI 0x1 -#define DELMOD_SMI 0x2 +#define DELMOD_FIXED 0x0 +#define DELMOD_LOWPRI 0x1 +#define DELMOD_SMI 0x2 /* 0x3 reserved */ -#define DELMOD_NMI 0x4 -#define DELMOD_INIT 0x5 -#define DELMOD_STARTUP 0x6 -#define DELMOD_EXTINT 0x7 +#define DELMOD_NMI 0x4 +#define DELMOD_INIT 0x5 +#define DELMOD_STARTUP 0x6 +#define DELMOD_EXTINT 0x7 /** Destination modes. */ -#define DESTMOD_PHYS 0x0 -#define DESTMOD_LOGIC 0x1 +#define DESTMOD_PHYS 0x0 +#define DESTMOD_LOGIC 0x1 /** Trigger Modes. */ -#define TRIGMOD_EDGE 0x0 -#define TRIGMOD_LEVEL 0x1 +#define TRIGMOD_EDGE 0x0 +#define TRIGMOD_LEVEL 0x1 /** Levels. */ -#define LEVEL_DEASSERT 0x0 -#define LEVEL_ASSERT 0x1 +#define LEVEL_DEASSERT 0x0 +#define LEVEL_ASSERT 0x1 /** Destination Shorthands. */ -#define SHORTHAND_NONE 0x0 -#define SHORTHAND_SELF 0x1 -#define SHORTHAND_ALL_INCL 0x2 -#define SHORTHAND_ALL_EXCL 0x3 +#define SHORTHAND_NONE 0x0 +#define SHORTHAND_SELF 0x1 +#define SHORTHAND_ALL_INCL 0x2 +#define SHORTHAND_ALL_EXCL 0x3 /** Interrupt Input Pin Polarities. */ -#define POLARITY_HIGH 0x0 -#define POLARITY_LOW 0x1 +#define POLARITY_HIGH 0x0 +#define POLARITY_LOW 0x1 /** Divide Values. (Bit 2 is always 0) */ -#define DIVIDE_2 0x0 -#define DIVIDE_4 0x1 -#define DIVIDE_8 0x2 -#define DIVIDE_16 0x3 -#define DIVIDE_32 0x8 -#define DIVIDE_64 0x9 -#define DIVIDE_128 0xa -#define DIVIDE_1 0xb +#define DIVIDE_2 0x0 +#define DIVIDE_4 0x1 +#define DIVIDE_8 0x2 +#define DIVIDE_16 0x3 +#define DIVIDE_32 0x8 +#define DIVIDE_64 0x9 +#define DIVIDE_128 0xa +#define DIVIDE_1 0xb /** Timer Modes. */ -#define TIMER_ONESHOT 0x0 -#define TIMER_PERIODIC 0x1 +#define TIMER_ONESHOT 0x0 +#define TIMER_PERIODIC 0x1 /** Delivery status. */ -#define DELIVS_IDLE 0x0 -#define DELIVS_PENDING 0x1 +#define DELIVS_IDLE 0x0 +#define DELIVS_PENDING 0x1 /** Destination masks. */ -#define DEST_ALL 0xff +#define DEST_ALL 0xff /** Dest format models. */ -#define MODEL_FLAT 0xf -#define MODEL_CLUSTER 0x0 +#define MODEL_FLAT 0xf +#define MODEL_CLUSTER 0x0 /** Interrupt Command Register. */ -#define ICRlo (0x300 / sizeof(uint32_t)) -#define ICRhi (0x310 / sizeof(uint32_t)) +#define ICRlo (0x300 / sizeof(uint32_t)) +#define ICRhi (0x310 / sizeof(uint32_t)) + typedef struct { union { uint32_t lo; struct { - uint8_t vector; /**< Interrupt Vector. */ - unsigned delmod : 3; /**< Delivery Mode. */ - unsigned destmod : 1; /**< Destination Mode. */ - unsigned delivs : 1; /**< Delivery status (RO). */ - unsigned : 1; /**< Reserved. */ - unsigned level : 1; /**< Level. */ - unsigned trigger_mode : 1; /**< Trigger Mode. */ - unsigned : 2; /**< Reserved. */ - unsigned shorthand : 2; /**< Destination Shorthand. */ - unsigned : 12; /**< Reserved. */ + uint8_t vector; /**< Interrupt Vector. */ + unsigned int delmod : 3; /**< Delivery Mode. */ + unsigned int destmod : 1; /**< Destination Mode. */ + unsigned int delivs : 1; /**< Delivery status (RO). */ + unsigned int : 1; /**< Reserved. */ + unsigned int level : 1; /**< Level. */ + unsigned int trigger_mode : 1; /**< Trigger Mode. */ + unsigned int : 2; /**< Reserved. */ + unsigned int shorthand : 2; /**< Destination Shorthand. */ + unsigned int : 12; /**< Reserved. */ } __attribute__ ((packed)); }; @@ -127,6 +128,6 @@ uint32_t hi; struct { - unsigned : 24; /**< Reserved. */ - uint8_t dest; /**< Destination field. */ + unsigned int : 24; /**< Reserved. */ + uint8_t dest; /**< Destination field. */ } __attribute__ ((packed)); }; @@ -134,154 +135,165 @@ /* End Of Interrupt. */ -#define EOI (0x0b0 / sizeof(uint32_t)) +#define EOI (0x0b0 / sizeof(uint32_t)) /** Error Status Register. */ -#define ESR (0x280 / sizeof(uint32_t)) +#define ESR (0x280 / sizeof(uint32_t)) + typedef union { uint32_t value; uint8_t err_bitmap; struct { - unsigned send_checksum_error : 1; - unsigned receive_checksum_error : 1; - unsigned send_accept_error : 1; - unsigned receive_accept_error : 1; - unsigned : 1; - unsigned send_illegal_vector : 1; - unsigned received_illegal_vector : 1; - unsigned illegal_register_address : 1; - unsigned : 24; + unsigned int send_checksum_error : 1; + unsigned int receive_checksum_error : 1; + unsigned int send_accept_error : 1; + unsigned int receive_accept_error : 1; + unsigned int : 1; + unsigned int send_illegal_vector : 1; + unsigned int received_illegal_vector : 1; + unsigned int illegal_register_address : 1; + unsigned int : 24; } __attribute__ ((packed)); } esr_t; /* Task Priority Register */ -#define TPR (0x080 / sizeof(uint32_t)) -typedef union { - uint32_t value; - struct { - unsigned pri_sc : 4; /**< Task Priority Sub-Class. */ - unsigned pri : 4; /**< Task Priority. */ +#define TPR (0x080 / sizeof(uint32_t)) + +typedef union { + uint32_t value; + struct { + unsigned int pri_sc : 4; /**< Task Priority Sub-Class. */ + unsigned int pri : 4; /**< Task Priority. */ } __attribute__ ((packed)); } tpr_t; /** Spurious-Interrupt Vector Register. */ -#define SVR (0x0f0 / sizeof(uint32_t)) -typedef union { - uint32_t value; - struct { - uint8_t vector; /**< Spurious Vector. */ - unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable. */ - unsigned focus_checking : 1; /**< Focus Processor Checking. */ - unsigned : 22; /**< Reserved. */ +#define SVR (0x0f0 / sizeof(uint32_t)) + +typedef union { + uint32_t value; + struct { + uint8_t vector; /**< Spurious Vector. */ + unsigned int lapic_enabled : 1; /**< APIC Software Enable/Disable. */ + unsigned int focus_checking : 1; /**< Focus Processor Checking. */ + unsigned int : 22; /**< Reserved. */ } __attribute__ ((packed)); } svr_t; /** Time Divide Configuration Register. */ -#define TDCR (0x3e0 / sizeof(uint32_t)) -typedef union { - uint32_t value; - struct { - unsigned div_value : 4; /**< Divide Value, bit 2 is always 0. */ - unsigned : 28; /**< Reserved. */ +#define TDCR (0x3e0 / sizeof(uint32_t)) + +typedef union { + uint32_t value; + struct { + unsigned int div_value : 4; /**< Divide Value, bit 2 is always 0. */ + unsigned int : 28; /**< Reserved. */ } __attribute__ ((packed)); } tdcr_t; /* Initial Count Register for Timer */ -#define ICRT (0x380 / sizeof(uint32_t)) +#define ICRT (0x380 / sizeof(uint32_t)) /* Current Count Register for Timer */ -#define CCRT (0x390 / sizeof(uint32_t)) +#define CCRT (0x390 / sizeof(uint32_t)) /** LVT Timer register. */ -#define LVT_Tm (0x320 / sizeof(uint32_t)) -typedef union { - uint32_t value; - struct { - uint8_t vector; /**< Local Timer Interrupt vector. */ - unsigned : 4; /**< Reserved. */ - unsigned delivs : 1; /**< Delivery status (RO). */ - unsigned : 3; /**< Reserved. */ - unsigned masked : 1; /**< Interrupt Mask. */ - unsigned mode : 1; /**< Timer Mode. */ - unsigned : 14; /**< Reserved. */ +#define LVT_Tm (0x320 / sizeof(uint32_t)) + +typedef union { + uint32_t value; + struct { + uint8_t vector; /**< Local Timer Interrupt vector. */ + unsigned int : 4; /**< Reserved. */ + unsigned int delivs : 1; /**< Delivery status (RO). */ + unsigned int : 3; /**< Reserved. */ + unsigned int masked : 1; /**< Interrupt Mask. */ + unsigned int mode : 1; /**< Timer Mode. */ + unsigned int : 14; /**< Reserved. */ } __attribute__ ((packed)); } lvt_tm_t; /** LVT LINT registers. */ -#define LVT_LINT0 (0x350 / sizeof(uint32_t)) -#define LVT_LINT1 (0x360 / sizeof(uint32_t)) -typedef union { - uint32_t value; - struct { - uint8_t vector; /**< LINT Interrupt vector. */ - unsigned delmod : 3; /**< Delivery Mode. */ - unsigned : 1; /**< Reserved. */ - unsigned delivs : 1; /**< Delivery status (RO). */ - unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ - unsigned irr : 1; /**< Remote IRR (RO). */ - unsigned trigger_mode : 1; /**< Trigger Mode. */ - unsigned masked : 1; /**< Interrupt Mask. */ - unsigned : 15; /**< Reserved. */ +#define LVT_LINT0 (0x350 / sizeof(uint32_t)) +#define LVT_LINT1 (0x360 / sizeof(uint32_t)) + +typedef union { + uint32_t value; + struct { + uint8_t vector; /**< LINT Interrupt vector. */ + unsigned int delmod : 3; /**< Delivery Mode. */ + unsigned int : 1; /**< Reserved. */ + unsigned int delivs : 1; /**< Delivery status (RO). */ + unsigned int intpol : 1; /**< Interrupt Input Pin Polarity. */ + unsigned int irr : 1; /**< Remote IRR (RO). */ + unsigned int trigger_mode : 1; /**< Trigger Mode. */ + unsigned int masked : 1; /**< Interrupt Mask. */ + unsigned int : 15; /**< Reserved. */ } __attribute__ ((packed)); } lvt_lint_t; /** LVT Error register. */ -#define LVT_Err (0x370 / sizeof(uint32_t)) -typedef union { - uint32_t value; - struct { - uint8_t vector; /**< Local Timer Interrupt vector. */ - unsigned : 4; /**< Reserved. */ - unsigned delivs : 1; /**< Delivery status (RO). */ - unsigned : 3; /**< Reserved. */ - unsigned masked : 1; /**< Interrupt Mask. */ - unsigned : 15; /**< Reserved. */ +#define LVT_Err (0x370 / sizeof(uint32_t)) + +typedef union { + uint32_t value; + struct { + uint8_t vector; /**< Local Timer Interrupt vector. */ + unsigned int : 4; /**< Reserved. */ + unsigned int delivs : 1; /**< Delivery status (RO). */ + unsigned int : 3; /**< Reserved. */ + unsigned int masked : 1; /**< Interrupt Mask. */ + unsigned int : 15; /**< Reserved. */ } __attribute__ ((packed)); } lvt_error_t; /** Local APIC ID Register. */ -#define L_APIC_ID (0x020 / sizeof(uint32_t)) -typedef union { - uint32_t value; - struct { - unsigned : 24; /**< Reserved. */ - uint8_t apic_id; /**< Local APIC ID. */ +#define L_APIC_ID (0x020 / sizeof(uint32_t)) + +typedef union { + uint32_t value; + struct { + unsigned int : 24; /**< Reserved. */ + uint8_t apic_id; /**< Local APIC ID. */ } __attribute__ ((packed)); } l_apic_id_t; /** Local APIC Version Register */ -#define LAVR (0x030 / sizeof(uint32_t)) -#define LAVR_Mask 0xff -#define is_local_apic(x) (((x) & LAVR_Mask & 0xf0) == 0x1) -#define is_82489DX_apic(x) ((((x) & LAVR_Mask & 0xf0) == 0x0)) -#define is_local_xapic(x) (((x) & LAVR_Mask) == 0x14) +#define LAVR (0x030 / sizeof(uint32_t)) +#define LAVR_Mask 0xff + +#define is_local_apic(x) (((x) & LAVR_Mask & 0xf0) == 0x1) +#define is_82489DX_apic(x) ((((x) & LAVR_Mask & 0xf0) == 0x0)) +#define is_local_xapic(x) (((x) & LAVR_Mask) == 0x14) /** Logical Destination Register. */ -#define LDR (0x0d0 / sizeof(uint32_t)) -typedef union { - uint32_t value; - struct { - unsigned : 24; /**< Reserved. */ - uint8_t id; /**< Logical APIC ID. */ +#define LDR (0x0d0 / sizeof(uint32_t)) + +typedef union { + uint32_t value; + struct { + unsigned int : 24; /**< Reserved. */ + uint8_t id; /**< Logical APIC ID. */ } __attribute__ ((packed)); } ldr_t; /** Destination Format Register. */ -#define DFR (0x0e0 / sizeof(uint32_t)) -typedef union { - uint32_t value; - struct { - unsigned : 28; /**< Reserved, all ones. */ - unsigned model : 4; /**< Model. */ +#define DFR (0x0e0 / sizeof(uint32_t)) + +typedef union { + uint32_t value; + struct { + unsigned int : 28; /**< Reserved, all ones. */ + unsigned int model : 4; /**< Model. */ } __attribute__ ((packed)); } dfr_t; /* IO APIC */ -#define IOREGSEL (0x00 / sizeof(uint32_t)) -#define IOWIN (0x10 / sizeof(uint32_t)) - -#define IOAPICID 0x00 -#define IOAPICVER 0x01 -#define IOAPICARB 0x02 -#define IOREDTBL 0x10 +#define IOREGSEL (0x00 / sizeof(uint32_t)) +#define IOWIN (0x10 / sizeof(uint32_t)) + +#define IOAPICID 0x00 +#define IOAPICVER 0x01 +#define IOAPICARB 0x02 +#define IOREDTBL 0x10 /** I/O Register Select Register. */ @@ -289,6 +301,6 @@ uint32_t value; struct { - uint8_t reg_addr; /**< APIC Register Address. */ - unsigned : 24; /**< Reserved. */ + uint8_t reg_addr; /**< APIC Register Address. */ + unsigned int : 24; /**< Reserved. */ } __attribute__ ((packed)); } io_regsel_t; @@ -299,13 +311,13 @@ uint32_t lo; struct { - uint8_t intvec; /**< Interrupt Vector. */ - unsigned delmod : 3; /**< Delivery Mode. */ - unsigned destmod : 1; /**< Destination mode. */ - unsigned delivs : 1; /**< Delivery status (RO). */ - unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ - unsigned irr : 1; /**< Remote IRR (RO). */ - unsigned trigger_mode : 1; /**< Trigger Mode. */ - unsigned masked : 1; /**< Interrupt Mask. */ - unsigned : 15; /**< Reserved. */ + uint8_t intvec; /**< Interrupt Vector. */ + unsigned int delmod : 3; /**< Delivery Mode. */ + unsigned int destmod : 1; /**< Destination mode. */ + unsigned int delivs : 1; /**< Delivery status (RO). */ + unsigned int intpol : 1; /**< Interrupt Input Pin Polarity. */ + unsigned int irr : 1; /**< Remote IRR (RO). */ + unsigned int trigger_mode : 1; /**< Trigger Mode. */ + unsigned int masked : 1; /**< Interrupt Mask. */ + unsigned int : 15; /**< Reserved. */ } __attribute__ ((packed)); }; @@ -313,6 +325,6 @@ uint32_t hi; struct { - unsigned : 24; /**< Reserved. */ - uint8_t dest : 8; /**< Destination Field. */ + unsigned int : 24; /**< Reserved. */ + uint8_t dest : 8; /**< Destination Field. */ } __attribute__ ((packed)); }; @@ -325,7 +337,7 @@ uint32_t value; struct { - unsigned : 24; /**< Reserved. */ - unsigned apic_id : 4; /**< IO APIC ID. */ - unsigned : 4; /**< Reserved. */ + unsigned int : 24; /**< Reserved. */ + unsigned int apic_id : 4; /**< IO APIC ID. */ + unsigned int : 4; /**< Reserved. */ } __attribute__ ((packed)); } io_apic_id_t; @@ -340,14 +352,14 @@ extern void l_apic_init(void); extern void l_apic_eoi(void); -extern int l_apic_broadcast_custom_ipi(uint8_t vector); -extern int l_apic_send_init_ipi(uint8_t apicid); +extern int l_apic_broadcast_custom_ipi(uint8_t); +extern int l_apic_send_init_ipi(uint8_t); extern void l_apic_debug(void); extern uint8_t l_apic_id(void); -extern uint32_t io_apic_read(uint8_t address); -extern void io_apic_write(uint8_t address , uint32_t x); -extern void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t v, int flags); -extern void io_apic_disable_irqs(uint16_t irqmask); -extern void io_apic_enable_irqs(uint16_t irqmask); +extern uint32_t io_apic_read(uint8_t); +extern void io_apic_write(uint8_t, uint32_t); +extern void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t v, unsigned int); +extern void io_apic_disable_irqs(uint16_t); +extern void io_apic_enable_irqs(uint16_t); #endif Index: kernel/arch/ia32/src/ddi/ddi.c =================================================================== --- kernel/arch/ia32/src/ddi/ddi.c (revision b8230b99f42baed609487cfaa5737fbb11968cc0) +++ kernel/arch/ia32/src/ddi/ddi.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -50,34 +50,31 @@ * Interrupts are disabled and task is locked. * - * @param task Task. + * @param task Task. * @param ioaddr Startign I/O space address. - * @param size Size of the enabled I/O range. + * @param size Size of the enabled I/O range. * * @return 0 on success or an error code from errno.h. + * */ int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size) { - size_t bits; - - bits = ioaddr + size; + size_t bits = ioaddr + size; if (bits > IO_PORTS) return ENOENT; - + if (task->arch.iomap.bits < bits) { - bitmap_t oldiomap; - uint8_t *newmap; - /* * The I/O permission bitmap is too small and needs to be grown. */ - newmap = (uint8_t *) malloc(BITS2BYTES(bits), FRAME_ATOMIC); + uint8_t *newmap = (uint8_t *) malloc(BITS2BYTES(bits), FRAME_ATOMIC); if (!newmap) return ENOMEM; + bitmap_t oldiomap; bitmap_initialize(&oldiomap, task->arch.iomap.map, task->arch.iomap.bits); bitmap_initialize(&task->arch.iomap, newmap, bits); - + /* * Mark the new range inaccessible. @@ -85,9 +82,9 @@ bitmap_set_range(&task->arch.iomap, oldiomap.bits, bits - oldiomap.bits); - + /* * In case there really existed smaller iomap, * copy its contents and deallocate it. - */ + */ if (oldiomap.bits) { bitmap_copy(&task->arch.iomap, &oldiomap, @@ -96,15 +93,15 @@ } } - + /* * Enable the range and we are done. */ bitmap_clear_range(&task->arch.iomap, (size_t) ioaddr, (size_t) size); - + /* * Increment I/O Permission bitmap generation counter. */ task->arch.iomapver++; - + return 0; } @@ -116,23 +113,20 @@ * * Interrupts must be disabled prior this call. + * */ void io_perm_bitmap_install(void) { - size_t bits; - ptr_16_32_t cpugdtr; - descriptor_t *gdt_p; - size_t ver; - /* First, copy the I/O Permission Bitmap. */ - spinlock_lock(&TASK->lock); - ver = TASK->arch.iomapver; - if ((bits = TASK->arch.iomap.bits)) { + irq_spinlock_lock(&TASK->lock, false); + size_t ver = TASK->arch.iomapver; + size_t bits = TASK->arch.iomap.bits; + if (bits) { + ASSERT(TASK->arch.iomap.map); + bitmap_t iomap; - task_t *task = TASK; - - ASSERT(TASK->arch.iomap.map); bitmap_initialize(&iomap, CPU->arch.tss->iomap, TSS_IOMAP_SIZE * 8); - bitmap_copy(&iomap, &task->arch.iomap, task->arch.iomap.bits); + bitmap_copy(&iomap, &TASK->arch.iomap, TASK->arch.iomap.bits); + /* * It is safe to set the trailing eight bits because of the @@ -141,15 +135,17 @@ bitmap_set_range(&iomap, ALIGN_UP(TASK->arch.iomap.bits, 8), 8); } - spinlock_unlock(&TASK->lock); - + irq_spinlock_unlock(&TASK->lock, false); + /* * Second, adjust TSS segment limit. * Take the extra ending byte with all bits set into account. */ + ptr_16_32_t cpugdtr; gdtr_store(&cpugdtr); - gdt_p = (descriptor_t *) cpugdtr.base; + + descriptor_t *gdt_p = (descriptor_t *) cpugdtr.base; gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + BITS2BYTES(bits)); gdtr_load(&cpugdtr); - + /* * Before we load new TSS limit, the current TSS descriptor Index: kernel/arch/ia32/src/drivers/i8254.c =================================================================== --- kernel/arch/ia32/src/drivers/i8254.c (revision b8230b99f42baed609487cfaa5737fbb11968cc0) +++ kernel/arch/ia32/src/drivers/i8254.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -54,9 +54,12 @@ #include -#define CLK_PORT1 ((ioport8_t *)0x40) -#define CLK_PORT4 ((ioport8_t *)0x43) +#define CLK_PORT1 ((ioport8_t *) 0x40) +#define CLK_PORT4 ((ioport8_t *) 0x43) -#define CLK_CONST 1193180 -#define MAGIC_NUMBER 1194 +#define CLK_CONST 1193180 +#define MAGIC_NUMBER 1194 + +#define LOOPS 150000 +#define SHIFT 11 static irq_t i8254_irq; @@ -75,7 +78,7 @@ * lock. We just release it, call clock() and then reacquire it again. */ - spinlock_unlock(&irq->lock); + irq_spinlock_unlock(&irq->lock, false); clock(); - spinlock_lock(&irq->lock); + irq_spinlock_lock(&irq->lock, false); } @@ -102,13 +105,6 @@ } -#define LOOPS 150000 -#define SHIFT 11 void i8254_calibrate_delay_loop(void) { - uint64_t clk1, clk2; - uint32_t t1, t2, o1, o2; - uint8_t not_ok; - - /* * One-shot timer. Count-down from 0xffff at 1193180Hz @@ -118,5 +114,9 @@ pio_write_8(CLK_PORT1, 0xff); pio_write_8(CLK_PORT1, 0xff); - + + uint8_t not_ok; + uint32_t t1; + uint32_t t2; + do { /* will read both status and count */ @@ -126,34 +126,34 @@ t1 |= pio_read_8(CLK_PORT1) << 8; } while (not_ok); - + asm_delay_loop(LOOPS); - + pio_write_8(CLK_PORT4, 0xd2); t2 = pio_read_8(CLK_PORT1); t2 |= pio_read_8(CLK_PORT1) << 8; - + /* * We want to determine the overhead of the calibrating mechanism. */ pio_write_8(CLK_PORT4, 0xd2); - o1 = pio_read_8(CLK_PORT1); + uint32_t o1 = pio_read_8(CLK_PORT1); o1 |= pio_read_8(CLK_PORT1) << 8; - + asm_fake_loop(LOOPS); - + pio_write_8(CLK_PORT4, 0xd2); - o2 = pio_read_8(CLK_PORT1); + uint32_t o2 = pio_read_8(CLK_PORT1); o2 |= pio_read_8(CLK_PORT1) << 8; - + CPU->delay_loop_const = ((MAGIC_NUMBER * LOOPS) / 1000) / ((t1 - t2) - (o1 - o2)) + (((MAGIC_NUMBER * LOOPS) / 1000) % ((t1 - t2) - (o1 - o2)) ? 1 : 0); - - clk1 = get_cycle(); + + uint64_t clk1 = get_cycle(); delay(1 << SHIFT); - clk2 = get_cycle(); + uint64_t clk2 = get_cycle(); CPU->frequency_mhz = (clk2 - clk1) >> SHIFT; - + return; } Index: kernel/arch/ia32/src/interrupt.c =================================================================== --- kernel/arch/ia32/src/interrupt.c (revision b8230b99f42baed609487cfaa5737fbb11968cc0) +++ kernel/arch/ia32/src/interrupt.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -94,5 +94,5 @@ { fault_if_from_uspace(istate, "Unserviced interrupt: %d.", n); - + decode_istate(istate); panic("Unserviced interrupt: %d.", n); @@ -102,5 +102,5 @@ { fault_if_from_uspace(istate, "Divide error."); - + decode_istate(istate); panic("Divide error."); @@ -111,10 +111,8 @@ { if (TASK) { - size_t ver; + irq_spinlock_lock(&TASK->lock, false); + size_t ver = TASK->arch.iomapver; + irq_spinlock_unlock(&TASK->lock, false); - spinlock_lock(&TASK->lock); - ver = TASK->arch.iomapver; - spinlock_unlock(&TASK->lock); - if (CPU->arch.iomapver_copy != ver) { /* @@ -130,5 +128,5 @@ fault_if_from_uspace(istate, "General protection fault."); } - + decode_istate(istate); panic("General protection fault."); @@ -138,5 +136,5 @@ { fault_if_from_uspace(istate, "Stack fault."); - + decode_istate(istate); panic("Stack fault."); @@ -146,8 +144,9 @@ { uint32_t mxcsr; - asm ( + asm volatile ( "stmxcsr %[mxcsr]\n" : [mxcsr] "=m" (mxcsr) ); + fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR: %#zx.", (unative_t) mxcsr); @@ -158,7 +157,8 @@ } -static void nm_fault(int n __attribute__((unused)), istate_t *istate __attribute__((unused))) -{ -#ifdef CONFIG_FPU_LAZY +static void nm_fault(int n __attribute__((unused)), + istate_t *istate __attribute__((unused))) +{ +#ifdef CONFIG_FPU_LAZY scheduler_fpu_lazy_request(); #else @@ -169,5 +169,6 @@ #ifdef CONFIG_SMP -static void tlb_shootdown_ipi(int n __attribute__((unused)), istate_t *istate __attribute__((unused))) +static void tlb_shootdown_ipi(int n __attribute__((unused)), + istate_t *istate __attribute__((unused))) { trap_virtual_eoi(); @@ -191,5 +192,5 @@ * The IRQ handler was found. */ - + if (irq->preack) { /* Send EOI before processing the interrupt */ @@ -198,5 +199,5 @@ } irq->handler(irq); - spinlock_unlock(&irq->lock); + irq_spinlock_unlock(&irq->lock, false); } else { /* Index: kernel/arch/ia32/src/smp/apic.c =================================================================== --- kernel/arch/ia32/src/smp/apic.c (revision b8230b99f42baed609487cfaa5737fbb11968cc0) +++ kernel/arch/ia32/src/smp/apic.c (revision da1bafb8cf9a3b3be8ef21bc114daaa476a85190) @@ -53,11 +53,12 @@ * Advanced Programmable Interrupt Controller for SMP systems. * Tested on: - * Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs - * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs - * VMware Workstation 5.5 with 2 CPUs - * QEMU 0.8.0 with 2-15 CPUs - * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs - * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs - * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs + * Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs + * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs + * VMware Workstation 5.5 with 2 CPUs + * QEMU 0.8.0 with 2-15 CPUs + * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs + * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs + * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs + * */ @@ -69,4 +70,5 @@ * optimize the code too much and accesses to l_apic and io_apic, that must * always be 32-bit, would use byte oriented instructions. + * */ volatile uint32_t *l_apic = (uint32_t *) 0xfee00000; @@ -79,5 +81,5 @@ #ifdef LAPIC_VERBOSE -static char *delmod_str[] = { +static const char *delmod_str[] = { "Fixed", "Lowest Priority", @@ -90,30 +92,30 @@ }; -static char *destmod_str[] = { +static const char *destmod_str[] = { "Physical", "Logical" }; -static char *trigmod_str[] = { +static const char *trigmod_str[] = { "Edge", "Level" }; -static char *mask_str[] = { +static const char *mask_str[] = { "Unmasked", "Masked" }; -static char *delivs_str[] = { +static const char *delivs_str[] = { "Idle", "Send Pending" }; -static char *tm_mode_str[] = { +static const char *tm_mode_str[] = { "One-shot", "Periodic" }; -static char *intpol_str[] = { +static const char *intpol_str[] = { "Polarity High", "Polarity Low" @@ -123,8 +125,10 @@ /** APIC spurious interrupt handler. * - * @param n Interrupt vector. + * @param n Interrupt vector. * @param istate Interrupted state. - */ -static void apic_spurious(int n __attribute__((unused)), istate_t *istate __attribute__((unused))) + * + */ +static void apic_spurious(int n __attribute__((unused)), + istate_t *istate __attribute__((unused))) { #ifdef CONFIG_DEBUG @@ -145,7 +149,7 @@ * irq->lock so we just unlock it and then lock it again. */ - spinlock_unlock(&irq->lock); + irq_spinlock_unlock(&irq->lock, false); clock(); - spinlock_lock(&irq->lock); + irq_spinlock_lock(&irq->lock, false); } @@ -153,8 +157,6 @@ void apic_init(void) { - io_apic_id_t idreg; - exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious); - + enable_irqs_function = io_apic_enable_irqs; disable_irqs_function = io_apic_disable_irqs; @@ -179,5 +181,5 @@ for (i = 0; i < IRQ_COUNT; i++) { int pin; - + if ((pin = smp_irq_to_pin(i)) != -1) io_apic_change_ioredtbl((uint8_t) pin, DEST_ALL, (uint8_t) (IVT_IRQBASE + i), LOPRI); @@ -187,6 +189,8 @@ * Ensure that io_apic has unique ID. */ + io_apic_id_t idreg; + idreg.value = io_apic_read(IOAPICID); - if ((1 << idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ + if ((1 << idreg.apic_id) & apic_id_mask) { /* See if IO APIC ID is used already */ for (i = 0; i < APIC_ID_COUNT; i++) { if (!((1 << i) & apic_id_mask)) { @@ -197,11 +201,10 @@ } } - + /* * Configure the BSP's lapic. */ l_apic_init(); - - l_apic_debug(); + l_apic_debug(); } @@ -211,4 +214,5 @@ * * @return 0 on error, 1 on success. + * */ int apic_poll_errors(void) @@ -232,5 +236,5 @@ if (esr.illegal_register_address) printf("Illegal Register Address\n"); - + return !esr.err_bitmap; } @@ -241,9 +245,10 @@ * * @return 0 on failure, 1 on success. + * */ int l_apic_broadcast_custom_ipi(uint8_t vector) { icr_t icr; - + icr.lo = l_apic[ICRlo]; icr.delmod = DELMOD_FIXED; @@ -253,7 +258,7 @@ icr.trigger_mode = TRIGMOD_LEVEL; icr.vector = vector; - + l_apic[ICRlo] = icr.lo; - + icr.lo = l_apic[ICRlo]; if (icr.delivs == DELIVS_PENDING) { @@ -262,5 +267,5 @@ #endif } - + return apic_poll_errors(); } @@ -271,13 +276,13 @@ * * @return 0 on failure, 1 on success. + * */ int l_apic_send_init_ipi(uint8_t apicid) { + /* + * Read the ICR register in and zero all non-reserved fields. + */ icr_t icr; - int i; - - /* - * Read the ICR register in and zero all non-reserved fields. - */ + icr.lo = l_apic[ICRlo]; icr.hi = l_apic[ICRhi]; @@ -293,5 +298,5 @@ l_apic[ICRhi] = icr.hi; l_apic[ICRlo] = icr.lo; - + /* * According to MP Specification, 20us should be enough to @@ -299,8 +304,8 @@ */ delay(20); - + if (!apic_poll_errors()) return 0; - + icr.lo = l_apic[ICRlo]; if (icr.delivs == DELIVS_PENDING) { @@ -309,5 +314,5 @@ #endif } - + icr.delmod = DELMOD_INIT; icr.destmod = DESTMOD_PHYS; @@ -317,15 +322,16 @@ icr.vector = 0; l_apic[ICRlo] = icr.lo; - + /* * Wait 10ms as MP Specification specifies. */ delay(10000); - + if (!is_82489DX_apic(l_apic[LAVR])) { /* * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. */ - for (i = 0; i<2; i++) { + unsigned int i; + for (i = 0; i < 2; i++) { icr.lo = l_apic[ICRlo]; icr.vector = (uint8_t) (((uintptr_t) ap_boot) >> 12); /* calculate the reset vector */ @@ -346,31 +352,26 @@ void l_apic_init(void) { + /* Initialize LVT Error register. */ lvt_error_t error; - lvt_lint_t lint; - tpr_t tpr; - svr_t svr; - icr_t icr; - tdcr_t tdcr; - lvt_tm_t tm; - ldr_t ldr; - dfr_t dfr; - uint32_t t1, t2; - - /* Initialize LVT Error register. */ + error.value = l_apic[LVT_Err]; error.masked = true; l_apic[LVT_Err] = error.value; - + /* Initialize LVT LINT0 register. */ + lvt_lint_t lint; + lint.value = l_apic[LVT_LINT0]; lint.masked = true; l_apic[LVT_LINT0] = lint.value; - + /* Initialize LVT LINT1 register. */ lint.value = l_apic[LVT_LINT1]; lint.masked = true; l_apic[LVT_LINT1] = lint.value; - + /* Task Priority Register initialization. */ + tpr_t tpr; + tpr.value = l_apic[TPR]; tpr.pri_sc = 0; @@ -379,4 +380,6 @@ /* Spurious-Interrupt Vector Register initialization. */ + svr_t svr; + svr.value = l_apic[SVR]; svr.vector = VECTOR_APIC_SPUR; @@ -384,9 +387,11 @@ svr.focus_checking = true; l_apic[SVR] = svr.value; - + if (CPU->arch.family >= 6) enable_l_apic_in_msr(); /* Interrupt Command Register initialization. */ + icr_t icr; + icr.lo = l_apic[ICRlo]; icr.delmod = DELMOD_INIT; @@ -398,9 +403,13 @@ /* Timer Divide Configuration Register initialization. */ + tdcr_t tdcr; + tdcr.value = l_apic[TDCR]; tdcr.div_value = DIVIDE_1; l_apic[TDCR] = tdcr.value; - + /* Program local timer. */ + lvt_tm_t tm; + tm.value = l_apic[LVT_Tm]; tm.vector = VECTOR_CLK; @@ -408,23 +417,24 @@ tm.masked = false; l_apic[LVT_Tm] = tm.value; - + /* * Measure and configure the timer to generate timer * interrupt with period 1s/HZ seconds. */ + uint32_t t1 = l_apic[CCRT]; + l_apic[ICRT] = 0xffffffff; + + while (l_apic[CCRT] == t1); + t1 = l_apic[CCRT]; - l_apic[ICRT] = 0xffffffff; - - while (l_apic[CCRT] == t1) - ; - - t1 = l_apic[CCRT]; - delay(1000000/HZ); - t2 = l_apic[CCRT]; - - l_apic[ICRT] = t1-t2; + delay(1000000 / HZ); + uint32_t t2 = l_apic[CCRT]; + + l_apic[ICRT] = t1 - t2; /* Program Logical Destination Register. */ ASSERT(CPU->id < 8); + ldr_t ldr; + ldr.value = l_apic[LDR]; ldr.id = (uint8_t) (1 << CPU->id); @@ -432,4 +442,6 @@ /* Program Destination Format Register for Flat mode. */ + dfr_t dfr; + dfr.value = l_apic[DFR]; dfr.model = MODEL_FLAT; @@ -447,16 +459,17 @@ { #ifdef LAPIC_VERBOSE + printf("LVT on cpu%" PRIs ", LAPIC ID: %" PRIu8 "\n", CPU->id, l_apic_id()); + lvt_tm_t tm; - lvt_lint_t lint; - lvt_error_t error; - - printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); - tm.value = l_apic[LVT_Tm]; printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); + + lvt_lint_t lint; lint.value = l_apic[LVT_LINT0]; printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); lint.value = l_apic[LVT_LINT1]; printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); + + lvt_error_t error; error.value = l_apic[LVT_Err]; printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); @@ -467,4 +480,5 @@ * * @return Local APIC ID. + * */ uint8_t l_apic_id(void) @@ -481,4 +495,5 @@ * * @return Content of the addressed IO APIC register. + * */ uint32_t io_apic_read(uint8_t address) @@ -495,7 +510,8 @@ * * @param address IO APIC register address. - * @param x Content to be written to the addressed IO APIC register. - */ -void io_apic_write(uint8_t address, uint32_t x) + * @param val Content to be written to the addressed IO APIC register. + * + */ +void io_apic_write(uint8_t address, uint32_t val) { io_regsel_t regsel; @@ -504,22 +520,26 @@ regsel.reg_addr = address; io_apic[IOREGSEL] = regsel.value; - io_apic[IOWIN] = x; + io_apic[IOWIN] = val; } /** Change some attributes of one item in I/O Redirection Table. * - * @param pin IO APIC pin number. - * @param dest Interrupt destination address. - * @param v Interrupt vector to trigger. + * @param pin IO APIC pin number. + * @param dest Interrupt destination address. + * @param vec Interrupt vector to trigger. * @param flags Flags. - */ -void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t v, int flags) -{ - io_redirection_reg_t reg; - int dlvr = DELMOD_FIXED; + * + */ +void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t vec, + unsigned int flags) +{ + unsigned int dlvr; if (flags & LOPRI) dlvr = DELMOD_LOWPRI; - + else + dlvr = DELMOD_FIXED; + + io_redirection_reg_t reg; reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2)); reg.hi = io_apic_read((uint8_t) (IOREDTBL + pin * 2 + 1)); @@ -530,6 +550,6 @@ reg.intpol = POLARITY_HIGH; reg.delmod = dlvr; - reg.intvec = v; - + reg.intvec = vec; + io_apic_write((uint8_t) (IOREDTBL + pin * 2), reg.lo); io_apic_write((uint8_t) (IOREDTBL + pin * 2 + 1), reg.hi); @@ -539,11 +559,9 @@ * * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). + * */ void io_apic_disable_irqs(uint16_t irqmask) { - io_redirection_reg_t reg; unsigned int i; - int pin; - for (i = 0; i < 16; i++) { if (irqmask & (1 << i)) { @@ -552,6 +570,8 @@ * mapping for the respective IRQ number. */ - pin = smp_irq_to_pin(i); + int pin = smp_irq_to_pin(i); if (pin != -1) { + io_redirection_reg_t reg; + reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2)); reg.masked = true; @@ -566,11 +586,9 @@ * * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). + * */ void io_apic_enable_irqs(uint16_t irqmask) { unsigned int i; - int pin; - io_redirection_reg_t reg; - for (i = 0; i < 16; i++) { if (irqmask & (1 << i)) { @@ -579,6 +597,8 @@ * mapping for the respective IRQ number. */ - pin = smp_irq_to_pin(i); + int pin = smp_irq_to_pin(i); if (pin != -1) { + io_redirection_reg_t reg; + reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2)); reg.masked = false;