Index: kernel/arch/sparc64/include/mm/cache_spec.h
===================================================================
--- kernel/arch/sparc64/include/mm/cache_spec.h	(revision d7c9fcbada5f87468ffaff65b3781cb5cfe0f582)
+++ kernel/arch/sparc64/include/mm/cache_spec.h	(revision d7c9fcbada5f87468ffaff65b3781cb5cfe0f582)
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2008 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/** @addtogroup sparc64mm	
+ * @{
+ */
+/** @file
+ */
+
+#ifndef KERN_sparc64_CACHE_SPEC_H_
+#define KERN_sparc64_CACHE_SPEC_H_
+
+/*
+ * The following macros are valid for the following processors:
+ *
+ * 	UltraSPARC, UltraSPARC II, UltraSPARC IIi
+ * 
+ * Should we support other UltraSPARC processors, we need to make sure that
+ * the macros are defined correctly for them.
+ */
+
+#define DCACHE_SIZE		(16 * 1024)
+#define DCACHE_LINE_SIZE	32	
+
+#define ICACHE_SIZE		(16 * 1024)
+#define ICACHE_WAYS		2
+#define ICACHE_LINE_SIZE	32
+
+#endif
+
+/** @}
+ */
Index: kernel/arch/sparc64/include/mm/tlb.h
===================================================================
--- kernel/arch/sparc64/include/mm/tlb.h	(revision 71eef11b8afe2eec0d0ac48ea6fce51144cb5b0c)
+++ kernel/arch/sparc64/include/mm/tlb.h	(revision d7c9fcbada5f87468ffaff65b3781cb5cfe0f582)
@@ -161,5 +161,5 @@
 {
 	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
-	flush();
+	flush_blind();
 }
 
@@ -180,5 +180,5 @@
 {
 	asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
-	flush();
+	flush_blind();
 }
 
@@ -210,5 +210,5 @@
 	reg.tlb_entry = entry;
 	asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
-	flush();
+	flush_blind();
 }
 
@@ -280,5 +280,5 @@
 {
 	asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
-	flush();
+	flush_blind();
 }
 
@@ -319,5 +319,5 @@
 {
 	asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
-	flush();
+	flush_blind();
 }
 
@@ -348,5 +348,5 @@
 {
 	asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
-	flush();
+	flush_blind();
 }
 
@@ -401,5 +401,5 @@
 							 * address within the
 							 * ASI */ 
-	flush();
+	flush_blind();
 }