Index: kernel/arch/amd64/include/mm/page.h =================================================================== --- kernel/arch/amd64/include/mm/page.h (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/amd64/include/mm/page.h (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -177,5 +177,23 @@ #define PFERR_CODE_ID (1 << 4) -static inline int get_pt_flags(pte_t *pt, size_t i) +/** Page Table Entry. */ +typedef struct { + unsigned present : 1; + unsigned writeable : 1; + unsigned uaccessible : 1; + unsigned page_write_through : 1; + unsigned page_cache_disable : 1; + unsigned accessed : 1; + unsigned dirty : 1; + unsigned unused: 1; + unsigned global : 1; + unsigned soft_valid : 1; /**< Valid content even if present bit is cleared. */ + unsigned avl : 2; + unsigned addr_12_31 : 30; + unsigned addr_32_51 : 21; + unsigned no_execute : 1; +} __attribute__ ((packed)) pte_t; + +static inline unsigned int get_pt_flags(pte_t *pt, size_t i) { pte_t *p = &pt[i]; Index: kernel/arch/amd64/include/types.h =================================================================== --- kernel/arch/amd64/include/types.h (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/amd64/include/types.h (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -82,22 +82,4 @@ #define PRIxn "llx" -/** Page Table Entry. */ -typedef struct { - unsigned present : 1; - unsigned writeable : 1; - unsigned uaccessible : 1; - unsigned page_write_through : 1; - unsigned page_cache_disable : 1; - unsigned accessed : 1; - unsigned dirty : 1; - unsigned unused: 1; - unsigned global : 1; - unsigned soft_valid : 1; /**< Valid content even if present bit is cleared. */ - unsigned avl : 2; - unsigned addr_12_31 : 30; - unsigned addr_32_51 : 21; - unsigned no_execute : 1; -} __attribute__ ((packed)) pte_t; - #endif Index: kernel/arch/amd64/src/amd64.c =================================================================== --- kernel/arch/amd64/src/amd64.c (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/amd64/src/amd64.c (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -67,4 +67,5 @@ #include #include +#include /** Disable I/O on non-privileged levels Index: kernel/arch/amd64/src/interrupt.c =================================================================== --- kernel/arch/amd64/src/interrupt.c (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/amd64/src/interrupt.c (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -98,4 +98,11 @@ } +static void de_fault(int n, istate_t *istate) +{ + fault_if_from_uspace(istate, "Divide error."); + decode_istate(n, istate); + panic("Divide error."); +} + /** General Protection Fault. */ static void gp_fault(int n, istate_t *istate) @@ -200,4 +207,5 @@ } + exc_register(0, "de_fault", (iroutine) de_fault); exc_register(7, "nm_fault", (iroutine) nm_fault); exc_register(12, "ss_fault", (iroutine) ss_fault); Index: kernel/arch/arm32/Makefile.inc =================================================================== --- kernel/arch/arm32/Makefile.inc (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/arm32/Makefile.inc (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -61,5 +61,6 @@ arch/$(KARCH)/src/mm/page.c \ arch/$(KARCH)/src/mm/tlb.c \ - arch/$(KARCH)/src/mm/page_fault.c + arch/$(KARCH)/src/mm/page_fault.c \ + arch/$(KARCH)/src/ras.c ifeq ($(MACHINE),testarm) Index: kernel/arch/arm32/include/atomic.h =================================================================== --- kernel/arch/arm32/include/atomic.h (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/arm32/include/atomic.h (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -37,4 +37,6 @@ #define KERN_arm32_ATOMIC_H_ +#include + /** Atomic addition. * @@ -47,19 +49,14 @@ static inline long atomic_add(atomic_t *val, int i) { - int ret; - volatile long *mem = &(val->count); - - asm volatile ( - "1:\n" - "ldr r2, [%[mem]]\n" - "add r3, r2, %[i]\n" - "str r3, %[ret]\n" - "swp r3, r3, [%[mem]]\n" - "cmp r3, r2\n" - "bne 1b\n" - : [ret] "=m" (ret) - : [mem] "r" (mem), [i] "r" (i) - : "r3", "r2" - ); + long ret; + + /* + * This implementation is for UP pre-ARMv6 systems where we do not have + * the LDREX and STREX instructions. + */ + ipl_t ipl = interrupts_disable(); + val->count += i; + ret = val->count; + interrupts_restore(ipl); return ret; Index: kernel/arch/arm32/include/mm/as.h =================================================================== --- kernel/arch/arm32/include/mm/as.h (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/arm32/include/mm/as.h (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -54,5 +54,4 @@ #define as_destructor_arch(as) (as != as) #define as_create_arch(as, flags) (as != as) -#define as_install_arch(as) #define as_deinstall_arch(as) #define as_invalidate_translation_cache(as, page, cnt) Index: kernel/arch/arm32/include/mm/page.h =================================================================== --- kernel/arch/arm32/include/mm/page.h (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/arm32/include/mm/page.h (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -75,5 +75,5 @@ /* Get PTE address accessors for each level. */ #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ - ((pte_t *) ((((pte_level0_t *)(ptl0))[(i)]).coarse_table_addr << 10)) + ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10)) #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ (ptl1) @@ -81,19 +81,19 @@ (ptl2) #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ - ((uintptr_t) ((((pte_level1_t *)(ptl3))[(i)]).frame_base_addr << 12)) + ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12)) /* Set PTE address accessors for each level. */ #define SET_PTL0_ADDRESS_ARCH(ptl0) \ - (set_ptl0_addr((pte_level0_t *) (ptl0))) + (set_ptl0_addr((pte_t *) (ptl0))) #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ - (((pte_level0_t *) (ptl0))[(i)].coarse_table_addr = (a) >> 10) + (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10) #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ - (((pte_level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12) + (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12) /* Get PTE flags accessors for each level. */ #define GET_PTL1_FLAGS_ARCH(ptl0, i) \ - get_pt_level0_flags((pte_level0_t *) (ptl0), (size_t) (i)) + get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i)) #define GET_PTL2_FLAGS_ARCH(ptl1, i) \ PAGE_PRESENT @@ -101,13 +101,13 @@ PAGE_PRESENT #define GET_FRAME_FLAGS_ARCH(ptl3, i) \ - get_pt_level1_flags((pte_level1_t *) (ptl3), (size_t) (i)) + get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i)) /* Set PTE flags accessors for each level. */ #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ - set_pt_level0_flags((pte_level0_t *) (ptl0), (size_t) (i), (x)) + set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x)) #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ - set_pt_level1_flags((pte_level1_t *) (ptl3), (size_t) (i), (x)) + set_pt_level1_flags((pte_t *) (ptl3), (size_t) (i), (x)) /* Macros for querying the last-level PTE entries. */ @@ -115,10 +115,9 @@ (*((uint32_t *) (pte)) != 0) #define PTE_PRESENT_ARCH(pte) \ - (((pte_level0_t *) (pte))->descriptor_type != 0) + (((pte_t *) (pte))->l0.descriptor_type != 0) #define PTE_GET_FRAME_ARCH(pte) \ - (((pte_level1_t *) (pte))->frame_base_addr << FRAME_WIDTH) + (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH) #define PTE_WRITABLE_ARCH(pte) \ - (((pte_level1_t *) (pte))->access_permission_0 == \ - PTE_AP_USER_RW_KERNEL_RW) + (((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) #define PTE_EXECUTABLE_ARCH(pte) \ 1 @@ -159,4 +158,8 @@ } ATTRIBUTE_PACKED pte_level1_t; +typedef union { + pte_level0_t l0; + pte_level1_t l1; +} pte_t; /* Level 1 page tables access permissions */ @@ -191,5 +194,5 @@ * @param pt Pointer to the page table to set. */ -static inline void set_ptl0_addr(pte_level0_t *pt) +static inline void set_ptl0_addr(pte_t *pt) { asm volatile ( @@ -205,7 +208,7 @@ * @param i Index of the entry to return. */ -static inline int get_pt_level0_flags(pte_level0_t *pt, size_t i) -{ - pte_level0_t *p = &pt[i]; +static inline int get_pt_level0_flags(pte_t *pt, size_t i) +{ + pte_level0_t *p = &pt[i].l0; int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); @@ -220,7 +223,7 @@ * @param i Index of the entry to return. */ -static inline int get_pt_level1_flags(pte_level1_t *pt, size_t i) -{ - pte_level1_t *p = &pt[i]; +static inline int get_pt_level1_flags(pte_t *pt, size_t i) +{ + pte_level1_t *p = &pt[i].l1; int dt = p->descriptor_type; @@ -245,7 +248,7 @@ * @param flags new flags */ -static inline void set_pt_level0_flags(pte_level0_t *pt, size_t i, int flags) -{ - pte_level0_t *p = &pt[i]; +static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags) +{ + pte_level0_t *p = &pt[i].l0; if (flags & PAGE_NOT_PRESENT) { @@ -273,7 +276,7 @@ * @param flags New flags. */ -static inline void set_pt_level1_flags(pte_level1_t *pt, size_t i, int flags) -{ - pte_level1_t *p = &pt[i]; +static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags) +{ + pte_level1_t *p = &pt[i].l1; if (flags & PAGE_NOT_PRESENT) { Index: kernel/arch/arm32/include/ras.h =================================================================== --- kernel/arch/arm32/include/ras.h (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) +++ kernel/arch/arm32/include/ras.h (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2009 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief Declarations related to Restartable Atomic Sequences. + */ + +#ifndef KERN_arm32_RAS_H_ +#define KERN_arm32_RAS_H_ + +#include +#include + +#define RAS_START 0 +#define RAS_END 1 + +extern uintptr_t *ras_page; + +extern void ras_init(void); +extern void ras_check(int, istate_t *); + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/types.h =================================================================== --- kernel/arch/arm32/include/types.h (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/arm32/include/types.h (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -87,13 +87,4 @@ #define PRIxn "x" /**< Format for hexadecimal (u)native_t. */ -/** Page table entry. - * - * We have different structs for level 0 and level 1 page table entries. - * See page.h for definition of pte_level*_t. - */ -typedef struct { - unsigned dummy : 32; -} pte_t; - #endif Index: kernel/arch/arm32/src/arm32.c =================================================================== --- kernel/arch/arm32/src/arm32.c (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/arm32/src/arm32.c (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -48,4 +48,5 @@ #include #include +#include #ifdef MACHINE_testarm @@ -88,4 +89,7 @@ exception_init(); interrupt_init(); + + /* Initialize Restartable Atomic Sequences support. */ + ras_init(); machine_output_init(); @@ -136,5 +140,4 @@ uint8_t *stck; - tlb_invalidate_all(); stck = &THREAD->kstack[THREAD_STACK_SIZE - SP_DELTA]; supervisor_sp = (uintptr_t) stck; Index: kernel/arch/arm32/src/exc_handler.S =================================================================== --- kernel/arch/arm32/src/exc_handler.S (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/arm32/src/exc_handler.S (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -148,5 +148,5 @@ mov r0, #0 mov r1, r13 - bl exc_dispatch + bl ras_check LOAD_REGS_FROM_STACK @@ -156,5 +156,5 @@ mov r0, #5 mov r1, r13 - bl exc_dispatch + bl ras_check LOAD_REGS_FROM_STACK @@ -164,5 +164,5 @@ mov r0, #6 mov r1, r13 - bl exc_dispatch + bl ras_check LOAD_REGS_FROM_STACK @@ -171,5 +171,5 @@ mov r0, #1 mov r1, r13 - bl exc_dispatch + bl ras_check LOAD_REGS_FROM_STACK @@ -179,5 +179,5 @@ mov r0, #3 mov r1, r13 - bl exc_dispatch + bl ras_check LOAD_REGS_FROM_STACK @@ -187,5 +187,5 @@ mov r0, #4 mov r1, r13 - bl exc_dispatch + bl ras_check LOAD_REGS_FROM_STACK @@ -195,5 +195,5 @@ mov r0, #2 mov r1, r13 - bl exc_dispatch + bl ras_check LOAD_REGS_FROM_STACK Index: kernel/arch/arm32/src/mm/as.c =================================================================== --- kernel/arch/arm32/src/mm/as.c (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/arm32/src/mm/as.c (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -36,6 +36,8 @@ #include #include +#include #include #include +#include #include @@ -49,4 +51,9 @@ } +void as_install_arch(as_t *as) +{ + tlb_invalidate_all(); +} + /** @} */ Index: kernel/arch/arm32/src/ras.c =================================================================== --- kernel/arch/arm32/src/ras.c (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) +++ kernel/arch/arm32/src/ras.c (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2009 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief Kernel part of Restartable Atomic Sequences support. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +uintptr_t *ras_page = NULL; + +void ras_init(void) +{ + ras_page = frame_alloc(ONE_FRAME, FRAME_KA); + memsetb(ras_page, FRAME_SIZE, 0); + ras_page[RAS_START] = 0; + ras_page[RAS_END] = 0xffffffff; + /* + * Userspace needs to be able to write to this page. The page is + * cached in TLB as PAGE_KERNEL. Purge it from TLB and map it + * read/write PAGE_USER. + */ + tlb_invalidate_pages(ASID_KERNEL, (uintptr_t)ras_page, 1); + page_table_lock(AS, true); + page_mapping_insert(AS, (uintptr_t)ras_page, (uintptr_t)KA2PA(ras_page), + PAGE_READ | PAGE_WRITE | PAGE_USER); + page_table_unlock(AS, true); +} + +void ras_check(int n, istate_t *istate) +{ + uintptr_t rewrite_pc = istate->pc; + + if (istate_from_uspace(istate)) { + if (ras_page[RAS_START]) { + if ((ras_page[RAS_START] < istate->pc) && + (ras_page[RAS_END] > istate->pc)) { + rewrite_pc = ras_page[RAS_START]; + } + ras_page[RAS_START] = 0; + ras_page[RAS_END] = 0xffffffff; + } + } + + exc_dispatch(n, istate); + + istate->pc = rewrite_pc; +} + Index: kernel/arch/arm32/src/userspace.c =================================================================== --- kernel/arch/arm32/src/userspace.c (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/arm32/src/userspace.c (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -35,4 +35,5 @@ #include +#include /** Struct for holding all general purpose registers. @@ -74,8 +75,11 @@ ustate.r1 = 0; + /* pass the RAS page address in %r2 */ + ustate.r2 = (uintptr_t) ras_page; + /* clear other registers */ - ustate.r2 = ustate.r3 = ustate.r4 = ustate.r5 = - ustate.r6 = ustate.r7 = ustate.r8 = ustate.r9 = ustate.r10 = - ustate.r11 = ustate.r12 = ustate.lr = 0; + ustate.r3 = ustate.r4 = ustate.r5 = ustate.r6 = ustate.r7 = + ustate.r8 = ustate.r9 = ustate.r10 = ustate.r11 = ustate.r12 = + ustate.lr = 0; /* set user stack */ Index: kernel/arch/ia32/include/mm/page.h =================================================================== --- kernel/arch/ia32/include/mm/page.h (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/ia32/include/mm/page.h (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -146,5 +146,21 @@ #define PFERR_CODE_RSVD (1 << 3) -static inline int get_pt_flags(pte_t *pt, size_t i) +/** Page Table Entry. */ +typedef struct { + unsigned present : 1; + unsigned writeable : 1; + unsigned uaccessible : 1; + unsigned page_write_through : 1; + unsigned page_cache_disable : 1; + unsigned accessed : 1; + unsigned dirty : 1; + unsigned pat : 1; + unsigned global : 1; + unsigned soft_valid : 1; /**< Valid content even if the present bit is not set. */ + unsigned avl : 2; + unsigned frame_address : 20; +} __attribute__ ((packed)) pte_t; + +static inline unsigned int get_pt_flags(pte_t *pt, size_t i) { pte_t *p = &pt[i]; Index: kernel/arch/ia32/include/types.h =================================================================== --- kernel/arch/ia32/include/types.h (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/ia32/include/types.h (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -80,20 +80,4 @@ #define PRIxn "x" /**< Format for hexadecimal (u)native_t. */ -/** Page Table Entry. */ -typedef struct { - unsigned present : 1; - unsigned writeable : 1; - unsigned uaccessible : 1; - unsigned page_write_through : 1; - unsigned page_cache_disable : 1; - unsigned accessed : 1; - unsigned dirty : 1; - unsigned pat : 1; - unsigned global : 1; - unsigned soft_valid : 1; /**< Valid content even if the present bit is not set. */ - unsigned avl : 2; - unsigned frame_address : 20; -} __attribute__ ((packed)) pte_t; - #endif Index: kernel/arch/ia32/src/ia32.c =================================================================== --- kernel/arch/ia32/src/ia32.c (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/ia32/src/ia32.c (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -68,4 +68,5 @@ #include #include +#include #ifdef CONFIG_SMP Index: kernel/arch/ia32/src/interrupt.c =================================================================== --- kernel/arch/ia32/src/interrupt.c (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/ia32/src/interrupt.c (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -98,4 +98,12 @@ } +static void de_fault(int n, istate_t *istate) +{ + fault_if_from_uspace(istate, "Divide error."); + + decode_istate(istate); + panic("Divide error."); +} + /** General Protection Fault. */ static void gp_fault(int n __attribute__((unused)), istate_t *istate) @@ -215,4 +223,5 @@ } + exc_register(0, "de_fault", (iroutine) de_fault); exc_register(7, "nm_fault", (iroutine) nm_fault); exc_register(12, "ss_fault", (iroutine) ss_fault); Index: kernel/arch/ia64/src/cpu/cpu.c =================================================================== --- kernel/arch/ia64/src/cpu/cpu.c (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/ia64/src/cpu/cpu.c (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -37,4 +37,5 @@ #include #include +#include void cpu_arch_init(void) Index: kernel/arch/mips32/include/mm/page.h =================================================================== --- kernel/arch/mips32/include/mm/page.h (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/mips32/include/mm/page.h (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -141,5 +141,19 @@ #include -static inline int get_pt_flags(pte_t *pt, size_t i) +/** Page Table Entry. */ +typedef struct { + unsigned g : 1; /**< Global bit. */ + unsigned p : 1; /**< Present bit. */ + unsigned d : 1; /**< Dirty bit. */ + unsigned cacheable : 1; /**< Cacheable bit. */ + unsigned : 1; /**< Unused. */ + unsigned soft_valid : 1; /**< Valid content even if not present. */ + unsigned pfn : 24; /**< Physical frame number. */ + unsigned w : 1; /**< Page writable bit. */ + unsigned a : 1; /**< Accessed bit. */ +} pte_t; + + +static inline unsigned int get_pt_flags(pte_t *pt, size_t i) { pte_t *p = &pt[i]; Index: kernel/arch/mips32/include/types.h =================================================================== --- kernel/arch/mips32/include/types.h (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/mips32/include/types.h (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -80,17 +80,4 @@ #define PRIxn "x" /**< Format for hexadecimal (u)native_t. */ -/** Page Table Entry. */ -typedef struct { - unsigned g : 1; /**< Global bit. */ - unsigned p : 1; /**< Present bit. */ - unsigned d : 1; /**< Dirty bit. */ - unsigned cacheable : 1; /**< Cacheable bit. */ - unsigned : 1; /**< Unused. */ - unsigned soft_valid : 1; /**< Valid content even if not present. */ - unsigned pfn : 24; /**< Physical frame number. */ - unsigned w : 1; /**< Page writable bit. */ - unsigned a : 1; /**< Accessed bit. */ -} pte_t; - #endif Index: kernel/arch/ppc32/include/mm/page.h =================================================================== --- kernel/arch/ppc32/include/mm/page.h (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/ppc32/include/mm/page.h (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -131,5 +131,16 @@ #include -static inline int get_pt_flags(pte_t *pt, size_t i) +/** Page Table Entry. */ +typedef struct { + unsigned present : 1; /**< Present bit. */ + unsigned page_write_through : 1; /**< Write thought caching. */ + unsigned page_cache_disable : 1; /**< No caching. */ + unsigned accessed : 1; /**< Accessed bit. */ + unsigned global : 1; /**< Global bit. */ + unsigned valid : 1; /**< Valid content even if not present. */ + unsigned pfn : 20; /**< Physical frame number. */ +} pte_t; + +static inline unsigned int get_pt_flags(pte_t *pt, size_t i) { pte_t *p = &pt[i]; Index: kernel/arch/ppc32/include/types.h =================================================================== --- kernel/arch/ppc32/include/types.h (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/ppc32/include/types.h (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -82,15 +82,4 @@ #define PRIxn "x" -/** Page Table Entry. */ -typedef struct { - unsigned present : 1; /**< Present bit. */ - unsigned page_write_through : 1; /**< Write thought caching. */ - unsigned page_cache_disable : 1; /**< No caching. */ - unsigned accessed : 1; /**< Accessed bit. */ - unsigned global : 1; /**< Global bit. */ - unsigned valid : 1; /**< Valid content even if not present. */ - unsigned pfn : 20; /**< Physical frame number. */ -} pte_t; - #endif Index: kernel/arch/ppc32/src/mm/as.c =================================================================== --- kernel/arch/ppc32/src/mm/as.c (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/ppc32/src/mm/as.c (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -35,4 +35,5 @@ #include #include +#include #include #include Index: kernel/arch/ppc32/src/mm/tlb.c =================================================================== --- kernel/arch/ppc32/src/mm/tlb.c (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/ppc32/src/mm/tlb.c (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -38,4 +38,5 @@ #include #include +#include #include #include Index: kernel/arch/ppc32/src/ppc32.c =================================================================== --- kernel/arch/ppc32/src/ppc32.c (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/ppc32/src/ppc32.c (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -44,4 +44,5 @@ #include #include +#include #include #include Index: kernel/arch/sparc64/src/mm/tlb.c =================================================================== --- kernel/arch/sparc64/src/mm/tlb.c (revision 245e8399f3d58ad45fc1730f6b948b33ae3ab8df) +++ kernel/arch/sparc64/src/mm/tlb.c (revision d6ff0fc53f67dba89ea46f18d5e2d03e8f665c4d) @@ -37,4 +37,5 @@ #include #include +#include #include #include