Index: arch/ia32/include/barrier.h
===================================================================
--- arch/ia32/include/barrier.h	(revision 3bf597623745263fdb3d4abbb40c083b7cec3cb0)
+++ arch/ia32/include/barrier.h	(revision d6e5cbc6f5fd409a91c10cc64f7841774bcf8b94)
@@ -30,6 +30,4 @@
 #define __ia32_BARRIER_H__
 
-#include <arch/types.h>
-
 /*
  * NOTE:
@@ -61,5 +59,5 @@
 #		define write_barrier()	__asm__ volatile ("sfence\n" ::: "memory")
 #	else
-#		define write_barrier()
+#		define write_barrier()  __asm__ volatile( "" ::: "memory");
 #	endif
 #elif CONFIG_FENCES_P3
@@ -69,5 +67,5 @@
 #		define write_barrier()	__asm__ volatile ("sfence\n" ::: "memory")
 #	else
-#		define write_barrier()
+#		define write_barrier()  __asm__ volatile( "" ::: "memory");
 #	endif
 #else
@@ -77,5 +75,5 @@
 #		define write_barrier()	cpuid_serialization()
 #	else
-#		define write_barrier()
+#		define write_barrier()  __asm__ volatile( "" ::: "memory");
 #	endif
 #endif
Index: arch/mips32/include/barrier.h
===================================================================
--- arch/mips32/include/barrier.h	(revision 3bf597623745263fdb3d4abbb40c083b7cec3cb0)
+++ arch/mips32/include/barrier.h	(revision d6e5cbc6f5fd409a91c10cc64f7841774bcf8b94)
@@ -36,7 +36,7 @@
 #define CS_LEAVE_BARRIER()	__asm__ volatile ("" ::: "memory")
 
-#define memory_barrier()
-#define read_barrier()
-#define write_barrier()
+#define memory_barrier()        __asm__ volatile ("" ::: "memory")
+#define read_barrier()          __asm__ volatile ("" ::: "memory")
+#define write_barrier()         __asm__ volatile ("" ::: "memory")
 
 #endif
Index: arch/mips32/include/cp0.h
===================================================================
--- arch/mips32/include/cp0.h	(revision 3bf597623745263fdb3d4abbb40c083b7cec3cb0)
+++ arch/mips32/include/cp0.h	(revision d6e5cbc6f5fd409a91c10cc64f7841774bcf8b94)
@@ -50,7 +50,6 @@
 /*
  * Magic value for use in msim.
- * On AMD Duron 800Mhz, this roughly seems like one us.
  */
-#define cp0_compare_value 		10000
+#define cp0_compare_value 		100000
 
 #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
Index: arch/mips32/src/interrupt.c
===================================================================
--- arch/mips32/src/interrupt.c	(revision 3bf597623745263fdb3d4abbb40c083b7cec3cb0)
+++ arch/mips32/src/interrupt.c	(revision d6e5cbc6f5fd409a91c10cc64f7841774bcf8b94)
@@ -77,7 +77,24 @@
 }
 
+/* TODO: This is SMP unsafe!!! */
+static unsigned long nextcount;
+/** Start hardware clock */
+static void timer_start(void)
+{
+	nextcount = cp0_compare_value + cp0_count_read();
+	cp0_compare_write(nextcount);
+}
+
 static void timer_exception(int n, istate_t *istate)
 {
-	cp0_compare_write(cp0_count_read() + cp0_compare_value); 
+	unsigned long drift;
+
+	drift = cp0_count_read() - nextcount;
+	while (drift > cp0_compare_value) {
+		drift -= cp0_compare_value;
+		CPU->missed_clock_ticks++;
+	}
+	nextcount = cp0_count_read() + cp0_compare_value - drift;
+	cp0_compare_write(nextcount);
 	clock();
 }
@@ -101,4 +118,5 @@
 	int_register(0, "swint0", swint0);
 	int_register(1, "swint1", swint1);
+	timer_start();
 }
 
Index: arch/mips32/src/mips32.c
===================================================================
--- arch/mips32/src/mips32.c	(revision 3bf597623745263fdb3d4abbb40c083b7cec3cb0)
+++ arch/mips32/src/mips32.c	(revision d6e5cbc6f5fd409a91c10cc64f7841774bcf8b94)
@@ -81,6 +81,4 @@
 	/* Initialize dispatch table */
 	exception_init();
-	interrupt_init();
-
 	arc_init();
 
@@ -90,4 +88,5 @@
 	memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE);
 
+	interrupt_init();
 	/*
 	 * Switch to BEV normal level so that exception vectors point to the kernel.
@@ -100,13 +99,9 @@
 	 */
 	cp0_mask_all_int();
+
 	/*
 	 * Unmask hardware clock interrupt.
 	 */
 	cp0_unmask_int(TIMER_IRQ);
-
-	/*
-	 * Start hardware clock.
-	 */
-	cp0_compare_write(cp0_compare_value + cp0_count_read());
 
 	console_init();
Index: generic/include/time/clock.h
===================================================================
--- generic/include/time/clock.h	(revision 3bf597623745263fdb3d4abbb40c083b7cec3cb0)
+++ generic/include/time/clock.h	(revision d6e5cbc6f5fd409a91c10cc64f7841774bcf8b94)
@@ -33,4 +33,5 @@
 
 extern void clock(void);
+extern void clock_counter_init(void);
 
 #endif
Index: generic/src/ipc/sysipc.c
===================================================================
--- generic/src/ipc/sysipc.c	(revision 3bf597623745263fdb3d4abbb40c083b7cec3cb0)
+++ generic/src/ipc/sysipc.c	(revision d6e5cbc6f5fd409a91c10cc64f7841774bcf8b94)
@@ -152,4 +152,5 @@
 			ipl_t ipl;
 			as_t *as;
+			int rc;
 			
 			ipl = interrupts_disable();
@@ -159,6 +160,7 @@
 			interrupts_restore(ipl);
 			
-			return as_area_share(AS, IPC_GET_ARG1(answer->data), IPC_GET_ARG2(*olddata),
-					     as, IPC_GET_ARG1(*olddata), IPC_GET_ARG3(*olddata));
+			rc = as_area_share(AS, IPC_GET_ARG1(answer->data), IPC_GET_ARG2(*olddata),
+					   as, IPC_GET_ARG1(*olddata), IPC_GET_ARG3(*olddata));
+			IPC_SET_RETVAL(answer->data, rc);
 		}
 	}
Index: generic/src/main/main.c
===================================================================
--- generic/src/main/main.c	(revision 3bf597623745263fdb3d4abbb40c083b7cec3cb0)
+++ generic/src/main/main.c	(revision d6e5cbc6f5fd409a91c10cc64f7841774bcf8b94)
@@ -198,5 +198,5 @@
 	tlb_init();
 	config.mm_initialized = true;
-	arch_post_mm_init();	
+	arch_post_mm_init();
 
 	version_print();
@@ -213,4 +213,5 @@
 	
 	calibrate_delay_loop();
+	clock_counter_init();
 	timeout_init();
 	scheduler_init();
Index: generic/src/mm/as.c
===================================================================
--- generic/src/mm/as.c	(revision 3bf597623745263fdb3d4abbb40c083b7cec3cb0)
+++ generic/src/mm/as.c	(revision d6e5cbc6f5fd409a91c10cc64f7841774bcf8b94)
@@ -478,5 +478,5 @@
 	mem_backend_t *src_backend;
 	mem_backend_data_t src_backend_data;
-
+	
 	ipl = interrupts_disable();
 	mutex_lock(&src_as->lock);
Index: generic/src/time/clock.c
===================================================================
--- generic/src/time/clock.c	(revision 3bf597623745263fdb3d4abbb40c083b7cec3cb0)
+++ generic/src/time/clock.c	(revision d6e5cbc6f5fd409a91c10cc64f7841774bcf8b94)
@@ -49,4 +49,66 @@
 #include <atomic.h>
 #include <proc/thread.h>
+#include <sysinfo/sysinfo.h>
+#include <arch/barrier.h>
+
+/* Pointers to public variables with time */
+struct ptime {
+	__native seconds;
+	__native useconds;
+	__native useconds2;
+};
+struct ptime *public_time;
+/* Variable holding fragment of second, so that we would update
+ * seconds correctly
+ */
+static __native secfrag = 0;
+
+/** Initialize realtime clock counter
+ *
+ * The applications (and sometimes kernel) need to access accurate
+ * information about realtime data. We allocate 1 page with these 
+ * data and update it periodically.
+ *
+ * 
+ */
+void clock_counter_init(void)
+{
+	void *faddr;
+
+	faddr = (void *)PFN2ADDR(frame_alloc(0, FRAME_ATOMIC));
+	if (!faddr)
+		panic("Cannot allocate page for clock");
+	
+	public_time = (struct ptime *)PA2KA(faddr);
+
+        /* TODO: We would need some arch dependent settings here */
+	public_time->seconds = 0;
+	public_time->useconds = 0; 
+
+	sysinfo_set_item_val("clock.faddr", NULL, (__native)faddr);
+}
+
+
+/** Update public counters
+ *
+ * Update it only on first processor
+ * TODO: Do we really need so many write barriers? 
+ */
+static void clock_update_counters(void)
+{
+	if (CPU->id == 0) {
+		secfrag += 1000000/HZ;
+		if (secfrag >= 1000000) {
+			public_time->useconds = 0;
+			write_barrier();
+			public_time->seconds++;
+			secfrag = 0;
+		} else
+			public_time->useconds += 1000000/HZ;
+		write_barrier();
+		public_time->useconds2 = public_time->useconds;
+		write_barrier();
+	}
+}
 
 /** Clock routine
@@ -70,4 +132,5 @@
 	 */
 	for (i = 0; i <= CPU->missed_clock_ticks; i++) {
+		clock_update_counters();
 		spinlock_lock(&CPU->timeoutlock);
 		while ((l = CPU->timeout_active_head.next) != &CPU->timeout_active_head) {
