Index: arch/mips32/include/barrier.h
===================================================================
--- arch/mips32/include/barrier.h	(revision fb8445570d1fefbb43a7a176047eda449d09879d)
+++ arch/mips32/include/barrier.h	(revision d6e5cbc6f5fd409a91c10cc64f7841774bcf8b94)
@@ -36,7 +36,7 @@
 #define CS_LEAVE_BARRIER()	__asm__ volatile ("" ::: "memory")
 
-#define memory_barrier()
-#define read_barrier()
-#define write_barrier()
+#define memory_barrier()        __asm__ volatile ("" ::: "memory")
+#define read_barrier()          __asm__ volatile ("" ::: "memory")
+#define write_barrier()         __asm__ volatile ("" ::: "memory")
 
 #endif
Index: arch/mips32/include/cp0.h
===================================================================
--- arch/mips32/include/cp0.h	(revision fb8445570d1fefbb43a7a176047eda449d09879d)
+++ arch/mips32/include/cp0.h	(revision d6e5cbc6f5fd409a91c10cc64f7841774bcf8b94)
@@ -50,7 +50,6 @@
 /*
  * Magic value for use in msim.
- * On AMD Duron 800Mhz, this roughly seems like one us.
  */
-#define cp0_compare_value 		10000
+#define cp0_compare_value 		100000
 
 #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))