Changeset d6c0016 in mainline
- Timestamp:
- 2018-05-22T19:06:50Z (6 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- d6f73b92
- Parents:
- 9e9ced0
- git-author:
- Jakub Jermar <jakub@…> (2018-04-22 12:16:08)
- git-committer:
- Jakub Jermar <jakub@…> (2018-05-22 19:06:50)
- Location:
- uspace/lib/virtio
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/lib/virtio/virtio-pci.c
r9e9ced0 rd6c0016 107 107 } 108 108 109 errno_t virtio_pci_dev_init(ddf_dev_t *dev, virtio_dev_t *vdev) 110 { 111 memset(vdev, 0, sizeof(virtio_dev_t)); 112 113 async_sess_t *pci_sess = ddf_dev_parent_sess_get(dev); 114 if (!pci_sess) 115 return ENOENT; 116 109 static errno_t enable_resources(async_sess_t *pci_sess, virtio_dev_t *vdev) 110 { 117 111 pio_window_t pio_window; 118 112 errno_t rc = pio_window_get(pci_sess, &pio_window); … … 139 133 rc = pci_config_space_read_32(pci_sess, 140 134 PCI_BAR0 + i * sizeof(uint32_t), &bar); 135 if (rc != EOK) 136 return rc; 141 137 if (!bar) 142 138 continue; 143 139 144 rc = pio_enable_resource(&pio_window, &hw_res.resources[j], 145 &vdev->bar[i].mapped_base, NULL); 140 hw_resource_t *res = &hw_res.resources[j]; 141 rc = pio_enable_resource(&pio_window, res, 142 &vdev->bar[i].mapped_base, &vdev->bar[i].mapped_size); 146 143 if (rc == EOK) 147 144 vdev->bar[i].mapped = true; 148 145 j++; 149 146 } 147 148 return rc; 149 } 150 151 static errno_t disable_resources(virtio_dev_t *vdev) 152 { 153 for (unsigned i = 0; i < PCI_BAR_COUNT; i++) { 154 if (vdev->bar[i].mapped) { 155 errno_t rc = pio_disable(vdev->bar[i].mapped_base, 156 vdev->bar[i].mapped_size); 157 if (rc != EOK) 158 return rc; 159 vdev->bar[i].mapped = false; 160 } 161 } 162 163 return EOK; 164 } 165 166 errno_t virtio_pci_dev_init(ddf_dev_t *dev, virtio_dev_t *vdev) 167 { 168 memset(vdev, 0, sizeof(virtio_dev_t)); 169 170 async_sess_t *pci_sess = ddf_dev_parent_sess_get(dev); 171 if (!pci_sess) 172 return ENOENT; 173 174 errno_t rc = enable_resources(pci_sess, vdev); 175 if (rc != EOK) 176 goto error; 150 177 151 178 /* … … 157 184 (rc == EOK) && c; 158 185 rc = pci_config_space_cap_next(pci_sess, &c, &id)) { 159 if (id == PCI_CAP_VENDORSPECID) { 160 uint8_t type; 161 rc = pci_config_space_read_8(pci_sess, 162 VIRTIO_PCI_CAP_TYPE(c), &type); 186 if (id != PCI_CAP_VENDORSPECID) 187 continue; 188 189 uint8_t type; 190 rc = pci_config_space_read_8(pci_sess, VIRTIO_PCI_CAP_TYPE(c), 191 &type); 192 if (rc != EOK) 193 goto error; 194 195 uint8_t bar; 196 rc = pci_config_space_read_8(pci_sess, VIRTIO_PCI_CAP_BAR(c), 197 &bar); 198 if (rc != EOK) 199 goto error; 200 201 uint32_t offset; 202 rc = pci_config_space_read_32(pci_sess, 203 VIRTIO_PCI_CAP_OFFSET(c), &offset); 204 if (rc != EOK) 205 goto error; 206 207 uint32_t length; 208 rc = pci_config_space_read_32(pci_sess, 209 VIRTIO_PCI_CAP_LENGTH(c), &length); 210 if (rc != EOK) 211 goto error; 212 213 uint32_t multiplier; 214 switch (type) { 215 case VIRTIO_PCI_CAP_COMMON_CFG: 216 virtio_pci_common_cfg(vdev, bar, offset, length); 217 break; 218 case VIRTIO_PCI_CAP_NOTIFY_CFG: 219 rc = pci_config_space_read_32(pci_sess, 220 VIRTIO_PCI_CAP_END(c), &multiplier); 163 221 if (rc != EOK) 164 return rc; 165 166 uint8_t bar; 167 rc = pci_config_space_read_8(pci_sess, 168 VIRTIO_PCI_CAP_BAR(c), &bar); 169 if (rc != EOK) 170 return rc; 171 172 uint32_t offset; 173 rc = pci_config_space_read_32(pci_sess, 174 VIRTIO_PCI_CAP_OFFSET(c), &offset); 175 if (rc != EOK) 176 return rc; 177 178 uint32_t length; 179 rc = pci_config_space_read_32(pci_sess, 180 VIRTIO_PCI_CAP_LENGTH(c), &length); 181 if (rc != EOK) 182 return rc; 183 184 uint32_t multiplier; 185 switch (type) { 186 case VIRTIO_PCI_CAP_COMMON_CFG: 187 virtio_pci_common_cfg(vdev, bar, offset, 188 length); 189 break; 190 case VIRTIO_PCI_CAP_NOTIFY_CFG: 191 rc = pci_config_space_read_32(pci_sess, 192 VIRTIO_PCI_CAP_END(c), &multiplier); 193 if (rc != EOK) 194 return rc; 195 virtio_pci_notify_cfg(vdev, bar, offset, length, 196 multiplier); 197 break; 198 case VIRTIO_PCI_CAP_ISR_CFG: 199 virtio_pci_isr_cfg(vdev, bar, offset, length); 200 break; 201 case VIRTIO_PCI_CAP_DEVICE_CFG: 202 virtio_pci_device_cfg(vdev, bar, offset, 203 length); 204 break; 205 case VIRTIO_PCI_CAP_PCI_CFG: 206 break; 207 default: 208 break; 209 } 222 goto error; 223 virtio_pci_notify_cfg(vdev, bar, offset, length, 224 multiplier); 225 break; 226 case VIRTIO_PCI_CAP_ISR_CFG: 227 virtio_pci_isr_cfg(vdev, bar, offset, length); 228 break; 229 case VIRTIO_PCI_CAP_DEVICE_CFG: 230 virtio_pci_device_cfg(vdev, bar, offset, length); 231 break; 232 case VIRTIO_PCI_CAP_PCI_CFG: 233 break; 234 default: 235 break; 210 236 } 211 237 } 212 238 213 239 return rc; 240 241 error: 242 (void) disable_resources(vdev); 243 return rc; 214 244 } 215 245 -
uspace/lib/virtio/virtio-pci.h
r9e9ced0 rd6c0016 73 73 bool mapped; 74 74 void *mapped_base; 75 size_t mapped_size; 75 76 } bar[PCI_BAR_COUNT]; 76 77
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