Index: kernel/arch/ia32/include/arch/asm.h
===================================================================
--- kernel/arch/ia32/include/arch/asm.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia32/include/arch/asm.h	(revision d5e5fd1214ee9617b9a936d6f09efec4c9a91b48)
@@ -174,5 +174,5 @@
 	if (((void *)port) < IO_SPACE_BOUNDARY) {
 		uint8_t val;
-		
+
 		asm volatile (
 			"inb %w[port], %b[val]\n"
@@ -180,5 +180,5 @@
 			: [port] "d" (port)
 		);
-		
+
 		return val;
 	} else
@@ -198,5 +198,5 @@
 	if (((void *)port) < IO_SPACE_BOUNDARY) {
 		uint16_t val;
-		
+
 		asm volatile (
 			"inw %w[port], %w[val]\n"
@@ -204,5 +204,5 @@
 			: [port] "d" (port)
 		);
-		
+
 		return val;
 	} else
@@ -222,5 +222,5 @@
 	if (((void *)port) < IO_SPACE_BOUNDARY) {
 		uint32_t val;
-		
+
 		asm volatile (
 			"inl %w[port], %[val]\n"
@@ -228,5 +228,5 @@
 			: [port] "d" (port)
 		);
-		
+
 		return val;
 	} else
@@ -243,5 +243,5 @@
 		: [v] "=r" (eflags)
 	);
-	
+
 	return eflags;
 }
@@ -276,7 +276,7 @@
 {
 	ipl_t ipl = interrupts_read();
-	
+
 	asm volatile ("sti\n");
-	
+
 	return ipl;
 }
@@ -292,7 +292,7 @@
 {
 	ipl_t ipl = interrupts_read();
-	
+
 	asm volatile ("cli\n");
-	
+
 	return ipl;
 }
@@ -336,5 +336,5 @@
 {
 	uint32_t ax, dx;
-	
+
 	asm volatile (
 		"rdmsr"
@@ -343,5 +343,5 @@
 		: "c" (msr)
 	);
-	
+
 	return ((uint64_t) dx << 32) | ax;
 }
@@ -360,5 +360,5 @@
 {
 	uintptr_t v;
-	
+
 	asm volatile (
 		"andl %%esp, %[v]\n"
@@ -366,5 +366,5 @@
 		: "0" (~(STACK_SIZE - 1))
 	);
-	
+
 	return v;
 }
Index: kernel/arch/ia32/include/arch/atomic.h
===================================================================
--- kernel/arch/ia32/include/arch/atomic.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia32/include/arch/atomic.h	(revision d5e5fd1214ee9617b9a936d6f09efec4c9a91b48)
@@ -75,5 +75,5 @@
 {
 	atomic_count_t r = 1;
-	
+
 	asm volatile (
 		"lock xaddl %[r], %[count]\n"
@@ -81,5 +81,5 @@
 		  [r] "+r" (r)
 	);
-	
+
 	return r;
 }
@@ -88,5 +88,5 @@
 {
 	atomic_count_t r = -1;
-	
+
 	asm volatile (
 		"lock xaddl %[r], %[count]\n"
@@ -94,5 +94,5 @@
 		  [r] "+r" (r)
 	);
-	
+
 	return r;
 }
@@ -104,5 +104,5 @@
 {
 	atomic_count_t v = 1;
-	
+
 	asm volatile (
 		"xchgl %[v], %[count]\n"
@@ -110,5 +110,5 @@
 		  [count] "+m" (val->count)
 	);
-	
+
 	return v;
 }
@@ -119,5 +119,5 @@
 {
 	atomic_count_t tmp;
-	
+
 	preemption_disable();
 	asm volatile (
@@ -129,5 +129,5 @@
 		"testl %[tmp], %[tmp]\n"
 		"jnz 0b\n"       /* lightweight looping on locked spinlock */
-		
+
 		"incl %[tmp]\n"  /* now use the atomic operation */
 		"xchgl %[count], %[tmp]\n"
@@ -137,5 +137,5 @@
 		  [tmp] "=&r" (tmp)
 	);
-	
+
 	/*
 	 * Prevent critical section code from bleeding out this way up.
Index: kernel/arch/ia32/include/arch/cpu.h
===================================================================
--- kernel/arch/ia32/include/arch/cpu.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia32/include/arch/cpu.h	(revision d5e5fd1214ee9617b9a936d6f09efec4c9a91b48)
@@ -80,5 +80,5 @@
 
 	tss_t *tss;
-	
+
 	size_t iomapver_copy;  /** Copy of TASK's I/O Permission bitmap generation count. */
 } cpu_arch_t;
Index: kernel/arch/ia32/include/arch/cpuid.h
===================================================================
--- kernel/arch/ia32/include/arch/cpuid.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia32/include/arch/cpuid.h	(revision d5e5fd1214ee9617b9a936d6f09efec4c9a91b48)
@@ -83,17 +83,17 @@
 	uint32_t val;
 	uint32_t ret;
-	
+
 	asm volatile (
 		"pushf\n"                      /* read flags */
 		"popl %[ret]\n"
 		"movl %[ret], %[val]\n"
-		
+
 		"xorl %[eflags_id], %[val]\n"  /* swap the ID bit */
-		
+
 		"pushl %[val]\n"               /* propagate the change into flags */
 		"popf\n"
 		"pushf\n"
 		"popl %[val]\n"
-		
+
 		"andl %[eflags_id], %[ret]\n"  /* interrested only in ID bit */
 		"andl %[eflags_id], %[val]\n"
@@ -102,5 +102,5 @@
 		: [eflags_id] "i" (EFLAGS_ID)
 	);
-	
+
 	return ret;
 }
Index: kernel/arch/ia32/include/arch/cycle.h
===================================================================
--- kernel/arch/ia32/include/arch/cycle.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia32/include/arch/cycle.h	(revision d5e5fd1214ee9617b9a936d6f09efec4c9a91b48)
@@ -44,10 +44,10 @@
 #else
 	uint64_t v;
-	
+
 	asm volatile(
 		"rdtsc\n"
 		: "=A" (v)
 	);
-	
+
 	return v;
 #endif
Index: kernel/arch/ia32/include/arch/mm/page.h
===================================================================
--- kernel/arch/ia32/include/arch/mm/page.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia32/include/arch/mm/page.h	(revision d5e5fd1214ee9617b9a936d6f09efec4c9a91b48)
@@ -183,5 +183,5 @@
 {
 	pte_t *p = &pt[i];
-	
+
 	return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT |
 	    (!p->present) << PAGE_PRESENT_SHIFT |
@@ -196,5 +196,5 @@
 {
 	pte_t *p = &pt[i];
-	
+
 	p->page_cache_disable = !(flags & PAGE_CACHEABLE);
 	p->present = !(flags & PAGE_NOT_PRESENT);
@@ -202,5 +202,5 @@
 	p->writeable = (flags & PAGE_WRITE) != 0;
 	p->global = (flags & PAGE_GLOBAL) != 0;
-	
+
 	/*
 	 * Ensure that there is at least one bit set even if the present bit is
Index: kernel/arch/ia32/include/arch/smp/apic.h
===================================================================
--- kernel/arch/ia32/include/arch/smp/apic.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia32/include/arch/smp/apic.h	(revision d5e5fd1214ee9617b9a936d6f09efec4c9a91b48)
@@ -334,5 +334,5 @@
 		} __attribute__ ((packed));
 	};
-	
+
 } __attribute__ ((packed)) io_redirection_reg_t;
 
Index: kernel/arch/ia32/include/arch/smp/smp.h
===================================================================
--- kernel/arch/ia32/include/arch/smp/smp.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia32/include/arch/smp/smp.h	(revision d5e5fd1214ee9617b9a936d6f09efec4c9a91b48)
@@ -43,11 +43,11 @@
 	/** Check whether a processor is enabled. */
 	bool (*cpu_enabled)(size_t);
-	
+
 	/** Check whether a processor is BSP. */
 	bool (*cpu_bootstrap)(size_t);
-	
+
 	/** Return APIC ID of a processor. */
 	uint8_t (*cpu_apic_id)(size_t);
-	
+
 	/** Return mapping between IRQ and APIC pin. */
 	int (*irq_to_pin)(unsigned int);