Changeset d5610b9 in mainline for kernel/arch/arm32/include/arch/mm/page_armv6.h

Timestamp:

2015-10-03T08:37:37Z (9 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

afe5e09

Parents:

8ca6f08

Message:

Cleanup some of the cache maintenance mess on ARM

• Do not define ARMv7 cache maintenance registers for ARMv6-.
• Define missing ARMv6- registers using analoguos naming convention.
• In smc_coherence() and pt_coherence_m(), do not blindly use ARMv7 DCCVMAU but decide the proper type of cache maintenance operation in dcache_clean_mva_pou().
• Also, do not use ARMv7 ICIALLU directly, but call icache_invalidate() instead, which does the right thing.

File:

• kernel/arch/arm32/include/arch/mm/page_armv6.h (modified) (1 diff)

kernel/arch/arm32/include/arch/mm/page_armv6.h

@@ -156 +156 @@
 do { \
         for (unsigned i = 0; i < count; ++i) \
-                DCCMVAU_write((uintptr_t)(pt + i)); \
+                dcache_clean_mva_pou((uintptr_t)(pt + i)); \
         read_barrier(); \
 } while (0)
-
 
 /** Returns level 0 page table entry flags.