Changeset d5610b9 in mainline for kernel/arch/arm32/include/arch/barrier.h

Timestamp:

2015-10-03T08:37:37Z (9 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

afe5e09

Parents:

8ca6f08

Message:

Cleanup some of the cache maintenance mess on ARM

• Do not define ARMv7 cache maintenance registers for ARMv6-.
• Define missing ARMv6- registers using analoguos naming convention.
• In smc_coherence() and pt_coherence_m(), do not blindly use ARMv7 DCCVMAU but decide the proper type of cache maintenance operation in dcache_clean_mva_pou().
• Also, do not use ARMv7 ICIALLU directly, but call icache_invalidate() instead, which does the right thing.

File:

• kernel/arch/arm32/include/arch/barrier.h (modified) (3 diffs)

kernel/arch/arm32/include/arch/barrier.h

@@ -38 +38 @@
 
 #ifdef KERNEL
+#include <arch/cache.h>
 #include <arch/cp15.h>
 #else
@@ -71 +72 @@
  * CP15 implementation is mandatory only for armv6+.
  */
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 #define memory_barrier()  CP15DMB_write(0)
-#define read_barrier()    CP15DSB_write(0)
+#else
+#define memory_barrier()  CP15DSB_write(0)
+#endif
+#define read_barrier()    CP15DSB_write(0) 
 #define write_barrier()   read_barrier()
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 #define inst_barrier()    CP15ISB_write(0)
+#else
+#define inst_barrier()
+#endif
 #else
 /* Older manuals mention syscalls as a way to implement cache coherency and
@@ -103 +112 @@
 
 #if defined PROCESSOR_ARCH_armv7_a | defined PROCESSOR_ARCH_armv6 | defined KERNEL
-/* Available on all supported arms,
- * invalidates entire ICache so the written value does not matter. */
 //TODO might be PL1 only on armv5-
 #define smc_coherence(a) \
 do { \
-        DCCMVAU_write((uint32_t)(a));  /* Flush changed memory */\
+        dcache_clean_mva_pou((uintptr_t) a);\
         write_barrier();               /* Wait for completion */\
-        ICIALLU_write(0);              /* Flush ICache */\
+        icache_invalidate();\
         inst_barrier();                /* Wait for Inst refetch */\
 } while (0)