Index: kernel/arch/arm32/include/barrier.h
===================================================================
--- kernel/arch/arm32/include/barrier.h	(revision e25eca8008c4df6f190fbd28a399c5e01406f863)
+++ kernel/arch/arm32/include/barrier.h	(revision d5087aa3fad89debb05d267f38ebb78362b1e3d2)
@@ -48,4 +48,5 @@
 
 #define smc_coherence(a)
+#define smc_coherence_block(a, l)
 
 #endif
Index: kernel/arch/ia32/include/barrier.h
===================================================================
--- kernel/arch/ia32/include/barrier.h	(revision e25eca8008c4df6f190fbd28a399c5e01406f863)
+++ kernel/arch/ia32/include/barrier.h	(revision d5087aa3fad89debb05d267f38ebb78362b1e3d2)
@@ -92,4 +92,5 @@
  */
 #define smc_coherence(a)		write_barrier()
+#define smc_coherence_block(a, l)	write_barrier()
 
 #endif
Index: kernel/arch/ia64/include/barrier.h
===================================================================
--- kernel/arch/ia64/include/barrier.h	(revision e25eca8008c4df6f190fbd28a399c5e01406f863)
+++ kernel/arch/ia64/include/barrier.h	(revision d5087aa3fad89debb05d267f38ebb78362b1e3d2)
@@ -63,4 +63,14 @@
 }
 
+#define FC_INVAL_MIN		32
+#define smc_coherence_block(a, l)		\
+{						\
+	unsigned long i;			\
+	for (i = 0; i < (l); i += FC_INVAL_MIN)	\
+		fc_i((void *)(a) + i);		\
+	sync_i();				\
+	srlz_i();				\
+}
+
 #endif
 
Index: kernel/arch/mips32/include/barrier.h
===================================================================
--- kernel/arch/mips32/include/barrier.h	(revision e25eca8008c4df6f190fbd28a399c5e01406f863)
+++ kernel/arch/mips32/include/barrier.h	(revision d5087aa3fad89debb05d267f38ebb78362b1e3d2)
@@ -47,4 +47,5 @@
 
 #define smc_coherence(a)
+#define smc_coherence_block(a, l)
 
 #endif
Index: kernel/arch/ppc32/include/barrier.h
===================================================================
--- kernel/arch/ppc32/include/barrier.h	(revision e25eca8008c4df6f190fbd28a399c5e01406f863)
+++ kernel/arch/ppc32/include/barrier.h	(revision d5087aa3fad89debb05d267f38ebb78362b1e3d2)
@@ -44,4 +44,5 @@
 
 #define smc_coherence(a)
+#define smc_coherence_block(a, l)
 
 #endif
Index: kernel/arch/ppc64/include/barrier.h
===================================================================
--- kernel/arch/ppc64/include/barrier.h	(revision e25eca8008c4df6f190fbd28a399c5e01406f863)
+++ kernel/arch/ppc64/include/barrier.h	(revision d5087aa3fad89debb05d267f38ebb78362b1e3d2)
@@ -44,4 +44,5 @@
 
 #define smc_coherence(a)
+#define smc_coherence_block(a, l)
 
 #endif
Index: kernel/arch/sparc64/include/barrier.h
===================================================================
--- kernel/arch/sparc64/include/barrier.h	(revision e25eca8008c4df6f190fbd28a399c5e01406f863)
+++ kernel/arch/sparc64/include/barrier.h	(revision d5087aa3fad89debb05d267f38ebb78362b1e3d2)
@@ -58,8 +58,6 @@
 	asm volatile ("membar #StoreStore\n" ::: "memory")
 
-static inline void flush(uintptr_t addr)
-{
-	asm volatile ("flush %0\n" :: "r" (addr) : "memory");
-}
+#define flush(a)		\
+	asm volatile ("flush %0\n" :: "r" ((a)) : "memory")
 
 /** Flush Instruction Memory instruction. */
@@ -91,4 +89,13 @@
 }
 
+#define FLUSH_INVAL_MIN		4
+#define smc_coherence_block(a, l)			\
+{							\
+	unsigned long i;				\
+	write_barrier();				\
+	for (i = 0; i < (l); i += FLUSH_INVAL_MIN)	\
+		flush((void *)(a) + i);			\
+}
+
 #endif