Index: kernel/arch/sparc64/include/drivers/pci.h
===================================================================
--- kernel/arch/sparc64/include/drivers/pci.h	(revision be544eff37120af56b1fe3114d2c775d92a06402)
+++ kernel/arch/sparc64/include/drivers/pci.h	(revision d4f184fc3eab318514b0d31443d56f409ea3bcd4)
@@ -47,5 +47,6 @@
 enum pci_model {
 	PCI_UNKNOWN,
-	PCI_SABRE
+	PCI_SABRE,
+	PCI_PSYCHO
 };
 
Index: kernel/arch/sparc64/src/drivers/pci.c
===================================================================
--- kernel/arch/sparc64/src/drivers/pci.c	(revision be544eff37120af56b1fe3114d2c775d92a06402)
+++ kernel/arch/sparc64/src/drivers/pci.c	(revision d4f184fc3eab318514b0d31443d56f409ea3bcd4)
@@ -52,7 +52,16 @@
 #define PCI_SABRE_ICLR_BASE	0x300
 
+#define PCI_PSYCHO_REGS_REG	2	
+
+#define PCI_PSYCHO_IMAP_BASE	0x200
+#define PCI_PSYCHO_ICLR_BASE	0x300	
+
 static pci_t *pci_sabre_init(ofw_tree_node_t *node);
 static void pci_sabre_enable_interrupt(pci_t *pci, int inr);
 static void pci_sabre_clear_interrupt(pci_t *pci, int inr);
+
+static pci_t *pci_psycho_init(ofw_tree_node_t *node);
+static void pci_psycho_enable_interrupt(pci_t *pci, int inr);
+static void pci_psycho_clear_interrupt(pci_t *pci, int inr);
 
 /** PCI operations for Sabre model. */
@@ -61,6 +70,16 @@
 	.clear_interrupt = pci_sabre_clear_interrupt
 };
-
-/** Initialize PCI controller (model Sabre). */
+/** PCI operations for Psycho model. */
+static pci_operations_t pci_psycho_ops = {
+	.enable_interrupt = pci_psycho_enable_interrupt,
+	.clear_interrupt = pci_psycho_clear_interrupt
+};
+
+/** Initialize PCI controller (model Sabre).
+ *
+ * @param node OpenFirmware device tree node of the Sabre.
+ *
+ * @return Address of the initialized PCI structure.
+ */ 
 pci_t *pci_sabre_init(ofw_tree_node_t *node)
 {
@@ -96,4 +115,44 @@
 }
 
+
+/** Initialize the Psycho PCI controller.
+ *
+ * @param node OpenFirmware device tree node of the Psycho.
+ *
+ * @return Address of the initialized PCI structure.
+ */ 
+pci_t *pci_psycho_init(ofw_tree_node_t *node)
+{
+	pci_t *pci;
+	ofw_tree_property_t *prop;
+
+	/*
+	 * Get registers.
+	 */
+	prop = ofw_tree_getprop(node, "reg");
+	if (!prop || !prop->value)
+		return NULL;
+
+	ofw_upa_reg_t *reg = prop->value;
+	count_t regs = prop->size / sizeof(ofw_upa_reg_t);
+
+	if (regs < PCI_PSYCHO_REGS_REG + 1)
+		return NULL;
+
+	uintptr_t paddr;
+	if (!ofw_upa_apply_ranges(node->parent, &reg[PCI_PSYCHO_REGS_REG], &paddr))
+		return NULL;
+
+	pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
+	if (!pci)
+		return NULL;
+
+	pci->model = PCI_PSYCHO;
+	pci->op = &pci_psycho_ops;
+	pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_PSYCHO_REGS_REG].size);
+
+	return pci;
+}
+
 void pci_sabre_enable_interrupt(pci_t *pci, int inr)
 {
@@ -104,4 +163,14 @@
 {
 	pci->reg[PCI_SABRE_ICLR_BASE + (inr & INO_MASK)] = 0;
+}
+
+void pci_psycho_enable_interrupt(pci_t *pci, int inr)
+{
+	pci->reg[PCI_PSYCHO_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK;
+}
+
+void pci_psycho_clear_interrupt(pci_t *pci, int inr)
+{
+	pci->reg[PCI_PSYCHO_ICLR_BASE + (inr & INO_MASK)] = 0;
 }
 
@@ -129,4 +198,11 @@
 		 */
 		return pci_sabre_init(node);
+	} else if (strcmp(prop->value, "SUNW,psycho") == 0) {
+		/*
+		 * PCI controller Psycho.
+		 * Used on UltraSPARC II based processors, for instance,
+		 * on Ultra 60.
+		 */
+		return pci_psycho_init(node);
 	} else {
 		/*