Changeset d3dd96e in mainline
- Timestamp:
- 2013-12-30T02:10:18Z (11 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- f5bfd98
- Parents:
- 2fd16b93
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/bus/usb/ehci/res.c
r2fd16b93 rd3dd96e 46 46 47 47 #include "res.h" 48 49 #define HCC_PARAMS_OFFSET 0x8 50 #define HCC_PARAMS_EECP_MASK 0xff 51 #define HCC_PARAMS_EECP_OFFSET 8 52 53 #define CMD_OFFSET 0x0 54 #define STS_OFFSET 0x4 55 #define INT_OFFSET 0x8 56 #define CFG_OFFSET 0x40 57 58 #define USBCMD_RUN 1 59 #define USBSTS_HALTED (1 << 12) 48 #include "ehci_regs.h" 60 49 61 50 #define USBLEGSUP_OFFSET 0 … … 189 178 usb_log_debug2("Registers mapped at: %p.\n", regs); 190 179 191 const uint32_t hcc_params = 192 *(uint32_t*)(regs + HCC_PARAMS_OFFSET); 180 ehci_caps_regs_t *ehci_caps = regs; 181 182 const uint32_t hcc_params = EHCI_RD(ehci_caps->hccparams); 193 183 usb_log_debug("Value of hcc params register: %x.\n", hcc_params); 194 184 … … 196 186 * position of EEC registers (points to PCI config space) */ 197 187 const uint32_t eecp = 198 (hcc_params >> HCC_PARAMS_EECP_OFFSET) & HCC_PARAMS_EECP_MASK;188 (hcc_params >> EHCI_CAPS_HCC_EECP_SHIFT) & EHCI_CAPS_HCC_EECP_MASK; 199 189 usb_log_debug("Value of EECP: %x.\n", eecp); 200 190 … … 212 202 213 203 /* Get size of capability registers in memory space. */ 214 const unsigned operation_offset = *(uint8_t*)regs;204 const unsigned operation_offset = EHCI_RD8(ehci_caps->caplength); 215 205 usb_log_debug("USBCMD offset: %d.\n", operation_offset); 216 206 217 /* Zero USBCMD register. */ 218 volatile uint32_t *usbcmd = 219 (uint32_t*)((uint8_t*)regs + operation_offset + CMD_OFFSET); 220 volatile uint32_t *usbsts = 221 (uint32_t*)((uint8_t*)regs + operation_offset + STS_OFFSET); 222 volatile uint32_t *usbconf = 223 (uint32_t*)((uint8_t*)regs + operation_offset + CFG_OFFSET); 224 volatile uint32_t *usbint = 225 (uint32_t*)((uint8_t*)regs + operation_offset + INT_OFFSET); 226 usb_log_debug("USBCMD value: %x.\n", *usbcmd); 227 if (*usbcmd & USBCMD_RUN) { 228 *usbsts = 0x3f; /* ack all interrupts */ 229 *usbint = 0; /* disable all interrupts */ 230 *usbconf = 0; /* release control of RH ports */ 231 232 *usbcmd = 0; 207 ehci_regs_t *ehci_regs = regs + operation_offset; 208 209 usb_log_debug("USBCMD value: %x.\n", EHCI_RD(ehci_regs->usbcmd)); 210 if (EHCI_RD(ehci_regs->usbcmd) & USB_CMD_RUN_FLAG) { 211 EHCI_WR(ehci_regs->usbintr, 0); /* disable all interrupts */ 212 EHCI_WR(ehci_regs->usbsts, 0x3f); /* ack all interrupts */ 213 EHCI_WR(ehci_regs->configflag, 0); /* release RH ports */ 214 EHCI_WR(ehci_regs->usbcmd, 0); 233 215 /* Wait until hc is halted */ 234 while (( *usbsts & USBSTS_HALTED) == 0);216 while ((EHCI_RD(ehci_regs->usbsts) & USB_STS_HC_HALTED_FLAG) == 0); 235 217 usb_log_info("EHCI turned off.\n"); 236 218 } else { … … 242 224 "\t USBINT(%p): %x(0x0 = no interrupts).\n" 243 225 "\t CONFIG(%p): %x(0x0 = ports controlled by companion hc).\n", 244 usbcmd, *usbcmd, usbsts, *usbsts, usbint, *usbint, usbconf,*usbconf); 226 &ehci_regs->usbcmd, EHCI_RD(ehci_regs->usbcmd), 227 &ehci_regs->usbsts, EHCI_RD(ehci_regs->usbsts), 228 &ehci_regs->usbintr, EHCI_RD(ehci_regs->usbintr), 229 &ehci_regs->configflag, EHCI_RD(ehci_regs->configflag)); 245 230 246 231 return ret;
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