Index: arch/ia32/include/smp/apic.h
===================================================================
--- arch/ia32/include/smp/apic.h	(revision 457d18ab5e0f7c0463835d670622bae2fc50be71)
+++ arch/ia32/include/smp/apic.h	(revision d0780b4c5091872c808a02941fb7b5bb5e5276d1)
@@ -152,5 +152,12 @@
 /* Task Priority Register */
 #define TPR		(0x080/sizeof(__u32))
-#define TPRClear	0xffffff00
+union tpr {
+	__u32 value;
+	struct {
+		unsigned pri_sc : 4;		/**< Task Priority Sub-Class. */
+		unsigned pri : 4;		/**< Task Priority. */
+	} __attribute__ ((packed));
+};
+typedef union tpr tpr_t;
 
 /** Spurious-Interrupt Vector Register. */
@@ -159,7 +166,7 @@
 	__u32 value;
 	struct {
-		__u8 vector;			/**< Spurious Vector */
-		unsigned lapic_enabled : 1;	/**< APIC Software Enable/Disable */
-		unsigned focus_checking : 1;	/**< Focus Processor Checking */
+		__u8 vector;			/**< Spurious Vector. */
+		unsigned lapic_enabled : 1;	/**< APIC Software Enable/Disable. */
+		unsigned focus_checking : 1;	/**< Focus Processor Checking. */
 		unsigned : 22;			/**< Reserved. */
 	} __attribute__ ((packed));
Index: arch/ia32/src/smp/apic.c
===================================================================
--- arch/ia32/src/smp/apic.c	(revision 457d18ab5e0f7c0463835d670622bae2fc50be71)
+++ arch/ia32/src/smp/apic.c	(revision d0780b4c5091872c808a02941fb7b5bb5e5276d1)
@@ -45,5 +45,5 @@
  * Advanced Programmable Interrupt Controller for SMP systems.
  * Tested on:
- *	Bochs 2.0.2 - Bochs 2.2.5 with 2-8 CPUs
+ *	Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
  *	Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
  *	VMware Workstation 5.5 with 2 CPUs
@@ -309,4 +309,5 @@
 	lvt_error_t error;
 	lvt_lint_t lint;
+	tpr_t tpr;
 	svr_t svr;
 	icr_t icr;
@@ -331,4 +332,10 @@
 	lint.masked = true;
 	l_apic[LVT_LINT1] = lint.value;
+
+	/* Task Priority Register initialization. */
+	tpr.value = l_apic[TPR];
+	tpr.pri_sc = 0;
+	tpr.pri = 0;
+	l_apic[TPR] = tpr.value;
 	
 	/* Spurious-Interrupt Vector Register initialization. */
@@ -336,7 +343,6 @@
 	svr.vector = VECTOR_APIC_SPUR;
 	svr.lapic_enabled = true;
+	svr.focus_checking = true;
 	l_apic[SVR] = svr.value;
-
-	l_apic[TPR] &= TPRClear;
 
 	if (CPU->arch.family >= 6)
Index: doc/arch/amd64
===================================================================
--- doc/arch/amd64	(revision 457d18ab5e0f7c0463835d670622bae2fc50be71)
+++ doc/arch/amd64	(revision d0780b4c5091872c808a02941fb7b5bb5e5276d1)
@@ -16,5 +16,5 @@
 
 SMP COMPATIBILITY
-        o Bochs 2.2.1
+        o Bochs 2.2.1 - 2.2.6
                 o 2x-8x AMD64 CPU
         o Simics 2.2.19
Index: doc/arch/ia32
===================================================================
--- doc/arch/ia32	(revision 457d18ab5e0f7c0463835d670622bae2fc50be71)
+++ doc/arch/ia32	(revision d0780b4c5091872c808a02941fb7b5bb5e5276d1)
@@ -17,5 +17,5 @@
 
 SMP COMPATIBILITY
-        o Bochs 2.0.2 - Bochs 2.2.5
+        o Bochs 2.0.2 - Bochs 2.2.6
                 o 2x-8x 686 CPU
         o Simics 2.0.28 - Simics 2.2.19