Index: arch/ia64/src/mm/tlb.c
===================================================================
--- arch/ia64/src/mm/tlb.c	(revision 9faddb3ab7b9a03107b9a6b1b515a42a97e050dc)
+++ arch/ia64/src/mm/tlb.c	(revision cfad878ac84e70dde6b1c1a70cbccb3534be5830)
@@ -39,4 +39,6 @@
 #include <arch/barrier.h>
 #include <arch/interrupt.h>
+#include <arch/pal/pal.h>
+#include <arch/asm.h>
 #include <typedefs.h>
 #include <panic.h>
@@ -46,5 +48,36 @@
 void tlb_invalidate_all(void)
 {
-	/* TODO */
+		__address adr;
+		__u32 count1,count2,stride1,stride2;
+		
+		int i,j;
+		
+		adr=PAL_PTCE_INFO_BASE();
+		count1=PAL_PTCE_INFO_COUNT1();
+		count2=PAL_PTCE_INFO_COUNT2();
+		stride1=PAL_PTCE_INFO_STRIDE1();
+		stride2=PAL_PTCE_INFO_STRIDE2();
+		
+		interrupts_disable();
+
+		for(i=0;i<count1;i++)
+		{
+			for(j=0;j<count2;j++)
+			{
+				asm volatile
+				(
+					"ptc.e %0;;"
+					:
+					:"r" (adr)
+				);
+				adr+=stride2;
+			}
+			adr+=stride1;
+		}
+
+		interrupts_enable();
+
+		srlz_d();
+		srlz_i();
 }