Index: kernel/arch/abs32le/src/abs32le.c
===================================================================
--- kernel/arch/abs32le/src/abs32le.c	(revision 07c913b7957f3c0dc58289db4a7542e11eb4ffd4)
+++ kernel/arch/abs32le/src/abs32le.c	(revision cf3aee195010da61f58b4c6e8daa8d03620c0a4e)
@@ -69,5 +69,5 @@
 }
 
-void arch_post_cpu_init()
+void arch_post_cpu_init(void)
 {
 }
Index: kernel/arch/amd64/include/arch/asm.h
===================================================================
--- kernel/arch/amd64/include/arch/asm.h	(revision 07c913b7957f3c0dc58289db4a7542e11eb4ffd4)
+++ kernel/arch/amd64/include/arch/asm.h	(revision cf3aee195010da61f58b4c6e8daa8d03620c0a4e)
@@ -339,5 +339,5 @@
  *
  */
-NO_TRACE static inline void enable_l_apic_in_msr()
+NO_TRACE static inline void enable_l_apic_in_msr(void)
 {
 	asm volatile (
Index: kernel/arch/amd64/src/fpu_context.c
===================================================================
--- kernel/arch/amd64/src/fpu_context.c	(revision 07c913b7957f3c0dc58289db4a7542e11eb4ffd4)
+++ kernel/arch/amd64/src/fpu_context.c	(revision cf3aee195010da61f58b4c6e8daa8d03620c0a4e)
@@ -54,5 +54,5 @@
 }
 
-void fpu_init()
+void fpu_init(void)
 {
 	/* TODO: Zero all SSE, MMX etc. registers */
Index: kernel/arch/arm32/include/arch/cp15.h
===================================================================
--- kernel/arch/arm32/include/arch/cp15.h	(revision 07c913b7957f3c0dc58289db4a7542e11eb4ffd4)
+++ kernel/arch/arm32/include/arch/cp15.h	(revision cf3aee195010da61f58b4c6e8daa8d03620c0a4e)
@@ -47,5 +47,5 @@
 
 #define CONTROL_REG_GEN_READ(name, crn, opc1, crm, opc2) \
-static inline uint32_t name##_read() \
+static inline uint32_t name##_read(void) \
 { \
 	uint32_t val; \
Index: kernel/arch/arm32/include/arch/security_ext.h
===================================================================
--- kernel/arch/arm32/include/arch/security_ext.h	(revision 07c913b7957f3c0dc58289db4a7542e11eb4ffd4)
+++ kernel/arch/arm32/include/arch/security_ext.h	(revision cf3aee195010da61f58b4c6e8daa8d03620c0a4e)
@@ -46,5 +46,5 @@
  * older archs.
  */
-static inline bool sec_ext_is_implemented()
+static inline bool sec_ext_is_implemented(void)
 {
 #ifdef PROCESSOR_ARCH_armv7_a
@@ -60,5 +60,5 @@
  * mode.
  */
-static inline bool sec_ext_is_monitor_mode()
+static inline bool sec_ext_is_monitor_mode(void)
 {
 	return (current_status_reg_read() & MODE_MASK) == MONITOR_MODE;
@@ -75,5 +75,5 @@
  * Look for 'secureworld_exit' in arch/arm/cpu/armv7/omap3/board.c.
  */
-static inline bool sec_ext_is_secure()
+static inline bool sec_ext_is_secure(void)
 {
 	return sec_ext_is_implemented()
Index: kernel/arch/arm32/src/arm32.c
===================================================================
--- kernel/arch/arm32/src/arm32.c	(revision 07c913b7957f3c0dc58289db4a7542e11eb4ffd4)
+++ kernel/arch/arm32/src/arm32.c	(revision cf3aee195010da61f58b4c6e8daa8d03620c0a4e)
@@ -158,5 +158,5 @@
 
 /** Reboot. */
-void arch_reboot()
+void arch_reboot(void)
 {
 	/* not implemented */
Index: kernel/arch/arm32/src/fpu_context.c
===================================================================
--- kernel/arch/arm32/src/fpu_context.c	(revision 07c913b7957f3c0dc58289db4a7542e11eb4ffd4)
+++ kernel/arch/arm32/src/fpu_context.c	(revision cf3aee195010da61f58b4c6e8daa8d03620c0a4e)
@@ -101,4 +101,5 @@
 	FPSCR_EN_ALL = FPSCR_DENORMAL_EN_FLAG | FPSCR_INEXACT_EN_FLAG | FPSCR_UNDERFLOW_EN_FLAG | FPSCR_OVERFLOW_EN_FLAG | FPSCR_ZERO_DIV_EN_FLAG | FPSCR_INVALID_OP_EN_FLAG,
 };
+
 extern uint32_t fpscr_read(void);
 extern void fpscr_write(uint32_t);
@@ -114,7 +115,8 @@
 static void (*restore_context)(fpu_context_t *ctx);
 
-static int fpu_have_coprocessor_access()
-{
-/* The register containing the information (CPACR) is not available on armv6-
+static int fpu_have_coprocessor_access(void)
+{
+/*
+ * The register containing the information (CPACR) is not available on armv6-
  * rely on user decision to use CONFIG_FPU.
  */
@@ -143,7 +145,8 @@
  * @note do we need to call secure monitor here?
  */
-static void fpu_enable_coprocessor_access()
-{
-/* The register containing the information (CPACR) is not available on armv6-
+static void fpu_enable_coprocessor_access(void)
+{
+/*
+ * The register containing the information (CPACR) is not available on armv6-
  * rely on user decision to use CONFIG_FPU.
  */
Index: kernel/arch/ia32/src/fpu_context.c
===================================================================
--- kernel/arch/ia32/src/fpu_context.c	(revision 07c913b7957f3c0dc58289db4a7542e11eb4ffd4)
+++ kernel/arch/ia32/src/fpu_context.c	(revision cf3aee195010da61f58b4c6e8daa8d03620c0a4e)
@@ -125,5 +125,5 @@
 
 /** Initialize x87 FPU. Mask all exceptions. */
-void fpu_init()
+void fpu_init(void)
 {
 	uint32_t help0 = 0;
Index: kernel/arch/ia64/src/mm/vhpt.c
===================================================================
--- kernel/arch/ia64/src/mm/vhpt.c	(revision 07c913b7957f3c0dc58289db4a7542e11eb4ffd4)
+++ kernel/arch/ia64/src/mm/vhpt.c	(revision cf3aee195010da61f58b4c6e8daa8d03620c0a4e)
@@ -82,5 +82,5 @@
 }
 
-void vhpt_invalidate_all()
+void vhpt_invalidate_all(void)
 {
 	memsetb(vhpt_base, VHPT_SIZE, 0);
Index: kernel/arch/mips32/src/debugger.c
===================================================================
--- kernel/arch/mips32/src/debugger.c	(revision 07c913b7957f3c0dc58289db4a7542e11eb4ffd4)
+++ kernel/arch/mips32/src/debugger.c	(revision cf3aee195010da61f58b4c6e8daa8d03620c0a4e)
@@ -288,5 +288,5 @@
  *
  */
-void debugger_init()
+void debugger_init(void)
 {
 	unsigned int i;
Index: kernel/arch/mips32/src/fpu_context.c
===================================================================
--- kernel/arch/mips32/src/fpu_context.c	(revision 07c913b7957f3c0dc58289db4a7542e11eb4ffd4)
+++ kernel/arch/mips32/src/fpu_context.c	(revision cf3aee195010da61f58b4c6e8daa8d03620c0a4e)
@@ -53,5 +53,5 @@
 }
 
-void fpu_init()
+void fpu_init(void)
 {
 	/* TODO: Zero all registers */
Index: kernel/arch/sparc32/src/sparc32.c
===================================================================
--- kernel/arch/sparc32/src/sparc32.c	(revision 07c913b7957f3c0dc58289db4a7542e11eb4ffd4)
+++ kernel/arch/sparc32/src/sparc32.c	(revision cf3aee195010da61f58b4c6e8daa8d03620c0a4e)
@@ -96,5 +96,5 @@
 
 
-void arch_post_cpu_init()
+void arch_post_cpu_init(void)
 {
 }