Changeset ce890ec9 in mainline
- Timestamp:
- 2010-09-02T19:54:37Z (14 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 23c8be7f
- Parents:
- 7b213f2
- Location:
- kernel/arch/mips32
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/mips32/include/exception.h
r7b213f2 rce890ec9 79 79 uint32_t t6; 80 80 uint32_t t7; 81 uint32_t s0 82 uint32_t s1 83 uint32_t s2 84 uint32_t s3 85 uint32_t s4 86 uint32_t s5 87 uint32_t s6 88 uint32_t s7 81 uint32_t s0; 82 uint32_t s1; 83 uint32_t s2; 84 uint32_t s3; 85 uint32_t s4; 86 uint32_t s5; 87 uint32_t s6; 88 uint32_t s7; 89 89 uint32_t t8; 90 90 uint32_t t9; -
kernel/arch/mips32/src/exception.c
r7b213f2 rce890ec9 83 83 printf("lo=%p\thi=%p\t\n", istate->lo, istate->hi); 84 84 printf("cp0_status=%p\tcp0_epc=%p\tk1=%p\n", 85 istate->status, istate->epc, istate->k 1);85 istate->status, istate->epc, istate->kt1); 86 86 } 87 87 … … 97 97 ASSERT(THREAD); 98 98 istate->epc += 4; 99 istate->v1 = istate->k 1;99 istate->v1 = istate->kt1; 100 100 } else 101 101 unhandled_exception(n, istate); -
kernel/arch/mips32/src/start.S
r7b213f2 rce890ec9 46 46 47 47 /* 48 * Which status bits shouldare thread-local:48 * Which status bits are thread-local: 49 49 * KSU(UM), EXL, ERL, IE 50 50 */ … … 97 97 */ 98 98 .macro REGISTERS_STORE_AND_EXC_RESET r 99 sw $at, EOFFSET_AT(\r)100 sw $v0, EOFFSET_V0(\r)101 sw $v1, EOFFSET_V1(\r)102 sw $a0, EOFFSET_A0(\r)103 sw $a1, EOFFSET_A1(\r)104 sw $a2, EOFFSET_A2(\r)105 sw $a3, EOFFSET_A3(\r)106 sw $t0, EOFFSET_T0(\r)107 sw $t1, EOFFSET_T1(\r)108 sw $t2, EOFFSET_T2(\r)109 sw $t3, EOFFSET_T3(\r)110 sw $t4, EOFFSET_T4(\r)111 sw $t5, EOFFSET_T5(\r)112 sw $t6, EOFFSET_T6(\r)113 sw $t7, EOFFSET_T7(\r)114 sw $t8, EOFFSET_T8(\r)115 sw $t9, EOFFSET_T9(\r)99 sw $at, ISTATE_OFFSET_AT(\r) 100 sw $v0, ISTATE_OFFSET_V0(\r) 101 sw $v1, ISTATE_OFFSET_V1(\r) 102 sw $a0, ISTATE_OFFSET_A0(\r) 103 sw $a1, ISTATE_OFFSET_A1(\r) 104 sw $a2, ISTATE_OFFSET_A2(\r) 105 sw $a3, ISTATE_OFFSET_A3(\r) 106 sw $t0, ISTATE_OFFSET_T0(\r) 107 sw $t1, ISTATE_OFFSET_T1(\r) 108 sw $t2, ISTATE_OFFSET_T2(\r) 109 sw $t3, ISTATE_OFFSET_T3(\r) 110 sw $t4, ISTATE_OFFSET_T4(\r) 111 sw $t5, ISTATE_OFFSET_T5(\r) 112 sw $t6, ISTATE_OFFSET_T6(\r) 113 sw $t7, ISTATE_OFFSET_T7(\r) 114 sw $t8, ISTATE_OFFSET_T8(\r) 115 sw $t9, ISTATE_OFFSET_T9(\r) 116 116 117 117 mflo $at 118 sw $at, EOFFSET_LO(\r)118 sw $at, ISTATE_OFFSET_LO(\r) 119 119 mfhi $at 120 sw $at, EOFFSET_HI(\r)121 122 sw $gp, EOFFSET_GP(\r)123 sw $ra, EOFFSET_RA(\r)124 sw $k1, EOFFSET_K1(\r)120 sw $at, ISTATE_OFFSET_HI(\r) 121 122 sw $gp, ISTATE_OFFSET_GP(\r) 123 sw $ra, ISTATE_OFFSET_RA(\r) 124 sw $k1, ISTATE_OFFSET_KT1(\r) 125 125 126 126 mfc0 $t0, $status … … 134 134 and $t0, $t0, $t3 135 135 136 sw $t2, EOFFSET_STATUS(\r)137 sw $t1, EOFFSET_EPC(\r)136 sw $t2, ISTATE_OFFSET_STATUS(\r) 137 sw $t1, ISTATE_OFFSET_EPC(\r) 138 138 mtc0 $t0, $status 139 139 .endm … … 145 145 */ 146 146 mfc0 $t0, $status 147 lw $t1, EOFFSET_STATUS(\r)147 lw $t1, ISTATE_OFFSET_STATUS(\r) 148 148 149 149 /* mask UM, EXL, ERL, IE */ … … 155 155 mtc0 $t0, $status 156 156 157 lw $v0, EOFFSET_V0(\r)158 lw $v1, EOFFSET_V1(\r)159 lw $a0, EOFFSET_A0(\r)160 lw $a1, EOFFSET_A1(\r)161 lw $a2, EOFFSET_A2(\r)162 lw $a3, EOFFSET_A3(\r)163 lw $t0, EOFFSET_T0(\r)164 lw $t1, EOFFSET_T1(\r)165 lw $t2, EOFFSET_T2(\r)166 lw $t3, EOFFSET_T3(\r)167 lw $t4, EOFFSET_T4(\r)168 lw $t5, EOFFSET_T5(\r)169 lw $t6, EOFFSET_T6(\r)170 lw $t7, EOFFSET_T7(\r)171 lw $t8, EOFFSET_T8(\r)172 lw $t9, EOFFSET_T9(\r)173 174 lw $gp, EOFFSET_GP(\r)175 lw $ra, EOFFSET_RA(\r)176 lw $k1, EOFFSET_K1(\r)177 178 lw $at, EOFFSET_LO(\r)157 lw $v0, ISTATE_OFFSET_V0(\r) 158 lw $v1, ISTATE_OFFSET_V1(\r) 159 lw $a0, ISTATE_OFFSET_A0(\r) 160 lw $a1, ISTATE_OFFSET_A1(\r) 161 lw $a2, ISTATE_OFFSET_A2(\r) 162 lw $a3, ISTATE_OFFSET_A3(\r) 163 lw $t0, ISTATE_OFFSET_T0(\r) 164 lw $t1, ISTATE_OFFSET_T1(\r) 165 lw $t2, ISTATE_OFFSET_T2(\r) 166 lw $t3, ISTATE_OFFSET_T3(\r) 167 lw $t4, ISTATE_OFFSET_T4(\r) 168 lw $t5, ISTATE_OFFSET_T5(\r) 169 lw $t6, ISTATE_OFFSET_T6(\r) 170 lw $t7, ISTATE_OFFSET_T7(\r) 171 lw $t8, ISTATE_OFFSET_T8(\r) 172 lw $t9, ISTATE_OFFSET_T9(\r) 173 174 lw $gp, ISTATE_OFFSET_GP(\r) 175 lw $ra, ISTATE_OFFSET_RA(\r) 176 lw $k1, ISTATE_OFFSET_KT1(\r) 177 178 lw $at, ISTATE_OFFSET_LO(\r) 179 179 mtlo $at 180 lw $at, EOFFSET_HI(\r)180 lw $at, ISTATE_OFFSET_HI(\r) 181 181 mthi $at 182 182 183 lw $at, EOFFSET_EPC(\r)183 lw $at, ISTATE_OFFSET_EPC(\r) 184 184 mtc0 $at, $epc 185 185 186 lw $at, EOFFSET_AT(\r)187 lw $sp, EOFFSET_SP(\r)186 lw $at, ISTATE_OFFSET_AT(\r) 187 lw $sp, ISTATE_OFFSET_SP(\r) 188 188 .endm 189 189 … … 198 198 199 199 beq $k0, $0, 1f 200 add $k0, $sp, 0200 move $k0, $sp 201 201 202 202 /* move $k0 pointer to kernel stack */ … … 205 205 206 206 /* move $k0 (supervisor_sp) */ 207 lw $k0, 0($k0)207 lw $k0, ($k0) 208 208 209 209 1: … … 266 266 /* the $sp is automatically restored to former value */ 267 267 eret 268 269 #define SS_SP EOFFSET_SP270 #define SS_STATUS EOFFSET_STATUS271 #define SS_EPC EOFFSET_EPC272 #define SS_K1 EOFFSET_K1273 268 274 269 /** Syscall entry … … 291 286 mfc0 $t3, $epc 292 287 mfc0 $t2, $status 293 sw $t3, SS_EPC($sp) /* save EPC */294 sw $k1, SS_K1($sp)/* save $k1 not saved on context switch */288 sw $t3, ISTATE_OFFSET_EPC($sp) /* save EPC */ 289 sw $k1, ISTATE_OFFSET_KT1($sp) /* save $k1 not saved on context switch */ 295 290 296 291 and $t4, $t2, REG_SAVE_MASK /* save only KSU, EXL, ERL, IE */ … … 299 294 ori $t2, $t2, 0x1 /* set IE */ 300 295 301 sw $t4, SS_STATUS($sp)296 sw $t4, ISTATE_OFFSET_STATUS($sp) 302 297 mtc0 $t2, $status 303 298 304 299 /* 305 300 * Call the higher level system call handler. 306 * We are going to reuse part of the unused exception stack frame.307 301 * 308 302 */ 309 sw $t0, STACK_ARG4($sp) /* save the 5th argument on the stack */310 sw $t1, STACK_ARG5($sp) /* save the 6th argument on the stack */303 sw $t0, ISTATE_OFFSET_T0($sp) /* save the 5th argument on the stack */ 304 sw $t1, ISTATE_OFFSET_T1($sp) /* save the 6th argument on the stack */ 311 305 jal syscall_handler 312 sw $v0, STACK_ARG6($sp) /* save the syscall number on the stack */306 sw $v0, ISTATE_OFFSET_V0($sp) /* save the syscall number on the stack */ 313 307 314 308 /* restore status */ 315 309 mfc0 $t2, $status 316 lw $t3, SS_STATUS($sp)310 lw $t3, ISTATE_OFFSET_STATUS($sp) 317 311 318 312 /* … … 327 321 328 322 /* restore epc + 4 */ 329 lw $t2, SS_EPC($sp)330 lw $k1, SS_K1($sp)323 lw $t2, ISTATE_OFFSET_EPC($sp) 324 lw $k1, ISTATE_OFFSET_KT1($sp) 331 325 addi $t2, $t2, 4 332 326 mtc0 $t2, $epc 333 327 334 lw $sp, SS_SP($sp) /* restore $sp */328 lw $sp, ISTATE_OFFSET_SP($sp) /* restore $sp */ 335 329 eret 336 330 337 331 tlb_refill_handler: 338 332 KERNEL_STACK_TO_K0 339 sub $k0, REGISTER_SPACE333 sub $k0, ISTATE_SOFT_SIZE 340 334 REGISTERS_STORE_AND_EXC_RESET $k0 341 sw $sp, EOFFSET_SP($k0)342 add $sp, $k0,0335 sw $sp, ISTATE_OFFSET_SP($k0) 336 move $sp, $k0 343 337 344 338 jal tlb_refill 345 add $a0, $sp, 0339 move $a0, $sp 346 340 347 341 REGISTERS_LOAD $sp … … 350 344 cache_error_handler: 351 345 KERNEL_STACK_TO_K0 352 sub $k0, REGISTER_SPACE346 sub $k0, ISTATE_SOFT_SIZE 353 347 REGISTERS_STORE_AND_EXC_RESET $k0 354 sw $sp, EOFFSET_SP($k0)355 add $sp, $k0,0348 sw $sp, ISTATE_OFFSET_SP($k0) 349 move $sp, $k0 356 350 357 351 jal cache_error 358 add $a0, $sp, 0352 move $a0, $sp 359 353 360 354 REGISTERS_LOAD $sp
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