Index: kernel/arch/sparc64/include/arch/mm/sun4v/tlb.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4v/tlb.h	(revision aef669be8dd7a8d097d3e2f786ba26f90cf761fd)
+++ kernel/arch/sparc64/include/arch/mm/sun4v/tlb.h	(revision cade9c1cbd4f94b59da9f4de3a18874d30dcbb38)
@@ -141,7 +141,7 @@
 }
 
-extern void fast_instruction_access_mmu_miss(sysarg_t, istate_t *);
-extern void fast_data_access_mmu_miss(sysarg_t, istate_t *);
-extern void fast_data_access_protection(sysarg_t, istate_t *);
+extern void fast_instruction_access_mmu_miss(unsigned int, istate_t *);
+extern void fast_data_access_mmu_miss(unsigned int, istate_t *);
+extern void fast_data_access_protection(unsigned int, istate_t *);
 
 extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);
Index: kernel/arch/sparc64/include/arch/trap/sun4v/interrupt.h
===================================================================
--- kernel/arch/sparc64/include/arch/trap/sun4v/interrupt.h	(revision aef669be8dd7a8d097d3e2f786ba26f90cf761fd)
+++ kernel/arch/sparc64/include/arch/trap/sun4v/interrupt.h	(revision cade9c1cbd4f94b59da9f4de3a18874d30dcbb38)
@@ -40,6 +40,8 @@
 #ifndef __ASM__
 
+#include <arch/istate_struct.h>
+
 extern void sun4v_ipi_init(void);
-extern void cpu_mondo(void);
+extern void cpu_mondo(unsigned int, istate_t *);
 
 #endif
Index: kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h
===================================================================
--- kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h	(revision aef669be8dd7a8d097d3e2f786ba26f90cf761fd)
+++ kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h	(revision cade9c1cbd4f94b59da9f4de3a18874d30dcbb38)
@@ -73,5 +73,7 @@
 
 .macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
-	PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
+	mov TT_FAST_INSTRUCTION_ACCESS_MMU_MISS, %g2
+	clr %g5		! XXX
+	PREEMPTIBLE_HANDLER exc_dispatch 
 .endm
 
@@ -123,7 +125,7 @@
 	 * mapped. In such a case, this handler will be called from TL = 1.
 	 * We handle the situation by pretending that the MMU miss occurred
-	 * on TL = 0. Once the MMU miss trap is services, the instruction which
+	 * on TL = 0. Once the MMU miss trap is serviced, the instruction which
 	 * caused the spill/fill trap is restarted, the spill/fill trap occurs,
-	 * but this time its handler accesse memory which IS mapped.
+	 * but this time its handler accesses memory which is mapped.
 	 */
 	.if (\tl > 0)
@@ -131,16 +133,18 @@
 	.endif
 
+	mov TT_FAST_DATA_ACCESS_MMU_MISS, %g2
+
 	/*
-	 * Save the faulting virtual page and faulting context to the %g2
-	 * register. The most significant 51 bits of the %g2 register will
+	 * Save the faulting virtual page and faulting context to the %g5
+	 * register. The most significant 51 bits of the %g5 register will
 	 * contain the virtual address which caused the fault truncated to the
-	 * page boundary. The least significant 13 bits of the %g2 register
+	 * page boundary. The least significant 13 bits of the %g5 register
 	 * will contain the number of the context in which the fault occurred.
-	 * The value of the %g2 register will be passed as a parameter to the
-	 * higher level service routine.
+	 * The value of the %g5 register will be stored in the istate structure
+	 * for inspeciton by the higher level service routine.
 	 */
-	or %g1, %g3, %g2
+	or %g1, %g3, %g5
 
-	PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
+	PREEMPTIBLE_HANDLER exc_dispatch
 .endm
 
@@ -170,8 +174,10 @@
 	sllx %g1, TTE_DATA_TADDR_OFFSET, %g1
 
+	mov TT_FAST_DATA_ACCESS_PROTECTION, %g2
+
 	/* the same as for FAST_DATA_ACCESS_MMU_MISS_HANDLER */
-	or %g1, %g3, %g2
+	or %g1, %g3, %g5
 
-	PREEMPTIBLE_HANDLER fast_data_access_protection
+	PREEMPTIBLE_HANDLER exc_dispatch 
 .endm
 #endif /* __ASM__ */
Index: kernel/arch/sparc64/src/mm/sun4v/tlb.c
===================================================================
--- kernel/arch/sparc64/src/mm/sun4v/tlb.c	(revision aef669be8dd7a8d097d3e2f786ba26f90cf761fd)
+++ kernel/arch/sparc64/src/mm/sun4v/tlb.c	(revision cade9c1cbd4f94b59da9f4de3a18874d30dcbb38)
@@ -208,5 +208,5 @@
 
 /** ITLB miss handler. */
-void fast_instruction_access_mmu_miss(sysarg_t unused, istate_t *istate)
+void fast_instruction_access_mmu_miss(unsigned int tt, istate_t *istate)
 {
 	uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
@@ -239,17 +239,12 @@
  * low-level, assembly language part of the fast_data_access_mmu_miss handler.
  *
- * @param page_and_ctx	A 64-bit value describing the fault. The most
- * 			significant 51 bits of the value contain the virtual
- * 			address which caused the fault truncated to the page
- * 			boundary. The least significant 13 bits of the value
- * 			contain the number of the context in which the fault
- * 			occurred.
+ * @param tt		Trap type.
  * @param istate	Interrupted state saved on the stack.
  */
-void fast_data_access_mmu_miss(uint64_t page_and_ctx, istate_t *istate)
+void fast_data_access_mmu_miss(unsigned int tt, istate_t *istate)
 {
 	pte_t *t;
-	uintptr_t va = DMISS_ADDRESS(page_and_ctx);
-	uint16_t ctx = DMISS_CONTEXT(page_and_ctx);
+	uintptr_t va = DMISS_ADDRESS(istate->tlb_tag_access);
+	uint16_t ctx = DMISS_CONTEXT(istate->tlb_tag_access);
 	as_t *as = AS;
 
@@ -288,17 +283,12 @@
 /** DTLB protection fault handler.
  *
- * @param page_and_ctx	A 64-bit value describing the fault. The most
- * 			significant 51 bits of the value contain the virtual
- * 			address which caused the fault truncated to the page
- * 			boundary. The least significant 13 bits of the value
- * 			contain the number of the context in which the fault
- * 			occurred.
+ * @param tt		Trap type.
  * @param istate	Interrupted state saved on the stack.
  */
-void fast_data_access_protection(uint64_t page_and_ctx, istate_t *istate)
+void fast_data_access_protection(unsigned int tt, istate_t *istate)
 {
 	pte_t *t;
-	uintptr_t va = DMISS_ADDRESS(page_and_ctx);
-	uint16_t ctx = DMISS_CONTEXT(page_and_ctx);
+	uintptr_t va = DMISS_ADDRESS(istate->tlb_tag_access);
+	uint16_t ctx = DMISS_CONTEXT(istate->tlb_tag_access);
 	as_t *as = AS;
 
Index: kernel/arch/sparc64/src/sun4v/sparc64.c
===================================================================
--- kernel/arch/sparc64/src/sun4v/sparc64.c	(revision aef669be8dd7a8d097d3e2f786ba26f90cf761fd)
+++ kernel/arch/sparc64/src/sun4v/sparc64.c	(revision cade9c1cbd4f94b59da9f4de3a18874d30dcbb38)
@@ -84,6 +84,8 @@
 void arch_pre_mm_init(void)
 {
-	if (config.cpu_active == 1)
+	if (config.cpu_active == 1) {
 		trap_init();
+		exc_arch_init();
+	}
 }
 
Index: kernel/arch/sparc64/src/trap/interrupt.c
===================================================================
--- kernel/arch/sparc64/src/trap/interrupt.c	(revision aef669be8dd7a8d097d3e2f786ba26f90cf761fd)
+++ kernel/arch/sparc64/src/trap/interrupt.c	(revision cade9c1cbd4f94b59da9f4de3a18874d30dcbb38)
@@ -60,4 +60,14 @@
 	    "instruction_access_error", false,
 	    instruction_access_error);
+
+#ifdef SUN4V
+	exc_register(TT_IAE_UNAUTH_ACCESS,
+	    "iae_unauth_access", false,
+	    instruction_access_exception);
+	exc_register(TT_IAE_NFO_PAGE,
+	    "iae_nfo_page", false,
+	    instruction_access_exception);
+#endif
+
 	exc_register(TT_ILLEGAL_INSTRUCTION,
 	    "illegal_instruction", false,
@@ -72,4 +82,23 @@
 	    "unimplemented_STD", false,
 	    unimplemented_STD);
+
+#ifdef SUN4V
+	exc_register(TT_DAE_INVALID_ASI,
+	    "dae_invalid_asi", false,
+	    data_access_exception);
+	exc_register(TT_DAE_PRIVILEGE_VIOLATION,
+	    "dae_privilege_violation", false,
+	    data_access_exception);
+	exc_register(TT_DAE_NC_PAGE,
+	    "dae_nc_page", false,
+	    data_access_exception);
+	exc_register(TT_DAE_NC_PAGE,
+	    "dae_nc_page", false,
+	    data_access_exception);
+	exc_register(TT_DAE_NFO_PAGE,
+	    "dae_nfo_page", false,
+	    data_access_exception);
+#endif
+
 	exc_register(TT_FP_DISABLED,
 	    "fp_disabled", true,
@@ -116,5 +145,5 @@
 	    tick_interrupt);
 
-#ifdef SUN4u 
+#ifdef SUN4U 
 	exc_register(TT_INTERRUPT_VECTOR_TRAP,
 	    "interrupt_vector_trap", true,
@@ -131,4 +160,11 @@
 	    "fast_data_access_protection", true,
 	    fast_data_access_protection);	
+
+#ifdef SUN4V
+	exc_register(TT_CPU_MONDO,
+	    "cpu_mondo", true,
+	    cpu_mondo);
+#endif
+
 }
 
Index: kernel/arch/sparc64/src/trap/sun4v/interrupt.c
===================================================================
--- kernel/arch/sparc64/src/trap/sun4v/interrupt.c	(revision aef669be8dd7a8d097d3e2f786ba26f90cf761fd)
+++ kernel/arch/sparc64/src/trap/sun4v/interrupt.c	(revision cade9c1cbd4f94b59da9f4de3a18874d30dcbb38)
@@ -95,5 +95,5 @@
  * register and processes the message (invokes a function call).
  */
-void cpu_mondo(void)
+void cpu_mondo(unsigned int tt, istate_t *istate)
 {
 #ifdef CONFIG_SMP
Index: kernel/arch/sparc64/src/trap/sun4v/trap_table.S
===================================================================
--- kernel/arch/sparc64/src/trap/sun4v/trap_table.S	(revision aef669be8dd7a8d097d3e2f786ba26f90cf761fd)
+++ kernel/arch/sparc64/src/trap/sun4v/trap_table.S	(revision cade9c1cbd4f94b59da9f4de3a18874d30dcbb38)
@@ -66,5 +66,7 @@
 .global instruction_access_exception_tl0
 instruction_access_exception_tl0:
-	PREEMPTIBLE_HANDLER instruction_access_exception
+	mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x09, TL = 0, instruction_access_mmu_miss */
@@ -77,5 +79,7 @@
 .global instruction_access_error_tl0
 instruction_access_error_tl0:
-	PREEMPTIBLE_HANDLER instruction_access_error
+	mov TT_INSTRUCTION_ACCESS_ERROR, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x0b, TL = 0, IAE_unauth_access */
@@ -83,5 +87,7 @@
 .global iae_unauth_access_tl0
 iae_unauth_access_tl0:
-	PREEMPTIBLE_HANDLER instruction_access_exception
+	mov TT_IAE_UNAUTH_ACCESS, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x0c, TL = 0, IAE_nfo_page */
@@ -89,5 +95,7 @@
 .global iae_nfo_page_tl0
 iae_nfo_page_tl0:
-	PREEMPTIBLE_HANDLER instruction_access_exception
+	mov TT_IAE_NFO_PAGE, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x10, TL = 0, illegal_instruction */
@@ -95,5 +103,7 @@
 .global illegal_instruction_tl0
 illegal_instruction_tl0:
-	PREEMPTIBLE_HANDLER illegal_instruction
+	mov TT_ILLEGAL_INSTRUCTION, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x11, TL = 0, privileged_opcode */
@@ -101,5 +111,7 @@
 .global privileged_opcode_tl0
 privileged_opcode_tl0:
-	PREEMPTIBLE_HANDLER privileged_opcode
+	mov TT_PRIVILEGED_OPCODE, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x12, TL = 0, unimplemented_LDD */
@@ -107,5 +119,7 @@
 .global unimplemented_LDD_tl0
 unimplemented_LDD_tl0:
-	PREEMPTIBLE_HANDLER unimplemented_LDD
+	mov TT_UNIMPLEMENTED_LDD, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x13, TL = 0, unimplemented_STD */
@@ -113,5 +127,7 @@
 .global unimplemented_STD_tl0
 unimplemented_STD_tl0:
-	PREEMPTIBLE_HANDLER unimplemented_STD
+	mov TT_UNIMPLEMENTED_STD, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x14, TL = 0, DAE_invalid_asi */
@@ -119,5 +135,7 @@
 .global dae_invalid_asi_tl0
 dae_invalid_asi_tl0:
-	PREEMPTIBLE_HANDLER data_access_exception
+	mov TT_DAE_INVALID_ASI, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x15, TL = 0, DAE_privilege_violation */
@@ -125,5 +143,7 @@
 .global dae_privilege_violation_tl0
 dae_privilege_violation_tl0:
-	PREEMPTIBLE_HANDLER data_access_exception
+	mov TT_DAE_PRIVILEGE_VIOLATION, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x16, TL = 0, DAE_nc_page */
@@ -131,5 +151,7 @@
 .global dae_nc_page_tl0
 dae_nc_page_tl0:
-	PREEMPTIBLE_HANDLER data_access_exception
+	mov TT_DAE_NC_PAGE, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x17, TL = 0, DAE_nfo_page */
@@ -137,5 +159,7 @@
 .global dae_nfo_page_tl0
 dae_nfo_page_tl0:
-	PREEMPTIBLE_HANDLER data_access_exception
+	mov TT_DAE_NFO_PAGE, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x20, TL = 0, fb_disabled handler */
@@ -143,5 +167,7 @@
 .global fb_disabled_tl0
 fp_disabled_tl0:
-	PREEMPTIBLE_HANDLER fp_disabled
+	mov TT_FP_DISABLED, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x21, TL = 0, fb_exception_ieee_754 handler */
@@ -149,5 +175,7 @@
 .global fb_exception_ieee_754_tl0
 fp_exception_ieee_754_tl0:
-	PREEMPTIBLE_HANDLER fp_exception_ieee_754
+	mov TT_FP_EXCEPTION_IEEE_754, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x22, TL = 0, fb_exception_other handler */
@@ -155,5 +183,7 @@
 .global fb_exception_other_tl0
 fp_exception_other_tl0:
-	PREEMPTIBLE_HANDLER fp_exception_other
+	mov TT_FP_EXCEPTION_OTHER, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x23, TL = 0, tag_overflow */
@@ -161,5 +191,7 @@
 .global tag_overflow_tl0
 tag_overflow_tl0:
-	PREEMPTIBLE_HANDLER tag_overflow
+	mov TT_TAG_OVERFLOW, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x24, TL = 0, clean_window handler */
@@ -173,5 +205,7 @@
 .global division_by_zero_tl0
 division_by_zero_tl0:
-	PREEMPTIBLE_HANDLER division_by_zero
+	mov TT_DIVISION_BY_ZERO, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x30, TL = 0, data_access_exception */
@@ -180,5 +214,7 @@
 .global data_access_exception_tl0
 data_access_exception_tl0:
-	PREEMPTIBLE_HANDLER data_access_exception
+	mov TT_DATA_ACCESS_EXCEPTION, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x31, TL = 0, data_access_mmu_miss */
@@ -192,5 +228,7 @@
 .global data_access_error_tl0
 data_access_error_tl0:
-	PREEMPTIBLE_HANDLER data_access_error
+	mov TT_DATA_ACCESS_ERROR, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x34, TL = 0, mem_address_not_aligned */
@@ -198,5 +236,7 @@
 .global mem_address_not_aligned_tl0
 mem_address_not_aligned_tl0:
-	PREEMPTIBLE_HANDLER mem_address_not_aligned
+	mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x35, TL = 0, LDDF_mem_address_not_aligned */
@@ -204,5 +244,7 @@
 .global LDDF_mem_address_not_aligned_tl0
 LDDF_mem_address_not_aligned_tl0:
-	PREEMPTIBLE_HANDLER LDDF_mem_address_not_aligned
+	mov TT_LDDF_MEM_ADDRESS_NOT_ALIGNED, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x36, TL = 0, STDF_mem_address_not_aligned */
@@ -210,5 +252,7 @@
 .global STDF_mem_address_not_aligned_tl0
 STDF_mem_address_not_aligned_tl0:
-	PREEMPTIBLE_HANDLER STDF_mem_address_not_aligned
+	mov TT_STDF_MEM_ADDRESS_NOT_ALIGNED, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x37, TL = 0, privileged_action */
@@ -216,5 +260,7 @@
 .global privileged_action_tl0
 privileged_action_tl0:
-	PREEMPTIBLE_HANDLER privileged_action
+	mov TT_PRIVILEGED_ACTION, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x38, TL = 0, LDQF_mem_address_not_aligned */
@@ -222,5 +268,7 @@
 .global LDQF_mem_address_not_aligned_tl0
 LDQF_mem_address_not_aligned_tl0:
-	PREEMPTIBLE_HANDLER LDQF_mem_address_not_aligned
+	mov TT_LDQF_MEM_ADDRESS_NOT_ALIGNED, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x39, TL = 0, STQF_mem_address_not_aligned */
@@ -228,5 +276,7 @@
 .global STQF_mem_address_not_aligned_tl0
 STQF_mem_address_not_aligned_tl0:
-	PREEMPTIBLE_HANDLER STQF_mem_address_not_aligned
+	mov TT_STQF_MEM_ADDRESS_NOT_ALIGNED, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x41, TL = 0, interrupt_level_1 handler */
@@ -234,5 +284,7 @@
 .global interrupt_level_1_handler_tl0
 interrupt_level_1_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 1
+	mov TT_INTERRUPT_LEVEL_1, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x42, TL = 0, interrupt_level_2 handler */
@@ -240,5 +292,7 @@
 .global interrupt_level_2_handler_tl0
 interrupt_level_2_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 2
+	mov TT_INTERRUPT_LEVEL_2, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x43, TL = 0, interrupt_level_3 handler */
@@ -246,5 +300,7 @@
 .global interrupt_level_3_handler_tl0
 interrupt_level_3_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 3
+	mov TT_INTERRUPT_LEVEL_3, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x44, TL = 0, interrupt_level_4 handler */
@@ -252,5 +308,7 @@
 .global interrupt_level_4_handler_tl0
 interrupt_level_4_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 4
+	mov TT_INTERRUPT_LEVEL_4, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x45, TL = 0, interrupt_level_5 handler */
@@ -258,5 +316,7 @@
 .global interrupt_level_5_handler_tl0
 interrupt_level_5_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 5
+	mov TT_INTERRUPT_LEVEL_5, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x46, TL = 0, interrupt_level_6 handler */
@@ -264,5 +324,7 @@
 .global interrupt_level_6_handler_tl0
 interrupt_level_6_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 6
+	mov TT_INTERRUPT_LEVEL_6, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x47, TL = 0, interrupt_level_7 handler */
@@ -270,5 +332,7 @@
 .global interrupt_level_7_handler_tl0
 interrupt_level_7_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 7
+	mov TT_INTERRUPT_LEVEL_7, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x48, TL = 0, interrupt_level_8 handler */
@@ -276,5 +340,7 @@
 .global interrupt_level_8_handler_tl0
 interrupt_level_8_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 8
+	mov TT_INTERRUPT_LEVEL_8, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x49, TL = 0, interrupt_level_9 handler */
@@ -282,5 +348,7 @@
 .global interrupt_level_9_handler_tl0
 interrupt_level_9_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 9
+	mov TT_INTERRUPT_LEVEL_9, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x4a, TL = 0, interrupt_level_10 handler */
@@ -288,5 +356,7 @@
 .global interrupt_level_10_handler_tl0
 interrupt_level_10_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 10
+	mov TT_INTERRUPT_LEVEL_10, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x4b, TL = 0, interrupt_level_11 handler */
@@ -294,5 +364,7 @@
 .global interrupt_level_11_handler_tl0
 interrupt_level_11_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 11
+	mov TT_INTERRUPT_LEVEL_11, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x4c, TL = 0, interrupt_level_12 handler */
@@ -300,5 +372,7 @@
 .global interrupt_level_12_handler_tl0
 interrupt_level_12_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 12
+	mov TT_INTERRUPT_LEVEL_12, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x4d, TL = 0, interrupt_level_13 handler */
@@ -306,5 +380,7 @@
 .global interrupt_level_13_handler_tl0
 interrupt_level_13_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 13
+	mov TT_INTERRUPT_LEVEL_13, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x4e, TL = 0, interrupt_level_14 handler */
@@ -312,5 +388,7 @@
 .global interrupt_level_14_handler_tl0
 interrupt_level_14_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 14
+	mov TT_INTERRUPT_LEVEL_14, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x4f, TL = 0, interrupt_level_15 handler */
@@ -318,5 +396,7 @@
 .global interrupt_level_15_handler_tl0
 interrupt_level_15_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 15
+	mov TT_INTERRUPT_LEVEL_15, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */
@@ -342,5 +422,7 @@
 .global cpu_mondo_handler_tl0
 cpu_mondo_handler_tl0:
-PREEMPTIBLE_HANDLER cpu_mondo
+	mov TT_CPU_MONDO, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER cpu_mondo
 
 /* TT = 0x80, TL = 0, spill_0_normal handler */
@@ -392,6 +474,7 @@
 .global trap_instruction_\cur\()_tl0
 trap_instruction_\cur\()_tl0:
+	mov \cur, %g2
 	ba %xcc, trap_instruction_handler
-	mov \cur, %g2
+	clr %g5
 .endr
 
@@ -406,5 +489,7 @@
 instruction_access_exception_tl1:
 	wrpr %g0, 1, %tl
-	PREEMPTIBLE_HANDLER instruction_access_exception
+	mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x09, TL > 0, instruction_access_mmu_miss */
@@ -419,5 +504,7 @@
 instruction_access_error_tl1:
 	wrpr %g0, 1, %tl
-	PREEMPTIBLE_HANDLER instruction_access_error
+	mov TT_INSTRUCTION_ACCESS_ERROR, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x0b, TL > 0, IAE_unauth_access */
@@ -426,5 +513,7 @@
 iae_unauth_access_tl1:
 	wrpr %g0, 1, %tl
-	PREEMPTIBLE_HANDLER instruction_access_exception
+	mov TT_IAE_UNAUTH_ACCESS, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x0c, TL > 0, IAE_nfo_page */
@@ -433,5 +522,7 @@
 iae_nfo_page_tl1:
 	wrpr %g0, 1, %tl
-	PREEMPTIBLE_HANDLER instruction_access_exception
+	mov TT_IAE_NFO_PAGE, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x10, TL > 0, illegal_instruction */
@@ -440,5 +531,7 @@
 illegal_instruction_tl1:
 	wrpr %g0, 1, %tl
-	PREEMPTIBLE_HANDLER illegal_instruction
+	mov TT_ILLEGAL_INSTRUCTION, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x14, TL > 0, DAE_invalid_asi */
@@ -447,5 +540,7 @@
 dae_invalid_asi_tl1:
 	wrpr %g0, 1, %tl
-	PREEMPTIBLE_HANDLER data_access_exception
+	mov TT_DAE_INVALID_ASI, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x15, TL > 0, DAE_privilege_violation */
@@ -454,5 +549,7 @@
 dae_privilege_violation_tl1:
 	wrpr %g0, 1, %tl
-	PREEMPTIBLE_HANDLER data_access_exception
+	mov TT_DAE_PRIVILEGE_VIOLATION, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x16, TL > 0, DAE_nc_page */
@@ -461,5 +558,7 @@
 dae_nc_page_tl1:
 	wrpr %g0, 1, %tl
-	PREEMPTIBLE_HANDLER data_access_exception
+	mov TT_DAE_NC_PAGE, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x17, TL > 0, DAE_nfo_page */
@@ -468,5 +567,7 @@
 dae_nfo_page_tl1:
 	wrpr %g0, 1, %tl
-	PREEMPTIBLE_HANDLER data_access_exception
+	mov TT_DAE_NFO_PAGE, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x24, TL > 0, clean_window handler */
@@ -481,5 +582,7 @@
 division_by_zero_tl1:
 	wrpr %g0, 1, %tl
-	PREEMPTIBLE_HANDLER division_by_zero
+	mov TT_DIVISION_BY_ZERO, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x30, TL > 0, data_access_exception */
@@ -487,7 +590,8 @@
 .global data_access_exception_tl1
 data_access_exception_tl1:
-	/*wrpr %g0, 1, %tl
-	wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
-	PREEMPTIBLE_HANDLER data_access_exception*/
+	wrpr %g0, 1, %tl
+	mov TT_DATA_ACCESS_EXCEPTION, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x31, TL > 0, data_access_mmu_miss */
@@ -502,5 +606,7 @@
 data_access_error_tl1:
 	wrpr %g0, 1, %tl
-	PREEMPTIBLE_HANDLER data_access_error
+	mov TT_DATA_ACCESS_ERROR, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x34, TL > 0, mem_address_not_aligned */
@@ -509,5 +615,7 @@
 mem_address_not_aligned_tl1:
 	wrpr %g0, 1, %tl
-	PREEMPTIBLE_HANDLER mem_address_not_aligned
+	mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x68, TL > 0, fast_data_access_MMU_miss */
@@ -528,5 +636,7 @@
 cpu_mondo_handler_tl1:
 	wrpr %g0, %tl
-	PREEMPTIBLE_HANDLER cpu_mondo
+	mov TT_CPU_MONDO, %g2
+	clr %g5
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x80, TL > 0, spill_0_normal handler */
@@ -654,5 +764,5 @@
 .else
 	! store the syscall number on the stack as 7th argument
-	stx %g2, [%sp + STACK_WINDOW_SAVE_AREA_SIZE + STACK_BIAS + STACK_ARG6] 
+	stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_ARG6] 
 .endif
 
@@ -664,17 +774,18 @@
 	rdpr %tnpc, %g3
 
-	stx %g1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE]
-	stx %g2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC]
-	stx %g3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC]
+	stx %g1, [%sp + STACK_BIAS + ISTATE_OFFSET_TSTATE]
+	stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_TPC]
+	stx %g3, [%sp + STACK_BIAS + ISTATE_OFFSET_TNPC]
 
 	/*
 	 * Save the Y register.
-	 * This register is deprecated according to SPARC V9 specification
-	 * and is only present for backward compatibility with previous
-	 * versions of the SPARC architecture.
-	 * Surprisingly, gcc makes use of this register without a notice.
 	 */
 	rd %y, %g4
-	stx %g4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y]
+	stx %g4, [%sp + STACK_BIAS + ISTATE_OFFSET_Y]
+
+	/*
+	 * Save the faulting page and context.
+	 */
+	stx %g5, [%sp + STACK_BIAS + ISTATE_OFFSET_TLB_TAG_ACCESS]
 
 	/* switch to TL = 0, explicitly enable FPU */
@@ -689,5 +800,5 @@
 	/* call higher-level service routine, pass istate as its 2nd parameter */
 	call %l0
-	add %sp, PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC, %o1
+	add %sp, STACK_BIAS, %o1
 .else
 	/* Call the higher-level syscall handler. */
@@ -711,7 +822,7 @@
 
 	/* Read TSTATE, TPC and TNPC from saved copy. */
-	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE], %g1
-	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC], %g2
-	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC], %g3
+	ldx [%sp + STACK_BIAS + ISTATE_OFFSET_TSTATE], %g1
+	ldx [%sp + STACK_BIAS + ISTATE_OFFSET_TPC], %g2
+	ldx [%sp + STACK_BIAS + ISTATE_OFFSET_TNPC], %g3
 
 	/* Copy PSTATE.PEF to the in-register copy of TSTATE. */
@@ -728,5 +839,5 @@
 
 	/* Restore Y. */
-	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y], %g4
+	ldx [%sp + STACK_BIAS + ISTATE_OFFSET_Y], %g4
 	wr %g4, %y
 	
@@ -750,22 +861,22 @@
 	 */
 	mov %sp, %g2
-	stx %i0, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0]
-	stx %i1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1]
-	stx %i2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2]
-	stx %i3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3]
-	stx %i4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4]
-	stx %i5, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5]
-	stx %i6, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6]
-	stx %i7, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7]
+	stx %i0, [%sp + STACK_BIAS + ISTATE_OFFSET_O0]
+	stx %i1, [%sp + STACK_BIAS + ISTATE_OFFSET_O1]
+	stx %i2, [%sp + STACK_BIAS + ISTATE_OFFSET_O2]
+	stx %i3, [%sp + STACK_BIAS + ISTATE_OFFSET_O3]
+	stx %i4, [%sp + STACK_BIAS + ISTATE_OFFSET_O4]
+	stx %i5, [%sp + STACK_BIAS + ISTATE_OFFSET_O5]
+	stx %i6, [%sp + STACK_BIAS + ISTATE_OFFSET_O6]
+	stx %i7, [%sp + STACK_BIAS + ISTATE_OFFSET_O7]
 	wrpr %l0, 0, %cwp
 	mov %g2, %sp
-	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0], %i0
-	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1], %i1
-	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2], %i2
-	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3], %i3
-	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4], %i4
-	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5], %i5
-	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6], %i6
-	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7], %i7
+	ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O0], %i0
+	ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O1], %i1
+	ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O2], %i2
+	ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O3], %i3
+	ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O4], %i4
+	ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O5], %i5
+	ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O6], %i6
+	ldx [%sp + STACK_BIAS + ISTATE_OFFSET_O7], %i7
 .endm
 
@@ -774,17 +885,4 @@
  */
 .macro PREEMPTIBLE_HANDLER_KERNEL
-
-	/*
-	 * ASSERT(%tl == 1)
-	 */
-	rdpr %tl, %g3
-	cmp %g3, 1
-	be %xcc, 1f
-	nop
-
-	! this is for debugging, if we ever get here it will be easy to find
-0:	ba,a %xcc, 0b
-
-1:
 	/* prevent unnecessary CLEANWIN exceptions */
 	wrpr %g0, NWINDOWS - 1, %cleanwin
@@ -803,5 +901,5 @@
 2:
 	/* ask for new register window */
-	save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
+	save %sp, -ISTATE_SIZE, %sp
 
 	MIDDLE_PART 0
@@ -882,5 +980,5 @@
 	set SCRATCHPAD_KSTACK, %g4
 	ldxa [%g4] ASI_SCRATCHPAD, %g6
-	save %g6, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
+	save %g6, -ISTATE_SIZE, %sp
 
 .if \is_syscall
@@ -1015,5 +1113,5 @@
 	 * If the:
 	 *
-	 * 	save %g6, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
+	 * 	save %g6, -ISTATE_SIZE, %sp
 	 *
 	 * instruction trapped and spilled a register window into the userspace