Index: kernel/arch/ia64/include/asm.h
===================================================================
--- kernel/arch/ia64/include/asm.h	(revision dbd5df1bf8c369a2f0baa56e369ca2acf995f1f9)
+++ kernel/arch/ia64/include/asm.h	(revision ca8f84f28749a37bc03923e5f1b1de449c46816a)
@@ -40,8 +40,9 @@
 #include <typedefs.h>
 #include <arch/register.h>
+#include <trace.h>
 
 #define IA64_IOSPACE_ADDRESS  0xE001000000000000ULL
 
-static inline void pio_write_8(ioport8_t *port, uint8_t v)
+NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
 {
 	uintptr_t prt = (uintptr_t) port;
@@ -56,5 +57,5 @@
 }
 
-static inline void pio_write_16(ioport16_t *port, uint16_t v)
+NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
 {
 	uintptr_t prt = (uintptr_t) port;
@@ -69,5 +70,5 @@
 }
 
-static inline void pio_write_32(ioport32_t *port, uint32_t v)
+NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
 {
 	uintptr_t prt = (uintptr_t) port;
@@ -82,5 +83,5 @@
 }
 
-static inline uint8_t pio_read_8(ioport8_t *port)
+NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
 {
 	uintptr_t prt = (uintptr_t) port;
@@ -95,5 +96,5 @@
 }
 
-static inline uint16_t pio_read_16(ioport16_t *port)
+NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
 {
 	uintptr_t prt = (uintptr_t) port;
@@ -108,5 +109,5 @@
 }
 
-static inline uint32_t pio_read_32(ioport32_t *port)
+NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
 {
 	uintptr_t prt = (uintptr_t) port;
@@ -126,21 +127,26 @@
  * The stack is assumed to be STACK_SIZE long.
  * The stack must start on page boundary.
- */
-static inline uintptr_t get_stack_base(void)
-{
-	uint64_t v;
-	
-	/* I'm not sure why but this code bad inlines in scheduler,
-	   so THE shifts about 16B and causes kernel panic
-	   
-	   asm volatile (
-	       "and %[value] = %[mask], r12"
-	       : [value] "=r" (v)
-	       : [mask] "r" (~(STACK_SIZE - 1))
-	   );
-	   return v;
-	   
-	   This code have the same meaning but inlines well.
-	*/
+ *
+ */
+NO_TRACE static inline uintptr_t get_stack_base(void)
+{
+	uint64_t v;
+	
+	/*
+	 * I'm not sure why but this code inlines badly
+	 * in scheduler, resulting in THE shifting about
+	 * 16B and causing kernel panic.
+	 *
+	 * asm volatile (
+	 *     "and %[value] = %[mask], r12"
+	 *     : [value] "=r" (v)
+	 *     : [mask] "r" (~(STACK_SIZE - 1))
+	 * );
+	 * return v;
+	 *
+	 * The following code has the same semantics but
+	 * inlines correctly.
+	 *
+	 */
 	
 	asm volatile (
@@ -155,6 +161,7 @@
  *
  * @return PSR.
- */
-static inline uint64_t psr_read(void)
+ *
+ */
+NO_TRACE static inline uint64_t psr_read(void)
 {
 	uint64_t v;
@@ -171,6 +178,7 @@
  *
  * @return Return location of interruption vector table.
- */
-static inline uint64_t iva_read(void)
+ *
+ */
+NO_TRACE static inline uint64_t iva_read(void)
 {
 	uint64_t v;
@@ -187,6 +195,7 @@
  *
  * @param v New location of interruption vector table.
- */
-static inline void iva_write(uint64_t v)
+ *
+ */
+NO_TRACE static inline void iva_write(uint64_t v)
 {
 	asm volatile (
@@ -196,10 +205,11 @@
 }
 
-
 /** Read IVR (External Interrupt Vector Register).
  *
- * @return Highest priority, pending, unmasked external interrupt vector.
- */
-static inline uint64_t ivr_read(void)
+ * @return Highest priority, pending, unmasked external
+ *         interrupt vector.
+ *
+ */
+NO_TRACE static inline uint64_t ivr_read(void)
 {
 	uint64_t v;
@@ -213,5 +223,5 @@
 }
 
-static inline uint64_t cr64_read(void)
+NO_TRACE static inline uint64_t cr64_read(void)
 {
 	uint64_t v;
@@ -225,10 +235,10 @@
 }
 
-
 /** Write ITC (Interval Timer Counter) register.
  *
  * @param v New counter value.
- */
-static inline void itc_write(uint64_t v)
+ *
+ */
+NO_TRACE static inline void itc_write(uint64_t v)
 {
 	asm volatile (
@@ -241,6 +251,7 @@
  *
  * @return Current counter value.
- */
-static inline uint64_t itc_read(void)
+ *
+ */
+NO_TRACE static inline uint64_t itc_read(void)
 {
 	uint64_t v;
@@ -257,6 +268,7 @@
  *
  * @param v New match value.
- */
-static inline void itm_write(uint64_t v)
+ *
+ */
+NO_TRACE static inline void itm_write(uint64_t v)
 {
 	asm volatile (
@@ -269,6 +281,7 @@
  *
  * @return Match value.
- */
-static inline uint64_t itm_read(void)
+ *
+ */
+NO_TRACE static inline uint64_t itm_read(void)
 {
 	uint64_t v;
@@ -285,6 +298,7 @@
  *
  * @return Current vector and mask bit.
- */
-static inline uint64_t itv_read(void)
+ *
+ */
+NO_TRACE static inline uint64_t itv_read(void)
 {
 	uint64_t v;
@@ -301,6 +315,7 @@
  *
  * @param v New vector and mask bit.
- */
-static inline void itv_write(uint64_t v)
+ *
+ */
+NO_TRACE static inline void itv_write(uint64_t v)
 {
 	asm volatile (
@@ -313,6 +328,7 @@
  *
  * @param v This value is ignored.
- */
-static inline void eoi_write(uint64_t v)
+ *
+ */
+NO_TRACE static inline void eoi_write(uint64_t v)
 {
 	asm volatile (
@@ -325,6 +341,7 @@
  *
  * @return Current value of TPR.
- */
-static inline uint64_t tpr_read(void)
+ *
+ */
+NO_TRACE static inline uint64_t tpr_read(void)
 {
 	uint64_t v;
@@ -341,6 +358,7 @@
  *
  * @param v New value of TPR.
- */
-static inline void tpr_write(uint64_t v)
+ *
+ */
+NO_TRACE static inline void tpr_write(uint64_t v)
 {
 	asm volatile (
@@ -356,6 +374,7 @@
  *
  * @return Old interrupt priority level.
- */
-static ipl_t interrupts_disable(void)
+ *
+ */
+NO_TRACE static ipl_t interrupts_disable(void)
 {
 	uint64_t v;
@@ -377,6 +396,7 @@
  *
  * @return Old interrupt priority level.
- */
-static ipl_t interrupts_enable(void)
+ *
+ */
+NO_TRACE static ipl_t interrupts_enable(void)
 {
 	uint64_t v;
@@ -399,6 +419,7 @@
  *
  * @param ipl Saved interrupt priority level.
- */
-static inline void interrupts_restore(ipl_t ipl)
+ *
+ */
+NO_TRACE static inline void interrupts_restore(ipl_t ipl)
 {
 	if (ipl & PSR_I_MASK)
@@ -411,6 +432,7 @@
  *
  * @return PSR.
- */
-static inline ipl_t interrupts_read(void)
+ *
+ */
+NO_TRACE static inline ipl_t interrupts_read(void)
 {
 	return (ipl_t) psr_read();
@@ -422,5 +444,5 @@
  *
  */
-static inline bool interrupts_disabled(void)
+NO_TRACE static inline bool interrupts_disabled(void)
 {
 	return !(psr_read() & PSR_I_MASK);
@@ -428,5 +450,5 @@
 
 /** Disable protection key checking. */
-static inline void pk_disable(void)
+NO_TRACE static inline void pk_disable(void)
 {
 	asm volatile (
