Index: kernel/arch/arm32/include/arch/cp15.h
===================================================================
--- kernel/arch/arm32/include/arch/cp15.h	(revision 6ff23ff32c8aa9d6ad8d06f1743ca1b0d68c14bc)
+++ kernel/arch/arm32/include/arch/cp15.h	(revision c8afd5a8029517aba09c3f07e907308d90b306a2)
@@ -40,5 +40,6 @@
 
 /** See ARM Architecture reference manual ch. B3.17.1 page B3-1456
- * for the list */
+ * for the list
+ */
 
 #define CONTROL_REG_GEN_READ(name, crn, opc1, crm, opc2) \
@@ -183,4 +184,6 @@
 	CCSIDR_LINESIZE_MASK = 0x7,
 	CCSIDR_LINESIZE_SHIFT = 0,
+};
+
 #define CCSIDR_SETS(val) \
 	(((val >> CCSIDR_NUMSETS_SHIFT) & CCSIDR_NUMSETS_MASK) + 1)
@@ -190,5 +193,5 @@
 #define CCSIDR_LINESIZE_LOG(val) \
 	(((val >> CCSIDR_LINESIZE_SHIFT) & CCSIDR_LINESIZE_MASK) + 2 + 2)
-};
+
 CONTROL_REG_GEN_READ(CCSIDR, c0, 1, c0, 0);
 
@@ -206,7 +209,9 @@
 	CLIDR_UNI_CACHE = 0x4,
 	CLIDR_CACHE_MASK = 0x7,
+};
+
 /** levels counted from 0 */
 #define CLIDR_CACHE(level, val)   ((val >> (level * 3)) & CLIDR_CACHE_MASK)
-};
+
 CONTROL_REG_GEN_READ(CLIDR, c0, 1, c0, 1);
 CONTROL_REG_GEN_READ(AIDR, c0, 1, c0, 7); /* Implementation defined or MIDR */
@@ -225,6 +230,8 @@
 
 /* System control registers */
-/* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference
- * Manual ARMv7-A and ARMv7-R edition, page 1687 */
+/*
+ * Control register bit values see ch. B4.1.130 of ARM Architecture Reference
+ * Manual ARMv7-A and ARMv7-R edition, page 1687
+ */
 enum {
 	SCTLR_MMU_EN_FLAG            = 1 << 0,