Index: arch/mips32/src/exception.c
===================================================================
--- arch/mips32/src/exception.c	(revision 9cbd27bda027a69ffbcba03ec98a8179d37e83f0)
+++ arch/mips32/src/exception.c	(revision c715e9b93d5ce15f27506aa32b70bfc97c8630bf)
@@ -90,8 +90,6 @@
 		istate->epc += 4;
 		istate->v1 = istate->k1;
-	} else {
-		print_regdump(istate);
-		panic("reserved instruction");
-	}
+	} else 
+		unhandled_exception(n, istate);
 }
 
Index: arch/mips32/src/start.S
===================================================================
--- arch/mips32/src/start.S	(revision 9cbd27bda027a69ffbcba03ec98a8179d37e83f0)
+++ arch/mips32/src/start.S	(revision c715e9b93d5ce15f27506aa32b70bfc97c8630bf)
@@ -252,16 +252,14 @@
 	mtc0 $t0, $status
 
+	# CALL Syscall handler
 	jal syscall_handler
 	sw $v0, SS_ARG4($sp)        # save v0 - arg4 to stack
 
-	# restore epc+4
-	lw $t0,SS_EPC($sp)
-	addi $t0, $t0, 4
-	mtc0 $t0, $epc
-	
 	# restore status
 	mfc0 $t0, $status
 	lw $t1,SS_STATUS($sp)
 
+	# Change back to EXL=1(from last exception), otherwise
+	# an interrupt could rewrite the CP0-EPC
 	li $t2, ~REG_SAVE_MASK      # Mask UM,EXL,ERL,IE
 	and $t0, $t0, $t2
@@ -269,4 +267,9 @@
 	mtc0 $t0, $status
 			
+	# restore epc+4
+	lw $t0,SS_EPC($sp)
+	addi $t0, $t0, 4
+	mtc0 $t0, $epc
+	
 	lw $sp,SS_SP($sp) # restore sp