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  • boot/arch/arm32/src/mm.c

    r2e55443 rc6b601b  
    3838#include <arch/mm.h>
    3939
    40 /** Disable the MMU */
    41 static void disable_paging(void)
    42 {
    43         asm volatile (
    44                 "mrc p15, 0, r0, c1, c0, 0\n"
    45                 "bic r0, r0, #1\n"
    46                 "mcr p15, 0, r0, c1, c0, 0\n"
    47                 ::: "r0"
    48         );
    49 }
    50 
    51 /** Check if caching can be enabled for a given memory section.
    52  *
    53  * Memory areas used for I/O are excluded from caching.
    54  * At the moment caching is enabled only on GTA02.
    55  *
    56  * @param section       The section number.
    57  *
    58  * @return      1 if the given section can be mapped as cacheable, 0 otherwise.
    59 */
    60 static inline int section_cacheable(pfn_t section)
    61 {
    62 #ifdef MACHINE_gta02
    63         unsigned long address = section << PTE_SECTION_SHIFT;
    64 
    65         if (address >= GTA02_IOMEM_START && address < GTA02_IOMEM_END)
    66                 return 0;
    67         else
    68                 return 1;
    69 #elif defined MACHINE_beagleboardxm
    70         const unsigned long address = section << PTE_SECTION_SHIFT;
    71         if (address >= BBXM_RAM_START && address < BBXM_RAM_END)
    72                 return 1;
    73 #elif defined MACHINE_beaglebone
    74         const unsigned long address = section << PTE_SECTION_SHIFT;
    75         if (address >= AM335x_RAM_START && address < AM335x_RAM_END)
    76                 return 1;
    77 #endif
    78         return 0;
    79 }
    80 
    8140/** Initialize "section" page table entry.
    8241 *
    … …  
    9655        pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
    9756        pte->bufferable = 1;
    98         pte->cacheable = section_cacheable(frame);
     57        pte->cacheable = 0;
    9958        pte->xn = 0;
    10059        pte->domain = 0;
    … …  
    10362        pte->tex = 0;
    10463        pte->access_permission_1 = 0;
    105         pte->shareable = 0;
    10664        pte->non_global = 0;
    10765        pte->should_be_zero_2 = 0;
    … …  
    11876        for (page = 0; page < split_page; page++)
    11977                init_ptl0_section(&boot_pt[page], page);
     78       
     79        /*
     80         * Create 1:1 virtual-physical mapping in kernel space
     81         * (upper 2 GB), physical addresses start from 0.
     82         */
     83        /* BeagleBoard-xM (DM37x) memory starts at 2GB border,
     84         * thus mapping only lower 2GB is not not enough.
     85         * Map entire AS 1:1 instead and hope it works. */
     86        for (page = split_page; page < PTL0_ENTRIES; page++)
     87#ifndef MACHINE_beagleboardxm
     88                init_ptl0_section(&boot_pt[page], page - split_page);
     89#else
     90                init_ptl0_section(&boot_pt[page], page);
     91#endif
    12092       
    12193        asm volatile (
    … …  
    134106                "ldr r0, =0x55555555\n"
    135107                "mcr p15, 0, r0, c3, c0, 0\n"
    136 
     108               
     109#ifdef PROCESSOR_armv7_a
     110                /* Read Auxiliary control register */
     111                "mrc p15, 0, r0, c1, c0, 1\n"
     112                /* Mask to enable L2 cache */
     113                "ldr r1, =0x00000002\n"
     114                "orr r0, r0, r1\n"
     115                /* Store Auxiliary control register */
     116                "mrc p15, 0, r0, c1, c0, 1\n"
     117#endif
    137118                /* Current settings */
    138119                "mrc p15, 0, r0, c1, c0, 0\n"
    139120               
    140                 /* Enable ICache, DCache, BPredictors and MMU,
    141                  * we disable caches before jumping to kernel
    142                  * so this is safe for all archs.
    143                  */
    144                 "ldr r1, =0x00001805\n"
     121#ifdef PROCESSOR_armv7_a
     122                /* Mask to enable paging, caching */
     123                "ldr r1, =0x00000005\n"
     124#else
     125                /* Mask to enable paging */
     126                "ldr r1, =0x00000001\n"
     127#endif
     128                "orr r0, r0, r1\n"
    145129               
    146                 "orr r0, r0, r1\n"
    147 
    148                 /* Invalidate the TLB content before turning on the MMU.
    149                  * ARMv7-A Reference manual, B3.10.3
    150                  */
    151                 "mcr p15, 0, r0, c8, c7, 0\n"
    152                
    153                 /* Store settings, enable the MMU */
     130                /* Store settings */
    154131                "mcr p15, 0, r0, c1, c0, 0\n"
    155132                ::: "r0", "r1"
    … …  
    159136/** Start the MMU - initialize page table and enable paging. */
    160137void mmu_start() {
    161         disable_paging();
    162138        init_boot_pt();
    163139        enable_paging();
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