Changeset c621f4aa in mainline for kernel/arch/arm32/include


Ignore:
Timestamp:
2010-07-25T10:11:13Z (16 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
377cce8
Parents:
24a2517 (diff), a2da43c (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge with mainline.

Location:
kernel/arch/arm32/include
Files:
1 added
21 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/arm32/include/arch.h

    r24a2517 rc621f4aa  
    4545
    4646typedef struct {
    47         uintptr_t addr;
    48         uint32_t size;
     47        void *addr;
     48        size_t size;
    4949        char name[BOOTINFO_TASK_NAME_BUFLEN];
    5050} utask_t;
    5151
    5252typedef struct {
    53         uint32_t cnt;
     53        size_t cnt;
    5454        utask_t tasks[TASKMAP_MAX_RECORDS];
    5555} bootinfo_t;

  • kernel/arch/arm32/include/asm.h

    r24a2517 rc621f4aa  
    3838
    3939#include <typedefs.h>
    40 #include <arch/types.h>
    4140#include <arch/stack.h>
    4241#include <config.h>
    4342#include <arch/interrupt.h>
     43#include <trace.h>
    4444
    4545/** No such instruction on ARM to sleep CPU. */
    46 static inline void cpu_sleep(void)
     46NO_TRACE static inline void cpu_sleep(void)
    4747{
    4848}
    4949
    50 static inline void pio_write_8(ioport8_t *port, uint8_t v)
     50NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
    5151{
    5252        *port = v;
    5353}
    5454
    55 static inline void pio_write_16(ioport16_t *port, uint16_t v)
     55NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
    5656{
    5757        *port = v;
    5858}
    5959
    60 static inline void pio_write_32(ioport32_t *port, uint32_t v)
     60NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
    6161{
    6262        *port = v;
    6363}
    6464
    65 static inline uint8_t pio_read_8(ioport8_t *port)
     65NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
    6666{
    6767        return *port;
    6868}
    6969
    70 static inline uint16_t pio_read_16(ioport16_t *port)
     70NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
    7171{
    7272        return *port;
    7373}
    7474
    75 static inline uint32_t pio_read_32(ioport32_t *port)
     75NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
    7676{
    7777        return *port;
    … …  
    8585 *
    8686 */
    87 static inline uintptr_t get_stack_base(void)
     87NO_TRACE static inline uintptr_t get_stack_base(void)
    8888{
    8989        uintptr_t v;
     90       
    9091        asm volatile (
    9192                "and %[v], sp, %[size]\n"
    … …  
    9394                : [size] "r" (~(STACK_SIZE - 1))
    9495        );
     96       
    9597        return v;
    9698}

  • kernel/arch/arm32/include/atomic.h

    r24a2517 rc621f4aa  
    3838
    3939#include <arch/asm.h>
     40#include <trace.h>
    4041
    4142/** Atomic addition.
    … …  
    4748 *
    4849 */
    49 static inline long atomic_add(atomic_t *val, int i)
     50NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val,
     51    atomic_count_t i)
    5052{
    51         long ret;
    52 
    5353        /*
    5454         * This implementation is for UP pre-ARMv6 systems where we do not have
    … …  
    5757        ipl_t ipl = interrupts_disable();
    5858        val->count += i;
    59         ret = val->count;
     59        atomic_count_t ret = val->count;
    6060        interrupts_restore(ipl);
    6161       
    … …  
    6666 *
    6767 * @param val Variable to be incremented.
     68 *
    6869 */
    69 static inline void atomic_inc(atomic_t *val)
     70NO_TRACE static inline void atomic_inc(atomic_t *val)
    7071{
    7172        atomic_add(val, 1);
    … …  
    7576 *
    7677 * @param val Variable to be decremented.
     78 *
    7779 */
    78 static inline void atomic_dec(atomic_t *val) {
     80NO_TRACE static inline void atomic_dec(atomic_t *val) {
    7981        atomic_add(val, -1);
    8082}
    … …  
    8486 * @param val Variable to be incremented.
    8587 * @return    Value after incrementation.
     88 *
    8689 */
    87 static inline long atomic_preinc(atomic_t *val)
     90NO_TRACE static inline atomic_count_t atomic_preinc(atomic_t *val)
    8891{
    8992        return atomic_add(val, 1);
    … …  
    9497 * @param val Variable to be decremented.
    9598 * @return    Value after decrementation.
     99 *
    96100 */
    97 static inline long atomic_predec(atomic_t *val)
     101NO_TRACE static inline atomic_count_t atomic_predec(atomic_t *val)
    98102{
    99103        return atomic_add(val, -1);
    … …  
    104108 * @param val Variable to be incremented.
    105109 * @return    Value before incrementation.
     110 *
    106111 */
    107 static inline long atomic_postinc(atomic_t *val)
     112NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val)
    108113{
    109114        return atomic_add(val, 1) - 1;
    … …  
    114119 * @param val Variable to be decremented.
    115120 * @return    Value before decrementation.
     121 *
    116122 */
    117 static inline long atomic_postdec(atomic_t *val)
     123NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val)
    118124{
    119125        return atomic_add(val, -1) + 1;

  • kernel/arch/arm32/include/context.h

    r24a2517 rc621f4aa  
    5252#ifndef __ASM__
    5353
    54 #include <arch/types.h>
     54#include <typedefs.h>
    5555
    5656/** Thread context containing registers that must be preserved across function

  • kernel/arch/arm32/include/cpu.h

    r24a2517 rc621f4aa  
    3737#define KERN_arm32_CPU_H_
    3838
    39 #include <arch/types.h>
     39#include <typedefs.h>
    4040#include <arch/asm.h>
    4141

  • kernel/arch/arm32/include/cycle.h

    r24a2517 rc621f4aa  
    3737#define KERN_arm32_CYCLE_H_
    3838
    39 /** Returns count of CPU cycles.
     39#include <trace.h>
     40
     41/** Return count of CPU cycles.
    4042 *
    41  *  No such instruction on ARM to get count of cycles.
     43 * No such instruction on ARM to get count of cycles.
    4244 *
    43  *  @return Count of CPU cycles.
     45 * @return Count of CPU cycles.
     46 *
    4447 */
    45 static inline uint64_t get_cycle(void)
     48NO_TRACE static inline uint64_t get_cycle(void)
    4649{
    4750        return 0;

  • kernel/arch/arm32/include/exception.h

    r24a2517 rc621f4aa  
    2828 */
    2929
    30 /** @addtogroup arm32   
     30/** @addtogroup arm32
    3131 * @{
    3232 */
    … …  
    3838#define KERN_arm32_EXCEPTION_H_
    3939
    40 #include <arch/types.h>
     40#include <typedefs.h>
    4141#include <arch/regutils.h>
     42#include <trace.h>
    4243
    4344/** If defined, forces using of high exception vectors. */
    … …  
    4546
    4647#ifdef HIGH_EXCEPTION_VECTORS
    47         #define EXC_BASE_ADDRESS        0xffff0000
     48        #define EXC_BASE_ADDRESS  0xffff0000
    4849#else
    49         #define EXC_BASE_ADDRESS        0x0
     50        #define EXC_BASE_ADDRESS  0x0
    5051#endif
    5152
    5253/* Exception Vectors */
    53 #define EXC_RESET_VEC          (EXC_BASE_ADDRESS + 0x0)
    54 #define EXC_UNDEF_INSTR_VEC    (EXC_BASE_ADDRESS + 0x4)
    55 #define EXC_SWI_VEC            (EXC_BASE_ADDRESS + 0x8)
    56 #define EXC_PREFETCH_ABORT_VEC (EXC_BASE_ADDRESS + 0xc)
    57 #define EXC_DATA_ABORT_VEC     (EXC_BASE_ADDRESS + 0x10)
    58 #define EXC_IRQ_VEC            (EXC_BASE_ADDRESS + 0x18)
    59 #define EXC_FIQ_VEC            (EXC_BASE_ADDRESS + 0x1c)
     54#define EXC_RESET_VEC           (EXC_BASE_ADDRESS + 0x0)
     55#define EXC_UNDEF_INSTR_VEC     (EXC_BASE_ADDRESS + 0x4)
     56#define EXC_SWI_VEC             (EXC_BASE_ADDRESS + 0x8)
     57#define EXC_PREFETCH_ABORT_VEC  (EXC_BASE_ADDRESS + 0xc)
     58#define EXC_DATA_ABORT_VEC      (EXC_BASE_ADDRESS + 0x10)
     59#define EXC_IRQ_VEC             (EXC_BASE_ADDRESS + 0x18)
     60#define EXC_FIQ_VEC             (EXC_BASE_ADDRESS + 0x1c)
    6061
    6162/* Exception numbers */
    … …  
    6869#define EXC_FIQ             6
    6970
    70 
    7171/** Kernel stack pointer.
    7272 *
    7373 * It is set when thread switches to user mode,
    7474 * and then used for exception handling.
     75 *
    7576 */
    7677extern uintptr_t supervisor_sp;
    77 
    7878
    7979/** Temporary exception stack pointer.
    … …  
    8181 * Temporary stack is used in exceptions handling routines
    8282 * before switching to thread's kernel stack.
     83 *
    8384 */
    8485extern uintptr_t exc_stack;
    85 
    8686
    8787/** Struct representing CPU state saved when an exception occurs. */
    … …  
    9090        uint32_t sp;
    9191        uint32_t lr;
    92 
     92       
    9393        uint32_t r0;
    9494        uint32_t r1;
    … …  
    104104        uint32_t fp;
    105105        uint32_t r12;
    106 
     106       
    107107        uint32_t pc;
    108108} istate_t;
    109109
    110 
    111 /** Sets Program Counter member of given istate structure.
     110/** Set Program Counter member of given istate structure.
    112111 *
    113  * @param istate istate structure
     112 * @param istate  istate structure
    114113 * @param retaddr new value of istate's PC member
     114 *
    115115 */
    116 static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
     116NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     117    uintptr_t retaddr)
    117118{
    118         istate->pc = retaddr;
     119        istate->pc = retaddr;
    119120}
    120121
    121 
    122 /** Returns true if exception happened while in userspace. */
    123 static inline int istate_from_uspace(istate_t *istate)
     122/** Return true if exception happened while in userspace. */
     123NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    124124{
    125         return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE;
     125        return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE;
    126126}
    127127
    128 
    129 /** Returns Program Counter member of given istate structure. */
    130 static inline unative_t istate_get_pc(istate_t *istate)
     128/** Return Program Counter member of given istate structure. */
     129NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
    131130{
    132         return istate->pc;
     131        return istate->pc;
    133132}
    134133
    135 static inline unative_t istate_get_fp(istate_t *istate)
     134NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
    136135{
    137136        return istate->fp;
    138137}
    139138
    140 
    141139extern void install_exception_handlers(void);
    142140extern void exception_init(void);
    143 extern void print_istate(istate_t *istate);
    144141extern void reset_exception_entry(void);
    145142extern void irq_exception_entry(void);
    … …  
    150147extern void swi_exception_entry(void);
    151148
    152 
    153149#endif
    154150

  • kernel/arch/arm32/include/faddr.h

    r24a2517 rc621f4aa  
    2727 */
    2828
    29 /** @addtogroup arm32   
     29/** @addtogroup arm32
    3030 * @{
    3131 */
    … …  
    3737#define KERN_arm32_FADDR_H_
    3838
    39 #include <arch/types.h>
     39#include <typedefs.h>
    4040
    4141/** Calculate absolute address of function referenced by fptr pointer.
    4242 *
    4343 * @param fptr Function pointer.
     44 *
    4445 */
    45 #define FADDR(fptr)             ((uintptr_t) (fptr))
     46#define FADDR(fptr)  ((uintptr_t) (fptr))
    4647
    4748#endif

  • kernel/arch/arm32/include/fpu_context.h

    r24a2517 rc621f4aa  
    3939#define KERN_arm32_FPU_CONTEXT_H_
    4040
    41 #include <arch/types.h>
     41#include <typedefs.h>
    4242
    4343#define FPU_CONTEXT_ALIGN    0

  • kernel/arch/arm32/include/interrupt.h

    r24a2517 rc621f4aa  
    3737#define KERN_arm32_INTERRUPT_H_
    3838
    39 #include <arch/types.h>
     39#include <typedefs.h>
    4040#include <arch/exception.h>
    4141
    4242/** Initial size of exception dispatch table. */
    43 #define IVT_ITEMS       6
     43#define IVT_ITEMS  6
    4444
    4545/** Index of the first item in exception dispatch table. */
    46 #define IVT_FIRST       0
    47 
     46#define IVT_FIRST  0
    4847
    4948extern void interrupt_init(void);
    … …  
    5251extern void interrupts_restore(ipl_t ipl);
    5352extern ipl_t interrupts_read(void);
    54 
     53extern bool interrupts_disabled(void);
    5554
    5655#endif

  • kernel/arch/arm32/include/mach/integratorcp/integratorcp.h

    r24a2517 rc621f4aa  
    3636 */
    3737
    38 #ifndef KERN_arm32_MACHINE_H_
    39 #define KERN_arm32_MACHINE_H_
     38#ifndef KERN_arm32_icp_H_
     39#define KERN_arm32_icp_H_
    4040
    4141#include <arch/machine_func.h>
    … …  
    102102extern void icp_timer_irq_start(void);
    103103extern void icp_cpu_halt(void);
    104 extern void icp_irq_exception(int exc_no, istate_t *istate);
    105 extern uintptr_t icp_get_memory_size(void);
     104extern void icp_irq_exception(unsigned int, istate_t *);
     105extern void icp_get_memory_extents(uintptr_t *, uintptr_t *);
    106106extern void icp_frame_init(void);
     107
     108extern struct arm_machine_ops icp_machine_ops;
     109
     110/** Size of IntegratorCP IRQ number range (starting from 0) */
     111#define ICP_IRQ_COUNT 8
    107112
    108113#endif

  • kernel/arch/arm32/include/mach/testarm/testarm.h

    r24a2517 rc621f4aa  
    3737 */
    3838
    39 #ifndef KERN_arm32_MACHINE_H_
    40 #define KERN_arm32_MACHINE_H_
     39#ifndef KERN_arm32_testarm_H_
     40#define KERN_arm32_testarm_H_
    4141
    4242#include <arch/machine_func.h>
    4343
    44 /** Last interrupt number (beginning from 0) whose status is probed
    45  * from interrupt controller
    46  */
    47 #define GXEMUL_IRQC_MAX_IRQ  8
    48 #define GXEMUL_KBD_IRQ       2
    49 #define GXEMUL_TIMER_IRQ     4
     44/** Size of GXemul IRQ number range (starting from 0) */
     45#define GXEMUL_IRQ_COUNT        32
     46#define GXEMUL_KBD_IRQ          2
     47#define GXEMUL_TIMER_IRQ        4
    5048
    5149/** Timer frequency */
    … …  
    7270extern void gxemul_timer_irq_start(void);
    7371extern void gxemul_cpu_halt(void);
    74 extern void gxemul_irq_exception(int exc_no, istate_t *istate);
    75 extern uintptr_t gxemul_get_memory_size(void);
     72extern void gxemul_irq_exception(unsigned int, istate_t *);
     73extern void gxemul_get_memory_extents(uintptr_t *, uintptr_t *);
    7674extern void gxemul_frame_init(void);
    7775
     76extern struct arm_machine_ops gxemul_machine_ops;
    7877
    7978#endif

  • kernel/arch/arm32/include/machine_func.h

    r24a2517 rc621f4aa  
    4343
    4444#include <console/console.h>
    45 #include <arch/types.h>
     45#include <typedefs.h>
    4646#include <arch/exception.h>
    4747
    48 #define MACHINE_GENFUNC machine_genfunc
    49 
    5048struct arm_machine_ops {
    51         void            (*machine_init)(void);
    52         void            (*machine_timer_irq_start)(void);
    53         void            (*machine_cpu_halt)(void);
    54         uintptr_t       (*machine_get_memory_size)(void);
    55         void            (*machine_irq_exception)(int, istate_t*);
    56         void            (*machine_frame_init)(void);
    57         void            (*machine_output_init)(void);
    58         void            (*machine_input_init)(void);
     49        void (*machine_init)(void);
     50        void (*machine_timer_irq_start)(void);
     51        void (*machine_cpu_halt)(void);
     52        void (*machine_get_memory_extents)(uintptr_t *, uintptr_t *);
     53        void (*machine_irq_exception)(unsigned int, istate_t *);
     54        void (*machine_frame_init)(void);
     55        void (*machine_output_init)(void);
     56        void (*machine_input_init)(void);
    5957};
    6058
    61 extern struct arm_machine_ops machine_ops;
     59/** Pointer to arm_machine_ops structure being used. */
     60extern struct arm_machine_ops *machine_ops;
    6261
     62/** Initialize machine_ops pointer. */
     63extern void machine_ops_init(void);
    6364
    6465/** Maps HW devices to the kernel address space using #hw_map. */
    … …  
    7374extern void machine_cpu_halt(void);
    7475
    75 
    76 /** Returns size of available memory.
     76/** Get extents of available memory.
    7777 *
    78  *  @return Size of available memory.
     78 * @param start         Place to store memory start address.
     79 * @param size          Place to store memory size.
    7980 */
    80 extern uintptr_t machine_get_memory_size(void);
    81 
     81extern void machine_get_memory_extents(uintptr_t *start, uintptr_t *size);
    8282
    8383/** Interrupt exception handler.
    … …  
    8686 * @param istate Saved processor state.
    8787 */
    88 extern void machine_irq_exception(int exc_no, istate_t *istate);
     88extern void machine_irq_exception(unsigned int exc_no, istate_t *istate);
    8989
    9090
    … …  
    104104extern void machine_input_init(void);
    105105
    106 extern void machine_genfunc(void);
     106extern size_t machine_get_irq_count(void);
     107
    107108#endif
    108109

  • kernel/arch/arm32/include/memstr.h

    r24a2517 rc621f4aa  
    2727 */
    2828
    29 /** @addtogroup arm32   
     29/** @addtogroup arm32
    3030 * @{
    3131 */
    … …  
    3939#define memcpy(dst, src, cnt)  __builtin_memcpy((dst), (src), (cnt))
    4040
    41 extern void memsetw(void *dst, size_t cnt, uint16_t x);
    42 extern void memsetb(void *dst, size_t cnt, uint8_t x);
    43 
    44 extern int memcmp(const void *a, const void *b, size_t cnt);
     41extern void memsetw(void *, size_t, uint16_t);
     42extern void memsetb(void *, size_t, uint8_t);
    4543
    4644#endif

  • kernel/arch/arm32/include/mm/asid.h

    r24a2517 rc621f4aa  
    3939#define KERN_arm32_ASID_H_
    4040
    41 #include <arch/types.h>
     41#include <typedefs.h>
    4242
    4343#define ASID_MAX_ARCH           3       /* minimal required number */

  • kernel/arch/arm32/include/mm/frame.h

    r24a2517 rc621f4aa  
    4343#ifndef __ASM__
    4444
    45 #include <arch/types.h>
     45#include <typedefs.h>
    4646
    4747#define BOOT_PAGE_TABLE_SIZE     0x4000
    48 #define BOOT_PAGE_TABLE_ADDRESS  0x4000
     48
     49#ifdef MACHINE_gta02
     50#define BOOT_PAGE_TABLE_ADDRESS  0x30010000
     51#else
     52#define BOOT_PAGE_TABLE_ADDRESS  0x00008000
     53#endif
    4954
    5055#define BOOT_PAGE_TABLE_START_FRAME     (BOOT_PAGE_TABLE_ADDRESS >> FRAME_WIDTH)
    5156#define BOOT_PAGE_TABLE_SIZE_IN_FRAMES  (BOOT_PAGE_TABLE_SIZE >> FRAME_WIDTH)
     57
     58#ifdef MACHINE_gta02
     59#define PHYSMEM_START_ADDR      0x30008000
     60#else
     61#define PHYSMEM_START_ADDR      0x00000000
     62#endif
    5263
    5364extern uintptr_t last_frame;

  • kernel/arch/arm32/include/mm/page.h

    r24a2517 rc621f4aa  
    2727 */
    2828
    29 /** @addtogroup arm32mm 
     29/** @addtogroup arm32mm
    3030 * @{
    3131 */
    … …  
    4040#include <mm/mm.h>
    4141#include <arch/exception.h>
     42#include <trace.h>
    4243
    4344#define PAGE_WIDTH      FRAME_WIDTH
    … …  
    192193/** Sets the address of level 0 page table.
    193194 *
    194  * @param pt    Pointer to the page table to set.
    195  */   
    196 static inline void set_ptl0_addr(pte_t *pt)
     195 * @param pt Pointer to the page table to set.
     196 *
     197 */
     198NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
    197199{
    198200        asm volatile (
    … …  
    205207/** Returns level 0 page table entry flags.
    206208 *
    207  *  @param pt     Level 0 page table.
    208  *  @param i      Index of the entry to return.
    209  */
    210 static inline int get_pt_level0_flags(pte_t *pt, size_t i)
     209 * @param pt Level 0 page table.
     210 * @param i  Index of the entry to return.
     211 *
     212 */
     213NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i)
    211214{
    212215        pte_level0_t *p = &pt[i].l0;
    213216        int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT);
    214 
     217       
    215218        return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) |
    216219            (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) |
    … …  
    220223/** Returns level 1 page table entry flags.
    221224 *
    222  *  @param pt     Level 1 page table.
    223  *  @param i      Index of the entry to return.
    224  */
    225 static inline int get_pt_level1_flags(pte_t *pt, size_t i)
     225 * @param pt Level 1 page table.
     226 * @param i  Index of the entry to return.
     227 *
     228 */
     229NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i)
    226230{
    227231        pte_level1_t *p = &pt[i].l1;
    228 
     232       
    229233        int dt = p->descriptor_type;
    230234        int ap = p->access_permission_0;
    231 
     235       
    232236        return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) |
    233237            ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) |
    … …  
    241245}
    242246
    243 
    244247/** Sets flags of level 0 page table entry.
    245248 *
    246  *  @param pt     level 0 page table
    247  *  @param i      index of the entry to be changed
    248  *  @param flags  new flags
    249  */
    250 static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
     249 * @param pt    level 0 page table
     250 * @param i     index of the entry to be changed
     251 * @param flags new flags
     252 *
     253 */
     254NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
    251255{
    252256        pte_level0_t *p = &pt[i].l0;
    253 
     257       
    254258        if (flags & PAGE_NOT_PRESENT) {
    255259                p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
    … …  
    262266                p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
    263267                p->should_be_zero = 0;
    264     }
     268        }
    265269}
    266270
    … …  
    268272/** Sets flags of level 1 page table entry.
    269273 *
    270  *  We use same access rights for the whole page. When page is not preset we
    271  *  store 1 in acess_rigts_3 so that at least one bit is 1 (to mark correct
    272  *  page entry, see #PAGE_VALID_ARCH).
    273  *
    274  *  @param pt     Level 1 page table.
    275  *  @param i      Index of the entry to be changed.
    276  *  @param flags  New flags.
    277  */ 
    278 static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
     274 * We use same access rights for the whole page. When page
     275 * is not preset we store 1 in acess_rigts_3 so that at least
     276 * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH).
     277 *
     278 * @param pt    Level 1 page table.
     279 * @param i     Index of the entry to be changed.
     280 * @param flags New flags.
     281 *
     282 */
     283NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
    279284{
    280285        pte_level1_t *p = &pt[i].l1;
    … …  
    287292                p->access_permission_3 = p->access_permission_0;
    288293        }
    289  
     294       
    290295        p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
    291 
     296       
    292297        /* default access permission */
    293298        p->access_permission_0 = p->access_permission_1 =
    294299            p->access_permission_2 = p->access_permission_3 =
    295300            PTE_AP_USER_NO_KERNEL_RW;
    296 
     301       
    297302        if (flags & PAGE_USER)  {
    298303                if (flags & PAGE_READ) {

  • kernel/arch/arm32/include/mm/page_fault.h

    r24a2517 rc621f4aa  
    3737#define KERN_arm32_PAGE_FAULT_H_
    3838
    39 #include <arch/types.h>
     39#include <typedefs.h>
    4040
    4141
    … …  
    8181} instruction_union_t;
    8282
    83 extern void prefetch_abort(int n, istate_t *istate);
    84 extern void data_abort(int n, istate_t *istate);
     83extern void prefetch_abort(unsigned int, istate_t *);
     84extern void data_abort(unsigned int, istate_t *);
    8585
    8686#endif

  • kernel/arch/arm32/include/mm/tlb.h

    r24a2517 rc621f4aa  
    2727 */
    2828
    29 /** @addtogroup arm32mm 
     29/** @addtogroup arm32mm
    3030 * @{
    3131 */

  • kernel/arch/arm32/include/ras.h

    r24a2517 rc621f4aa  
    11/*
    2  * Copyright (c) 2009 Jakub Jermar 
     2 * Copyright (c) 2009 Jakub Jermar
    33 * All rights reserved.
    44 *
    … …  
    3838
    3939#include <arch/exception.h>
    40 #include <arch/types.h>
     40#include <typedefs.h>
    4141
    42 #define RAS_START       0
    43 #define RAS_END         1
     42#define RAS_START  0
     43#define RAS_END    1
    4444
    4545extern uintptr_t *ras_page;
    4646
    4747extern void ras_init(void);
    48 extern void ras_check(int, istate_t *);
     48extern void ras_check(unsigned int, istate_t *);
    4949
    5050#endif

  • kernel/arch/arm32/include/types.h

    r24a2517 rc621f4aa  
    2727 */
    2828
    29 /** @addtogroup arm32   
     29/** @addtogroup arm32
    3030 * @{
    3131 */
    … …  
    3838
    3939#ifndef DOXYGEN
    40 #       define ATTRIBUTE_PACKED __attribute__ ((packed))
     40        #define ATTRIBUTE_PACKED __attribute__((packed))
    4141#else
    42 #       define ATTRIBUTE_PACKED
     42        #define ATTRIBUTE_PACKED
    4343#endif
    44 
    45 typedef signed char int8_t;
    46 typedef signed short int16_t;
    47 typedef signed long int32_t;
    48 typedef signed long long int64_t;
    49 
    50 typedef unsigned char uint8_t;
    51 typedef unsigned short uint16_t;
    52 typedef unsigned long uint32_t;
    53 typedef unsigned long long uint64_t;
    5444
    5545typedef uint32_t size_t;
    … …  
    6252typedef uint32_t unative_t;
    6353typedef int32_t native_t;
     54typedef uint32_t atomic_count_t;
    6455
    6556typedef struct {
    6657} fncptr_t;
    6758
    68 #define PRIp "x"        /**< Format for uintptr_t. */
    69 #define PRIs "u"        /**< Format for size_t. */
     59#define PRIp "x"  /**< Format for uintptr_t. */
     60#define PRIs "u"  /**< Format for size_t. */
    7061
    71 #define PRId8 "d"       /**< Format for int8_t. */
    72 #define PRId16 "d"      /**< Format for int16_t. */
    73 #define PRId32 "d"      /**< Format for int32_t. */
    74 #define PRId64 "lld"    /**< Format for int64_t. */
    75 #define PRIdn "d"       /**< Format for native_t. */
     62#define PRId8 "d"     /**< Format for int8_t. */
     63#define PRId16 "d"    /**< Format for int16_t. */
     64#define PRId32 "d"    /**< Format for int32_t. */
     65#define PRId64 "lld"  /**< Format for int64_t. */
     66#define PRIdn "d"     /**< Format for native_t. */
    7667
    77 #define PRIu8 "u"       /**< Format for uint8_t. */
    78 #define PRIu16 "u"      /**< Format for uint16_t. */
    79 #define PRIu32 "u"      /**< Format for uint32_t. */
    80 #define PRIu64 "llu"    /**< Format for uint64_t. */
    81 #define PRIun "u"       /**< Format for unative_t. */
     68#define PRIu8 "u"     /**< Format for uint8_t. */
     69#define PRIu16 "u"    /**< Format for uint16_t. */
     70#define PRIu32 "u"    /**< Format for uint32_t. */
     71#define PRIu64 "llu"  /**< Format for uint64_t. */
     72#define PRIun "u"     /**< Format for unative_t. */
    8273
    83 #define PRIx8 "x"       /**< Format for hexadecimal (u)int8_t. */
    84 #define PRIx16 "x"      /**< Format for hexadecimal (u)int16_t. */
    85 #define PRIx32 "x"      /**< Format for hexadecimal (u)uint32_t. */
    86 #define PRIx64 "llx"    /**< Format for hexadecimal (u)int64_t. */
    87 #define PRIxn "x"       /**< Format for hexadecimal (u)native_t. */
     74#define PRIx8 "x"     /**< Format for hexadecimal (u)int8_t. */
     75#define PRIx16 "x"    /**< Format for hexadecimal (u)int16_t. */
     76#define PRIx32 "x"    /**< Format for hexadecimal (u)uint32_t. */
     77#define PRIx64 "llx"  /**< Format for hexadecimal (u)int64_t. */
     78#define PRIxn "x"     /**< Format for hexadecimal (u)native_t. */
    8879
    8980#endif
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