Index: arch/sparc64/include/asm.h
===================================================================
--- arch/sparc64/include/asm.h	(revision adb2ebf8ae233e612225d6bd9fe2229d2b8e4d67)
+++ arch/sparc64/include/asm.h	(revision c52ed6bc86daeb4ee79fb46aff5c5062f818f3c2)
@@ -132,7 +132,6 @@
 static inline void asi_u64_write(asi_t asi, __address va, __u64 v)
 {
-	__asm__ volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" (asi));
+	__asm__ volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" (asi) : "memory");
 }
-
 
 void cpu_halt(void);
Index: arch/sparc64/include/barrier.h
===================================================================
--- arch/sparc64/include/barrier.h	(revision adb2ebf8ae233e612225d6bd9fe2229d2b8e4d67)
+++ arch/sparc64/include/barrier.h	(revision c52ed6bc86daeb4ee79fb46aff5c5062f818f3c2)
@@ -40,5 +40,15 @@
 #define write_barrier()
 
-#define flush()			__asm__ volatile ("flush\n" ::: "memory")
+/** Flush Instruction Memory. */
+static inline void flush(void)
+{
+	/*
+	 * The FLUSH instruction takes address parameter,
+	 * but JPS1 implementations are free to ignore it.
+	 * The only requirement is that it is a valid address
+	 * as it is passed to D-MMU.
+	 */
+        __asm__ volatile ("flush %sp\n");       /* %sp is guaranteed to reference mapped memory */
+}
 
 #endif
Index: arch/sparc64/include/mm/tlb.h
===================================================================
--- arch/sparc64/include/mm/tlb.h	(revision adb2ebf8ae233e612225d6bd9fe2229d2b8e4d67)
+++ arch/sparc64/include/mm/tlb.h	(revision c52ed6bc86daeb4ee79fb46aff5c5062f818f3c2)
@@ -32,4 +32,5 @@
 #include <arch/mm/tte.h>
 #include <arch/asm.h>
+#include <arch/barrier.h>
 #include <arch/types.h>
 #include <typedefs.h>
@@ -98,4 +99,5 @@
 };
 typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
+typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
 
 /** Read IMMU TLB Data Access Register.
@@ -135,5 +137,5 @@
  * @return Current value of specified IMMU TLB Tag Read Register.
  */
-static inline __u64 itlb_tag_read(index_t entry)
+static inline __u64 itlb_tag_read_read(index_t entry)
 {
 	tlb_tag_read_addr_t tag;
@@ -150,5 +152,5 @@
  * @return Current value of specified DMMU TLB Tag Read Register.
  */
-static inline __u64 dtlb_tag_read(index_t entry)
+static inline __u64 dtlb_tag_read_read(index_t entry)
 {
 	tlb_tag_read_addr_t tag;
@@ -159,3 +161,43 @@
 }
 
+/** Write IMMU TLB Tag Access Register.
+ *
+ * @param v Value to be written.
+ */
+static inline void itlb_tag_access_write(__u64 v)
+{
+	asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
+	flush();
+}
+
+/** Write DMMU TLB Tag Access Register.
+ *
+ * @param v Value to be written.
+ */
+static inline void dtlb_tag_access_write(__u64 v)
+{
+	asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
+	flush();
+}
+
+/** Write IMMU TLB Data in Register.
+ *
+ * @param v Value to be written.
+ */
+static inline void itlb_data_in_write(__u64 v)
+{
+	asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
+	flush();
+}
+
+/** Write DMMU TLB Data in Register.
+ *
+ * @param v Value to be written.
+ */
+static inline void dtlb_data_in_write(__u64 v)
+{
+	asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
+	flush();
+}
+
 #endif
Index: arch/sparc64/src/mm/tlb.c
===================================================================
--- arch/sparc64/src/mm/tlb.c	(revision adb2ebf8ae233e612225d6bd9fe2229d2b8e4d67)
+++ arch/sparc64/src/mm/tlb.c	(revision c52ed6bc86daeb4ee79fb46aff5c5062f818f3c2)
@@ -45,7 +45,7 @@
 	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
 		d.value = itlb_data_access_read(i);
-		t.value = itlb_tag_read(i);
+		t.value = itlb_tag_read_read(i);
 		
-		printf("%d: va=%X, context=%d, v=%d, size=%X, nfo=%d, ie=%d, soft2=%X, diag=%X, pa=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
+		printf("%d: va=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pa=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
 			i, t.va, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pa, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
 	}
@@ -54,7 +54,7 @@
 	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
 		d.value = dtlb_data_access_read(i);
-		t.value = dtlb_tag_read(i);
+		t.value = dtlb_tag_read_read(i);
 		
-		printf("%d: va=%X, context=%d, v=%d, size=%X, nfo=%d, ie=%d, soft2=%X, diag=%X, pa=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
+		printf("%d: va=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pa=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
 			i, t.va, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pa, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
 	}
