Index: kernel/arch/amd64/include/arch/mm/pat.h
===================================================================
--- kernel/arch/amd64/include/arch/mm/pat.h	(revision 74cb66109763c1d227d236094006a779dee50793)
+++ kernel/arch/amd64/include/arch/mm/pat.h	(revision c4ed9fac928b1683c3ccc7d35d520ec9962fe18a)
@@ -1,3 +1,4 @@
 /*
+ * Copyright (c) 2024 Jiri Svoboda
  * Copyright (c) 2024 Jiří Zárevúcky
  * All rights reserved.
@@ -50,4 +51,5 @@
 } pat_type_t;
 
+#ifndef PROCESSOR_i486
 /**
  * Assign caching type for a particular combination of PAT,
@@ -65,4 +67,5 @@
 	write_msr(MSR_IA32_PAT, r);
 }
+#endif
 
 static inline bool pat_supported(void)
Index: kernel/arch/ia32/src/ia32.c
===================================================================
--- kernel/arch/ia32/src/ia32.c	(revision 74cb66109763c1d227d236094006a779dee50793)
+++ kernel/arch/ia32/src/ia32.c	(revision c4ed9fac928b1683c3ccc7d35d520ec9962fe18a)
@@ -1,5 +1,5 @@
 /*
+ * Copyright (c) 2024 Jiri Svoboda
  * Copyright (c) 2001-2004 Jakub Jermar
- * Copyright (c) 2009 Jiri Svoboda
  * Copyright (c) 2009 Martin Decky
  * All rights reserved.
@@ -106,7 +106,9 @@
 	pm_init();
 
+#ifndef PROCESSOR_i486
 	/* Use PCD+PWT bit combination in PTE to mean write-combining mode. */
 	if (pat_supported())
 		pat_set_mapping(false, true, true, PAT_TYPE_WRITE_COMBINING);
+#endif
 
 	if (config.cpu_active == 1) {