Index: kernel/arch/arm32/include/cp15.h
===================================================================
--- kernel/arch/arm32/include/cp15.h	(revision 612edcab380c7fc950cf3a91c5d8a7f8d6f6a23b)
+++ kernel/arch/arm32/include/cp15.h	(revision c3213bb3f6a5677419c2d8e2c51be09891ee3ee2)
@@ -68,4 +68,48 @@
 };
 CONTROL_REG_GEN_READ(MIDR, c0, 0, c0, 0);
+
+enum {
+	CTR_FORMAT_MASK = 0xe0000000,
+	CTR_FORMAT_ARMv7 = 0x80000000,
+	CTR_FORMAT_ARMv6 = 0x00000000,
+	/* ARMv7 format */
+	CTR_CWG_MASK = 0xf,
+	CTR_CWG_SHIFT = 24,
+	CTR_ERG_MASK = 0xf,
+	CTR_ERG_SHIFT = 20,
+	CTR_D_MIN_LINE_MASK = 0xf,
+	CTR_D_MIN_LINE_SHIFT = 16,
+	CTR_I_MIN_LINE_MASK = 0xf,
+	CTR_I_MIN_LINE_SHIFT = 0,
+	CTR_L1I_POLICY_MASK = 0x0000c000,
+	VTR_L1I_POLICY_AIVIVT = 0x00004000,
+	VTR_L1I_POLICY_VIPT = 0x00008000,
+	CTR_L1I_POLICY_PIPT = 0x0000c000,
+	/* ARMv6 format */
+	CTR_CTYPE_MASK = 0x1e000000,
+	CTR_CTYPE_WT = 0x00000000,
+	CTR_CTYPE_WB_NL = 0x04000000,
+	CTR_CTYPE_WB_D = 0x0a000000,
+	CTR_CTYPE_WB_A = 0x0c000000, /**< ARMv5- only */
+	CTR_CTYPE_WB_B = 0x0e000000, /**< ARMv5- only */
+	CTR_CTYPE_WB_C = 0x1c000000,
+	CTR_SEP_FLAG = 1 << 24,
+	CTR_DCACHE_P_FLAG = 1 << 23,
+	CTR_DCACHE_SIZE_MASK = 0xf,
+	CTR_DCACHE_SIZE_SHIFT = 18,
+	CTR_DCACHE_ASSOC_MASK = 0x7,
+	CTR_DCACHE_ASSOC_SHIFT = 15,
+	CTR_DCACHE_M_FLAG = 1 << 14,
+	CTR_DCACHE_LEN_MASK = 0x3,
+	CTR_DCACHE_LEN_SHIFT = 0,
+	CTR_ICACHE_P_FLAG = 1 << 11,
+	CTR_ICACHE_SIZE_MASK = 0xf,
+	CTR_ICACHE_SIZE_SHIFT = 6,
+	CTR_ICACHE_ASSOC_MASK = 0x7,
+	CTR_ICACHE_ASSOC_SHIFT = 3,
+	CTR_ICACHE_M_FLAG = 1 << 2,
+	CTR_ICACHE_LEN_MASK = 0x3,
+	CTR_ICACHE_LEN_SHIFT = 0,
+};
 CONTROL_REG_GEN_READ(CTR, c0, 0, c0, 1);
 CONTROL_REG_GEN_READ(TCMR, c0, 0, c0, 2);