Index: kernel/arch/sparc64/Makefile.inc =================================================================== --- kernel/arch/sparc64/Makefile.inc (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/Makefile.inc (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -75,5 +75,4 @@ arch/$(KARCH)/src/dummy.s \ arch/$(KARCH)/src/mm/$(USARCH)/as.c \ - arch/$(KARCH)/src/mm/cache.S \ arch/$(KARCH)/src/mm/$(USARCH)/frame.c \ arch/$(KARCH)/src/mm/page.c \ @@ -94,4 +93,9 @@ arch/$(KARCH)/src/drivers/pci.c \ arch/$(KARCH)/src/drivers/fhc.c + +ifeq ($(USARCH),sun4u) + ARCH_SOURCES += \ + arch/$(KARCH)/src/mm/cache.S +endif ifeq ($(USARCH),sun4v) Index: kernel/arch/sparc64/include/mm/as.h =================================================================== --- kernel/arch/sparc64/include/mm/as.h (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/include/mm/as.h (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -36,58 +36,9 @@ #define KERN_sparc64_AS_H_ -#include - -#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 1 - -#define KERNEL_ADDRESS_SPACE_START_ARCH (unsigned long) 0x0000000000000000 -#define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffffffffffff -#define USER_ADDRESS_SPACE_START_ARCH (unsigned long) 0x0000000000000000 -#define USER_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffffffffffff - -#define USTACK_ADDRESS_ARCH (0xffffffffffffffffULL - (PAGE_SIZE - 1)) - -#ifdef CONFIG_TSB - -/** TSB Tag Target register. */ -typedef union tsb_tag_target { - uint64_t value; - struct { - unsigned invalid : 1; /**< Invalidated by software. */ - unsigned : 2; - unsigned context : 13; /**< Software ASID. */ - unsigned : 6; - uint64_t va_tag : 42; /**< Virtual address bits <63:22>. */ - } __attribute__ ((packed)); -} tsb_tag_target_t; - -/** TSB entry. */ -typedef struct tsb_entry { - tsb_tag_target_t tag; - tte_data_t data; -} __attribute__ ((packed)) tsb_entry_t; - -typedef struct { - tsb_entry_t *itsb; - tsb_entry_t *dtsb; -} as_arch_t; - -#else - -typedef struct { -} as_arch_t; - -#endif /* CONFIG_TSB */ - -#include - -#ifdef CONFIG_TSB -#include -#define as_invalidate_translation_cache(as, page, cnt) \ - tsb_invalidate((as), (page), (cnt)) -#else -#define as_invalidate_translation_cache(as, page, cnt) +#if defined (SUN4U) +#include +#elif defined (SUN4V) +#include #endif - -extern void as_arch_init(void); #endif Index: kernel/arch/sparc64/include/mm/sun4u/as.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4u/as.h (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) +++ kernel/arch/sparc64/include/mm/sun4u/as.h (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4u_AS_H_ +#define KERN_sparc64_sun4u_AS_H_ + +#include + +#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 1 + +#define KERNEL_ADDRESS_SPACE_START_ARCH (unsigned long) 0x0000000000000000 +#define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffffffffffff +#define USER_ADDRESS_SPACE_START_ARCH (unsigned long) 0x0000000000000000 +#define USER_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffffffffffff + +#define USTACK_ADDRESS_ARCH (0xffffffffffffffffULL - (PAGE_SIZE - 1)) + +#ifdef CONFIG_TSB + +/** TSB Tag Target register. */ +typedef union tsb_tag_target { + uint64_t value; + struct { + unsigned invalid : 1; /**< Invalidated by software. */ + unsigned : 2; + unsigned context : 13; /**< Software ASID. */ + unsigned : 6; + uint64_t va_tag : 42; /**< Virtual address bits <63:22>. */ + } __attribute__ ((packed)); +} tsb_tag_target_t; + +/** TSB entry. */ +typedef struct tsb_entry { + tsb_tag_target_t tag; + tte_data_t data; +} __attribute__ ((packed)) tsb_entry_t; + +typedef struct { + tsb_entry_t *itsb; + tsb_entry_t *dtsb; +} as_arch_t; + +#else + +typedef struct { +} as_arch_t; + +#endif /* CONFIG_TSB */ + +#include + +#ifdef CONFIG_TSB +#include +#define as_invalidate_translation_cache(as, page, cnt) \ + tsb_invalidate((as), (page), (cnt)) +#else +#define as_invalidate_translation_cache(as, page, cnt) +#endif + +extern void as_arch_init(void); + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/mm/sun4u/tlb.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4u/tlb.h (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/include/mm/sun4u/tlb.h (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -684,4 +684,5 @@ extern void dump_sfsr_and_sfar(void); +extern void describe_dmmu_fault(void); #endif /* !def __ASM__ */ Index: kernel/arch/sparc64/include/mm/sun4u/tsb.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4u/tsb.h (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) +++ kernel/arch/sparc64/include/mm/sun4u/tsb.h (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4u_TSB_H_ +#define KERN_sparc64_sun4u_TSB_H_ + +/* + * ITSB abd DTSB will claim 64K of memory, which + * is a nice number considered that it is one of + * the page sizes supported by hardware, which, + * again, is nice because TSBs need to be locked + * in TLBs - only one TLB entry will do. + */ +#define TSB_SIZE 2 /* when changing this, change + * as.c as well */ +#define ITSB_ENTRY_COUNT (512 * (1 << TSB_SIZE)) +#define DTSB_ENTRY_COUNT (512 * (1 << TSB_SIZE)) + +#define TSB_TAG_TARGET_CONTEXT_SHIFT 48 + +#ifndef __ASM__ + +#include +#include +#include + +/** TSB Base register. */ +typedef union tsb_base_reg { + uint64_t value; + struct { + uint64_t base : 51; /**< TSB base address, bits 63:13. */ + unsigned split : 1; /**< Split vs. common TSB for 8K and 64K + * pages. HelenOS uses only 8K pages + * for user mappings, so we always set + * this to 0. + */ + unsigned : 9; + unsigned size : 3; /**< TSB size. Number of entries is + * 512 * 2^size. */ + } __attribute__ ((packed)); +} tsb_base_reg_t; + +/** Read ITSB Base register. + * + * @return Content of the ITSB Base register. + */ +static inline uint64_t itsb_base_read(void) +{ + return asi_u64_read(ASI_IMMU, VA_IMMU_TSB_BASE); +} + +/** Read DTSB Base register. + * + * @return Content of the DTSB Base register. + */ +static inline uint64_t dtsb_base_read(void) +{ + return asi_u64_read(ASI_DMMU, VA_DMMU_TSB_BASE); +} + +/** Write ITSB Base register. + * + * @param v New content of the ITSB Base register. + */ +static inline void itsb_base_write(uint64_t v) +{ + asi_u64_write(ASI_IMMU, VA_IMMU_TSB_BASE, v); +} + +/** Write DTSB Base register. + * + * @param v New content of the DTSB Base register. + */ +static inline void dtsb_base_write(uint64_t v) +{ + asi_u64_write(ASI_DMMU, VA_DMMU_TSB_BASE, v); +} + +#if defined (US3) + +/** Write DTSB Primary Extension register. + * + * @param v New content of the DTSB Primary Extension register. + */ +static inline void dtsb_primary_extension_write(uint64_t v) +{ + asi_u64_write(ASI_DMMU, VA_DMMU_PRIMARY_EXTENSION, v); +} + +/** Write DTSB Secondary Extension register. + * + * @param v New content of the DTSB Secondary Extension register. + */ +static inline void dtsb_secondary_extension_write(uint64_t v) +{ + asi_u64_write(ASI_DMMU, VA_DMMU_SECONDARY_EXTENSION, v); +} + +/** Write DTSB Nucleus Extension register. + * + * @param v New content of the DTSB Nucleus Extension register. + */ +static inline void dtsb_nucleus_extension_write(uint64_t v) +{ + asi_u64_write(ASI_DMMU, VA_DMMU_NUCLEUS_EXTENSION, v); +} + +/** Write ITSB Primary Extension register. + * + * @param v New content of the ITSB Primary Extension register. + */ +static inline void itsb_primary_extension_write(uint64_t v) +{ + asi_u64_write(ASI_IMMU, VA_IMMU_PRIMARY_EXTENSION, v); +} + +/** Write ITSB Nucleus Extension register. + * + * @param v New content of the ITSB Nucleus Extension register. + */ +static inline void itsb_nucleus_extension_write(uint64_t v) +{ + asi_u64_write(ASI_IMMU, VA_IMMU_NUCLEUS_EXTENSION, v); +} + +#endif + +/* Forward declarations. */ +struct as; +struct pte; + +extern void tsb_invalidate(struct as *as, uintptr_t page, size_t pages); +extern void itsb_pte_copy(struct pte *t, size_t index); +extern void dtsb_pte_copy(struct pte *t, size_t index, bool ro); + +#endif /* !def __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/mm/sun4v/frame.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4v/frame.h (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/include/mm/sun4v/frame.h (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -33,12 +33,7 @@ */ -#ifndef KERN_sparc64_SUN4V_FRAME_H_ -#define KERN_sparc64_SUN4V_FRAME_H_ +#ifndef KERN_sparc64_sun4v_FRAME_H_ +#define KERN_sparc64_sun4v_FRAME_H_ -/* - * Page size supported by the MMU. - * For 8K there is the nasty illegal virtual aliasing problem. - * Therefore, the kernel uses 8K only internally on the TLB and TSB levels. - */ #define MMU_FRAME_WIDTH 13 /* 8K */ #define MMU_FRAME_SIZE (1 << MMU_FRAME_WIDTH) @@ -52,24 +47,5 @@ #include -union frame_address { - uintptr_t address; - struct { -#if defined (US) - unsigned : 23; - uint64_t pfn : 28; /**< Physical Frame Number. */ -#elif defined (US3) - unsigned : 21; - uint64_t pfn : 30; /**< Physical Frame Number. */ -#endif - unsigned offset : 13; /**< Offset. */ - } __attribute__ ((packed)); -}; - -typedef union frame_address frame_address_t; - extern uintptr_t last_frame; -//MH -//extern uintptr_t end_of_identity; - extern void frame_arch_init(void); #define physmem_print() Index: kernel/arch/sparc64/include/mm/sun4v/mmu.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4v/mmu.h (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/include/mm/sun4v/mmu.h (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -45,106 +45,4 @@ #define ASI_SECONDARY_CONTEXT_REG 0x21 /**< secondary context register ASI. */ - - - - - - - - - - -/* I-MMU ASIs. */ -#define ASI_IMMU 0x50 -#define ASI_IMMU_TSB_8KB_PTR_REG 0x51 -#define ASI_IMMU_TSB_64KB_PTR_REG 0x52 -#define ASI_ITLB_DATA_IN_REG 0x54 -#define ASI_ITLB_DATA_ACCESS_REG 0x55 -#define ASI_ITLB_TAG_READ_REG 0x56 -#define ASI_IMMU_DEMAP 0x57 - -/* Virtual Addresses within ASI_IMMU. */ -#define VA_IMMU_TSB_TAG_TARGET 0x0 /**< IMMU TSB tag target register. */ -#define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ -#define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ -#define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ -#if defined (US3) -#define VA_IMMU_PRIMARY_EXTENSION 0x48 /**< IMMU TSB primary extension register */ -#define VA_IMMU_NUCLEUS_EXTENSION 0x58 /**< IMMU TSB nucleus extension register */ -#endif - - -/* D-MMU ASIs. */ -#define ASI_DMMU 0x58 -#define ASI_DMMU_TSB_8KB_PTR_REG 0x59 -#define ASI_DMMU_TSB_64KB_PTR_REG 0x5a -#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b -#define ASI_DTLB_DATA_IN_REG 0x5c -#define ASI_DTLB_DATA_ACCESS_REG 0x5d -#define ASI_DTLB_TAG_READ_REG 0x5e -#define ASI_DMMU_DEMAP 0x5f - -/* Virtual Addresses within ASI_DMMU. */ -#define VA_DMMU_TSB_TAG_TARGET 0x0 /**< DMMU TSB tag target register. */ -#define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ -#define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ -#define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ -#define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ -#define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ -#define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ -#define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ -#define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ -#if defined (US3) -#define VA_DMMU_PRIMARY_EXTENSION 0x48 /**< DMMU TSB primary extension register */ -#define VA_DMMU_SECONDARY_EXTENSION 0x50 /**< DMMU TSB secondary extension register */ -#define VA_DMMU_NUCLEUS_EXTENSION 0x58 /**< DMMU TSB nucleus extension register */ -#endif - -#ifndef __ASM__ - -#include -#include -#include - -#if defined(US) -/** LSU Control Register. */ -typedef union { - uint64_t value; - struct { - unsigned : 23; - unsigned pm : 8; - unsigned vm : 8; - unsigned pr : 1; - unsigned pw : 1; - unsigned vr : 1; - unsigned vw : 1; - unsigned : 1; - unsigned fm : 16; - unsigned dm : 1; /**< D-MMU enable. */ - unsigned im : 1; /**< I-MMU enable. */ - unsigned dc : 1; /**< D-Cache enable. */ - unsigned ic : 1; /**< I-Cache enable. */ - - } __attribute__ ((packed)); -} lsu_cr_reg_t; -#endif /* US */ - -#endif /* !def __ASM__ */ - - - - - - - - - - - - - - - - #endif Index: kernel/arch/sparc64/include/mm/sun4v/tsb.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4v/tsb.h (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/include/mm/sun4v/tsb.h (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -71,5 +71,5 @@ struct pte; -extern void tsb_invalidate(struct as *as, uintptr_t page, count_t pages); +extern void tsb_invalidate(struct as *as, uintptr_t page, uint64_t pages); extern void itsb_pte_copy(struct pte *t); extern void dtsb_pte_copy(struct pte *t, bool ro); Index: kernel/arch/sparc64/include/mm/tlb.h =================================================================== --- kernel/arch/sparc64/include/mm/tlb.h (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/include/mm/tlb.h (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -36,4 +36,5 @@ #define KERN_sparc64_TLB_H_ + #if defined (SUN4U) #include Index: kernel/arch/sparc64/include/mm/tsb.h =================================================================== --- kernel/arch/sparc64/include/mm/tsb.h (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/include/mm/tsb.h (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -36,134 +36,9 @@ #define KERN_sparc64_TSB_H_ -/* - * ITSB abd DTSB will claim 64K of memory, which - * is a nice number considered that it is one of - * the page sizes supported by hardware, which, - * again, is nice because TSBs need to be locked - * in TLBs - only one TLB entry will do. - */ -#define TSB_SIZE 2 /* when changing this, change - * as.c as well */ -#define ITSB_ENTRY_COUNT (512 * (1 << TSB_SIZE)) -#define DTSB_ENTRY_COUNT (512 * (1 << TSB_SIZE)) - -#define TSB_TAG_TARGET_CONTEXT_SHIFT 48 - -#ifndef __ASM__ - -#include -#include -#include - -/** TSB Base register. */ -typedef union tsb_base_reg { - uint64_t value; - struct { - uint64_t base : 51; /**< TSB base address, bits 63:13. */ - unsigned split : 1; /**< Split vs. common TSB for 8K and 64K - * pages. HelenOS uses only 8K pages - * for user mappings, so we always set - * this to 0. - */ - unsigned : 9; - unsigned size : 3; /**< TSB size. Number of entries is - * 512 * 2^size. */ - } __attribute__ ((packed)); -} tsb_base_reg_t; - -/** Read ITSB Base register. - * - * @return Content of the ITSB Base register. - */ -static inline uint64_t itsb_base_read(void) -{ - return asi_u64_read(ASI_IMMU, VA_IMMU_TSB_BASE); -} - -/** Read DTSB Base register. - * - * @return Content of the DTSB Base register. - */ -static inline uint64_t dtsb_base_read(void) -{ - return asi_u64_read(ASI_DMMU, VA_DMMU_TSB_BASE); -} - -/** Write ITSB Base register. - * - * @param v New content of the ITSB Base register. - */ -static inline void itsb_base_write(uint64_t v) -{ - asi_u64_write(ASI_IMMU, VA_IMMU_TSB_BASE, v); -} - -/** Write DTSB Base register. - * - * @param v New content of the DTSB Base register. - */ -static inline void dtsb_base_write(uint64_t v) -{ - asi_u64_write(ASI_DMMU, VA_DMMU_TSB_BASE, v); -} - -#if defined (US3) - -/** Write DTSB Primary Extension register. - * - * @param v New content of the DTSB Primary Extension register. - */ -static inline void dtsb_primary_extension_write(uint64_t v) -{ - asi_u64_write(ASI_DMMU, VA_DMMU_PRIMARY_EXTENSION, v); -} - -/** Write DTSB Secondary Extension register. - * - * @param v New content of the DTSB Secondary Extension register. - */ -static inline void dtsb_secondary_extension_write(uint64_t v) -{ - asi_u64_write(ASI_DMMU, VA_DMMU_SECONDARY_EXTENSION, v); -} - -/** Write DTSB Nucleus Extension register. - * - * @param v New content of the DTSB Nucleus Extension register. - */ -static inline void dtsb_nucleus_extension_write(uint64_t v) -{ - asi_u64_write(ASI_DMMU, VA_DMMU_NUCLEUS_EXTENSION, v); -} - -/** Write ITSB Primary Extension register. - * - * @param v New content of the ITSB Primary Extension register. - */ -static inline void itsb_primary_extension_write(uint64_t v) -{ - asi_u64_write(ASI_IMMU, VA_IMMU_PRIMARY_EXTENSION, v); -} - -/** Write ITSB Nucleus Extension register. - * - * @param v New content of the ITSB Nucleus Extension register. - */ -static inline void itsb_nucleus_extension_write(uint64_t v) -{ - asi_u64_write(ASI_IMMU, VA_IMMU_NUCLEUS_EXTENSION, v); -} - +#if defined (SUN4U) +#include +#elif defined (SUN4V) +#include #endif - -/* Forward declarations. */ -struct as; -struct pte; - -extern void tsb_invalidate(struct as *as, uintptr_t page, size_t pages); -extern void itsb_pte_copy(struct pte *t, size_t index); -extern void dtsb_pte_copy(struct pte *t, size_t index, bool ro); - -#endif /* !def __ASM__ */ #endif Index: kernel/arch/sparc64/include/sun4v/arch.h =================================================================== --- kernel/arch/sparc64/include/sun4v/arch.h (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/include/sun4v/arch.h (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -58,9 +58,4 @@ #define SCRATCHPAD_WBUF 0x18 -//MH - remove when cpu.h is forked -#define ASI_NUCLEUS_QUAD_LDD 0x24 /** ASI for 16-byte atomic loads. */ -#define ASI_DCACHE_TAG 0x47 /** ASI D-Cache Tag. */ -#define ASI_ICBUS_CONFIG 0x4a /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */ - #endif Index: kernel/arch/sparc64/include/sun4v/hypercall.h =================================================================== --- kernel/arch/sparc64/include/sun4v/hypercall.h (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/include/sun4v/hypercall.h (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -81,5 +81,5 @@ #define EBADPGSZ 4 /**< Invalid pagesize encoding */ #define EBADTSB 5 /**< Invalid TSB description */ -#define EINVAL 6 /**< Invalid argument */ +#define HV_EINVAL 6 /**< Invalid argument */ #define EBADTRAP 7 /**< Invalid function number */ #define EBADALIGN 8 /**< Invalid address alignment */ @@ -92,5 +92,5 @@ #define ETOOMANY 15 /**< Too many items specified / limit reached */ #define ECHANNEL 16 /**< Invalid LDC channel */ -#define EBUSY 17 /**< Operation failed as resource is otherwise busy */ +#define HV_EBUSY 17 /**< Operation failed as resource is otherwise busy */ Index: kernel/arch/sparc64/include/trap/exception.h =================================================================== --- kernel/arch/sparc64/include/trap/exception.h (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/include/trap/exception.h (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -38,9 +38,16 @@ #define TT_INSTRUCTION_ACCESS_EXCEPTION 0x08 +#define TT_INSTRUCTION_ACCESS_MMU_MISS 0x09 #define TT_INSTRUCTION_ACCESS_ERROR 0x0a +#define TT_IAE_UNAUTH_ACCESS 0x0b +#define TT_IAE_NFO_PAGE 0x0c #define TT_ILLEGAL_INSTRUCTION 0x10 #define TT_PRIVILEGED_OPCODE 0x11 #define TT_UNIMPLEMENTED_LDD 0x12 #define TT_UNIMPLEMENTED_STD 0x13 +#define TT_DAE_INVALID_ASI 0x14 +#define TT_DAE_PRIVILEGE_VIOLATION 0x15 +#define TT_DAE_NC_PAGE 0x16 +#define TT_DAE_NFO_PAGE 0x17 #define TT_FP_DISABLED 0x20 #define TT_FP_EXCEPTION_IEEE_754 0x21 @@ -49,4 +56,5 @@ #define TT_DIVISION_BY_ZERO 0x28 #define TT_DATA_ACCESS_EXCEPTION 0x30 +#define TT_DATA_ACCESS_MMU_MISS 0x31 #define TT_DATA_ACCESS_ERROR 0x32 #define TT_MEM_ADDRESS_NOT_ALIGNED 0x34 Index: kernel/arch/sparc64/include/trap/sun4v/mmu.h =================================================================== --- kernel/arch/sparc64/include/trap/sun4v/mmu.h (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/include/trap/sun4v/mmu.h (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -36,6 +36,6 @@ */ -#ifndef KERN_sparc64_SUN4V_MMU_TRAP_H_ -#define KERN_sparc64_SUN4V_MMU_TRAP_H_ +#ifndef KERN_sparc64_sun4v_MMU_TRAP_H_ +#define KERN_sparc64_sun4v_MMU_TRAP_H_ #include @@ -121,8 +121,7 @@ * but this time its handler accesse memory which IS mapped. */ -0: -.if (\tl > 0) - wrpr %g0, 1, %tl -.endif + .if (\tl > 0) + wrpr %g0, 1, %tl + .endif /* Index: kernel/arch/sparc64/include/trap/trap_table.h =================================================================== --- kernel/arch/sparc64/include/trap/trap_table.h (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/include/trap/trap_table.h (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -101,5 +101,5 @@ .macro PREEMPTIBLE_HANDLER f sethi %hi(\f), %g1 - ba %xcc, preemptible_handler + b preemptible_handler or %g1, %lo(\f), %g1 .endm Index: kernel/arch/sparc64/src/cpu/sun4v/cpu.c =================================================================== --- kernel/arch/sparc64/src/cpu/sun4v/cpu.c (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/src/cpu/sun4v/cpu.c (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -1,4 +1,5 @@ /* * Copyright (c) 2005 Jakub Jermar + * Copyright (c) 2009 Pavel Rimsky * All rights reserved. * @@ -51,6 +52,5 @@ __hypercall_fast_ret1(0, 0, 0, 0, 0, CPU_MYID, &myid); - //MH - //CPU->arch.id = myid; + CPU->arch.id = myid; md_node_t node = md_get_root(); Index: kernel/arch/sparc64/src/drivers/niagara.c =================================================================== --- kernel/arch/sparc64/src/drivers/niagara.c (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/src/drivers/niagara.c (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -111,4 +111,7 @@ static void niagara_putchar(outdev_t *dev, const wchar_t ch, bool silent) { + if (silent) + return; + do_putchar(ch); if (ch == '\n') Index: kernel/arch/sparc64/src/mm/sun4u/tlb.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4u/tlb.c (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/src/mm/sun4u/tlb.c (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -476,5 +476,5 @@ } -void dump_sfsr_and_sfar(void) +void describe_dmmu_fault(void) { tlb_sfsr_reg_t sfsr; @@ -499,4 +499,27 @@ } +void dump_sfsr_and_sfar(void) +{ + tlb_sfsr_reg_t sfsr; + uintptr_t sfar; + + sfsr.value = dtlb_sfsr_read(); + sfar = dtlb_sfar_read(); + +#if defined (US) + printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, " + "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, + sfsr.ow, sfsr.fv); +#elif defined (US3) + printf("DTLB SFSR: nf=%d, asi=%#x, tm=%d, ft=%#x, e=%d, ct=%d, pr=%d, " + "w=%d, ow=%d, fv=%d\n", sfsr.nf, sfsr.asi, sfsr.tm, sfsr.ft, + sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv); +#endif + + printf("DTLB SFAR: address=%p\n", sfar); + + dtlb_sfsr_write(0); +} + #if defined (US) /** Invalidate all unlocked ITLB and DTLB entries. */ Index: kernel/arch/sparc64/src/mm/sun4v/as.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4v/as.c (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/src/mm/sun4v/as.c (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -1,4 +1,5 @@ /* * Copyright (c) 2006 Jakub Jermar + * Copyright (c) 2009 Pavel Rimsky * All rights reserved. * @@ -34,4 +35,5 @@ #include +#include #include #include @@ -39,4 +41,5 @@ #include #include +#include #ifdef CONFIG_TSB @@ -86,5 +89,5 @@ { #ifdef CONFIG_TSB - count_t cnt = (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH; + size_t cnt = (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH; frame_free((uintptr_t) as->arch.tsb_description.tsb_base); return cnt; @@ -112,4 +115,23 @@ { mmu_secondary_context_write(as->asid); +#ifdef CONFIG_TSB + uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); + + ASSERT(as->arch.tsb_description.tsb_base); + uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base); + + if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { + /* + * TSBs were allocated from memory not covered + * by the locked 4M kernel DTLB entry. We need + * to map both TSBs explicitly. + */ + mmu_demap_page(tsb, 0, MMU_FLAG_DTLB); + dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true); + } + + __hypercall_fast2(MMU_TSB_CTXNON0, 1, KA2PA(&(as->arch.tsb_description))); + +#endif } @@ -134,7 +156,7 @@ uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); - ASSERT(as->arch.itsb && as->arch.dtsb); + ASSERT(as->arch.tsb_description.tsb_base); - uintptr_t tsb = (uintptr_t) as->arch.itsb; + uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base); if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { @@ -144,5 +166,5 @@ * to demap the entry installed by as_install_arch(). */ - dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); + __hypercall_fast3(MMU_UNMAP_PERM_ADDR, tsb, 0, MMU_FLAG_DTLB); } #endif Index: kernel/arch/sparc64/src/mm/sun4v/frame.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4v/frame.c (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/src/mm/sun4v/frame.c (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -41,6 +41,4 @@ #include -uintptr_t last_frame = NULL; - /** Create memory zones according to information stored in bootinfo. * @@ -68,6 +66,4 @@ SIZE2FRAMES(ALIGN_DOWN(size, FRAME_SIZE)), confdata, 0); - last_frame = max(last_frame, start + ALIGN_UP(size, - FRAME_SIZE)); } @@ -80,7 +76,4 @@ frame_mark_unavailable(ADDR2PFN(KA2PA(PFN2ADDR(0))), 1); } - -//MH -// end_of_identity = PA2KA(last_frame); } Index: kernel/arch/sparc64/src/mm/sun4v/tsb.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4v/tsb.c (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/src/mm/sun4v/tsb.c (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -1,4 +1,5 @@ /* * Copyright (c) 2006 Jakub Jermar + * Copyright (c) 2009 Pavel Rimsky * All rights reserved. * @@ -34,4 +35,5 @@ #include +#include #include #include @@ -49,30 +51,27 @@ * portions of both TSBs are invalidated at a time. * - * @param as Address space. - * @param page First page to invalidate in TSB. - * @param pages Number of pages to invalidate. Value of (size_t) -1 means the - * whole TSB. + * @param as Address space. + * @param page First page to invalidate in TSB. + * @param pages Number of pages to invalidate. Value of (count_t) -1 means the + * whole TSB. */ void tsb_invalidate(as_t *as, uintptr_t page, size_t pages) { - size_t i0; - size_t i; + size_t i0, i; size_t cnt; - ASSERT(as->arch.itsb && as->arch.dtsb); + ASSERT(as->arch.tsb_description.tsb_base); i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK; - ASSERT(i0 < ITSB_ENTRY_COUNT && i0 < DTSB_ENTRY_COUNT); + ASSERT(i0 < TSB_ENTRY_COUNT); - if (pages == (size_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT) - cnt = ITSB_ENTRY_COUNT; + if (pages == (size_t) - 1 || (pages) > TSB_ENTRY_COUNT) + cnt = TSB_ENTRY_COUNT; else - cnt = pages * 2; + cnt = pages; for (i = 0; i < cnt; i++) { - as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid = - true; - as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid = - true; + ((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[ + (i0 + i) & (TSB_ENTRY_COUNT - 1)].data.v = false; } } @@ -81,19 +80,15 @@ * * @param t Software PTE. - * @param index Zero if lower 8K-subpage, one if higher 8K subpage. */ -void itsb_pte_copy(pte_t *t, size_t index) +void itsb_pte_copy(pte_t *t) { -#if 0 as_t *as; tsb_entry_t *tsb; size_t entry; - ASSERT(index <= 1); - as = t->as; - entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK; - ASSERT(entry < ITSB_ENTRY_COUNT); - tsb = &as->arch.itsb[entry]; + entry = (t->page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK; + ASSERT(entry < TSB_ENTRY_COUNT); + tsb = &((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[entry]; /* @@ -103,24 +98,25 @@ */ - tsb->tag.invalid = true; /* invalidate the entry - * (tag target has this - * set to 0) */ + tsb->data.v = false; write_barrier(); - tsb->tag.context = as->asid; - /* the shift is bigger than PAGE_WIDTH, do not bother with index */ tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; + tsb->data.value = 0; + tsb->data.nfo = false; + tsb->data.ra = t->frame >> MMU_FRAME_WIDTH; + tsb->data.ie = false; + tsb->data.e = false; + tsb->data.cp = t->c; /* cp as cache in phys.-idxed, c as cacheable */ + tsb->data.cv = false; + tsb->data.p = t->k; /* p as privileged, k as kernel */ + tsb->data.x = true; + tsb->data.w = false; tsb->data.size = PAGESIZE_8K; - tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index; - tsb->data.cp = t->c; /* cp as cache in phys.-idxed, c as cacheable */ - tsb->data.p = t->k; /* p as privileged, k as kernel */ - tsb->data.v = t->p; /* v as valid, p as present */ write_barrier(); - tsb->tag.invalid = false; /* mark the entry as valid */ -#endif + tsb->data.v = t->p; /* v as valid, p as present */ } @@ -128,20 +124,16 @@ * * @param t Software PTE. - * @param index Zero if lower 8K-subpage, one if higher 8K-subpage. * @param ro If true, the mapping is copied read-only. */ -void dtsb_pte_copy(pte_t *t, size_t index, bool ro) +void dtsb_pte_copy(pte_t *t, bool ro) { -#if 0 as_t *as; tsb_entry_t *tsb; size_t entry; - - ASSERT(index <= 1); as = t->as; - entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK; - ASSERT(entry < DTSB_ENTRY_COUNT); - tsb = &as->arch.dtsb[entry]; + entry = (t->page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK; + ASSERT(entry < TSB_ENTRY_COUNT); + tsb = &((tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base))[entry]; /* @@ -151,31 +143,29 @@ */ - tsb->tag.invalid = true; /* invalidate the entry - * (tag target has this - * set to 0) */ + tsb->data.v = false; write_barrier(); - tsb->tag.context = as->asid; - /* the shift is bigger than PAGE_WIDTH, do not bother with index */ tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; + tsb->data.value = 0; - tsb->data.size = PAGESIZE_8K; - tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index; - tsb->data.cp = t->c; + tsb->data.nfo = false; + tsb->data.ra = t->frame >> MMU_FRAME_WIDTH; + tsb->data.ie = false; + tsb->data.e = false; + tsb->data.cp = t->c; /* cp as cache in phys.-idxed, c as cacheable */ #ifdef CONFIG_VIRT_IDX_DCACHE tsb->data.cv = t->c; #endif /* CONFIG_VIRT_IDX_DCACHE */ - tsb->data.p = t->k; /* p as privileged */ + tsb->data.p = t->k; /* p as privileged, k as kernel */ + tsb->data.x = true; tsb->data.w = ro ? false : t->w; - tsb->data.v = t->p; + tsb->data.size = PAGESIZE_8K; write_barrier(); - tsb->tag.invalid = false; /* mark the entry as valid */ -#endif + tsb->data.v = t->p; /* v as valid, p as present */ } /** @} */ - Index: kernel/arch/sparc64/src/sun4v/sparc64.c =================================================================== --- kernel/arch/sparc64/src/sun4v/sparc64.c (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/src/sun4v/sparc64.c (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -50,6 +50,4 @@ #include #include - -//MH #include Index: kernel/arch/sparc64/src/trap/exception.c =================================================================== --- kernel/arch/sparc64/src/trap/exception.c (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/src/trap/exception.c (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -162,6 +162,5 @@ fault_if_from_uspace(istate, "%s.", __func__); dump_istate(istate); -//MH -// dump_sfsr_and_sfar(); + describe_dmmu_fault(); panic("%s.", __func__); } Index: kernel/arch/sparc64/src/trap/sun4v/trap_table.S =================================================================== --- kernel/arch/sparc64/src/trap/sun4v/trap_table.S (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/arch/sparc64/src/trap/sun4v/trap_table.S (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -48,4 +48,6 @@ #include #include +#include +#include #define TABLE_SIZE TRAP_TABLE_SIZE @@ -60,9 +62,15 @@ /* TT = 0x08, TL = 0, instruction_access_exception */ +/* TT = 0x08, TL = 0, IAE_privilege_violation on UltraSPARC T2 */ .org trap_table + TT_INSTRUCTION_ACCESS_EXCEPTION*ENTRY_SIZE .global instruction_access_exception_tl0 instruction_access_exception_tl0: - /*wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate - PREEMPTIBLE_HANDLER instruction_access_exception*/ + PREEMPTIBLE_HANDLER instruction_access_exception + +/* TT = 0x09, TL = 0, instruction_access_mmu_miss */ +.org trap_table + TT_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE +.global instruction_access_mmu_miss_handler_tl0 + ba fast_instruction_access_mmu_miss_handler_tl0 + nop /* TT = 0x0a, TL = 0, instruction_access_error */ @@ -72,4 +80,16 @@ PREEMPTIBLE_HANDLER instruction_access_error +/* TT = 0x0b, TL = 0, IAE_unauth_access */ +.org trap_table + TT_IAE_UNAUTH_ACCESS*ENTRY_SIZE +.global iae_unauth_access_tl0 +iae_unauth_access_tl0: + PREEMPTIBLE_HANDLER instruction_access_exception + +/* TT = 0x0c, TL = 0, IAE_nfo_page */ +.org trap_table + TT_IAE_NFO_PAGE*ENTRY_SIZE +.global iae_nfo_page_tl0 +iae_nfo_page_tl0: + PREEMPTIBLE_HANDLER instruction_access_exception + /* TT = 0x10, TL = 0, illegal_instruction */ .org trap_table + TT_ILLEGAL_INSTRUCTION*ENTRY_SIZE @@ -96,4 +116,28 @@ PREEMPTIBLE_HANDLER unimplemented_STD +/* TT = 0x14, TL = 0, DAE_invalid_asi */ +.org trap_table + TT_DAE_INVALID_ASI*ENTRY_SIZE +.global dae_invalid_asi_tl0 +dae_invalid_asi_tl0: + PREEMPTIBLE_HANDLER data_access_exception + +/* TT = 0x15, TL = 0, DAE_privilege_violation */ +.org trap_table + TT_DAE_PRIVILEGE_VIOLATION*ENTRY_SIZE +.global dae_privilege_violation_tl0 +dae_privilege_violation_tl0: + PREEMPTIBLE_HANDLER data_access_exception + +/* TT = 0x16, TL = 0, DAE_nc_page */ +.org trap_table + TT_DAE_NC_PAGE*ENTRY_SIZE +.global dae_nc_page_tl0 +dae_nc_page_tl0: + PREEMPTIBLE_HANDLER data_access_exception + +/* TT = 0x17, TL = 0, DAE_nfo_page */ +.org trap_table + TT_DAE_NFO_PAGE*ENTRY_SIZE +.global dae_nfo_page_tl0 +dae_nfo_page_tl0: + PREEMPTIBLE_HANDLER data_access_exception + /* TT = 0x20, TL = 0, fb_disabled handler */ .org trap_table + TT_FP_DISABLED*ENTRY_SIZE @@ -133,9 +177,16 @@ /* TT = 0x30, TL = 0, data_access_exception */ +/* TT = 0x30, TL = 0, DAE_side_effect_page for UltraPSARC T2 */ .org trap_table + TT_DATA_ACCESS_EXCEPTION*ENTRY_SIZE .global data_access_exception_tl0 data_access_exception_tl0: - wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate PREEMPTIBLE_HANDLER data_access_exception + +/* TT = 0x31, TL = 0, data_access_mmu_miss */ +.org trap_table + TT_DATA_ACCESS_MMU_MISS*ENTRY_SIZE +.global data_access_mmu_miss_tl0 +data_access_mmu_miss_tl0: + ba fast_data_access_mmu_miss_handler_tl0 + nop /* TT = 0x32, TL = 0, data_access_error */ @@ -271,10 +322,4 @@ INTERRUPT_LEVEL_N_HANDLER 15 -/* TT = 0x60, TL = 0, interrupt_vector_trap handler */ -.org trap_table + TT_INTERRUPT_VECTOR_TRAP*ENTRY_SIZE -.global interrupt_vector_trap_handler_tl0 -interrupt_vector_trap_handler_tl0: - INTERRUPT_VECTOR_TRAP_HANDLER - /* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */ .org trap_table + TT_FAST_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE @@ -294,4 +339,10 @@ fast_data_access_protection_handler_tl0: FAST_DATA_ACCESS_PROTECTION_HANDLER 0 + +/* TT = 0x7c, TL = 0, cpu_mondo */ +.org trap_table + TT_CPU_MONDO*ENTRY_SIZE +.global cpu_mondo_handler_tl0 +cpu_mondo_handler_tl0: +/* PREEMPTIBLE_HANDLER cpu_mondo */ /* TT = 0x80, TL = 0, spill_0_normal handler */ @@ -352,10 +403,17 @@ /* TT = 0x08, TL > 0, instruction_access_exception */ +/* TT = 0x08, TL > 0, IAE_privilege_violation on UltraSPARC T2 */ .org trap_table + (TT_INSTRUCTION_ACCESS_EXCEPTION+512)*ENTRY_SIZE .global instruction_access_exception_tl1 instruction_access_exception_tl1: wrpr %g0, 1, %tl - wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate PREEMPTIBLE_HANDLER instruction_access_exception + +/* TT = 0x09, TL > 0, instruction_access_mmu_miss */ +.org trap_table + (TT_INSTRUCTION_ACCESS_MMU_MISS+512)*ENTRY_SIZE +.global instruction_access_mmu_miss_handler_tl1 + wrpr %g0, 1, %tl + ba fast_instruction_access_mmu_miss_handler_tl0 + nop /* TT = 0x0a, TL > 0, instruction_access_error */ @@ -366,4 +424,18 @@ PREEMPTIBLE_HANDLER instruction_access_error +/* TT = 0x0b, TL > 0, IAE_unauth_access */ +.org trap_table + (TT_IAE_UNAUTH_ACCESS+512)*ENTRY_SIZE +.global iae_unauth_access_tl1 +iae_unauth_access_tl1: + wrpr %g0, 1, %tl + PREEMPTIBLE_HANDLER instruction_access_exception + +/* TT = 0x0c, TL > 0, IAE_nfo_page */ +.org trap_table + (TT_IAE_NFO_PAGE+512)*ENTRY_SIZE +.global iae_nfo_page_tl1 +iae_nfo_page_tl1: + wrpr %g0, 1, %tl + PREEMPTIBLE_HANDLER instruction_access_exception + /* TT = 0x10, TL > 0, illegal_instruction */ .org trap_table + (TT_ILLEGAL_INSTRUCTION+512)*ENTRY_SIZE @@ -372,4 +444,32 @@ wrpr %g0, 1, %tl PREEMPTIBLE_HANDLER illegal_instruction + +/* TT = 0x14, TL > 0, DAE_invalid_asi */ +.org trap_table + (TT_DAE_INVALID_ASI+512)*ENTRY_SIZE +.global dae_invalid_asi_tl1 +dae_invalid_asi_tl1: + wrpr %g0, 1, %tl + PREEMPTIBLE_HANDLER data_access_exception + +/* TT = 0x15, TL > 0, DAE_privilege_violation */ +.org trap_table + (TT_DAE_PRIVILEGE_VIOLATION+512)*ENTRY_SIZE +.global dae_privilege_violation_tl1 +dae_privilege_violation_tl1: + wrpr %g0, 1, %tl + PREEMPTIBLE_HANDLER data_access_exception + +/* TT = 0x16, TL > 0, DAE_nc_page */ +.org trap_table + (TT_DAE_NC_PAGE+512)*ENTRY_SIZE +.global dae_nc_page_tl1 +dae_nc_page_tl1: + wrpr %g0, 1, %tl + PREEMPTIBLE_HANDLER data_access_exception + +/* TT = 0x17, TL > 0, DAE_nfo_page */ +.org trap_table + (TT_DAE_NFO_PAGE+512)*ENTRY_SIZE +.global dae_nfo_page_tl1 +dae_nfo_page_tl1: + wrpr %g0, 1, %tl + PREEMPTIBLE_HANDLER data_access_exception /* TT = 0x24, TL > 0, clean_window handler */ @@ -390,7 +490,15 @@ .global data_access_exception_tl1 data_access_exception_tl1: - wrpr %g0, 1, %tl + /*wrpr %g0, 1, %tl wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate - PREEMPTIBLE_HANDLER data_access_exception + PREEMPTIBLE_HANDLER data_access_exception*/ + +/* TT = 0x31, TL > 0, data_access_mmu_miss */ +.org trap_table + (TT_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE +.global data_access_mmu_miss_tl1 +data_access_mmu_miss_tl1: + ba fast_data_access_mmu_miss_handler_tl1 + nop + /* TT = 0x32, TL > 0, data_access_error */ @@ -419,4 +527,11 @@ fast_data_access_protection_handler_tl1: FAST_DATA_ACCESS_PROTECTION_HANDLER 1 + +/* TT = 0x7c, TL > 0, cpu_mondo */ +.org trap_table + (TT_CPU_MONDO+512)*ENTRY_SIZE +.global cpu_mondo_handler_tl1 +cpu_mondo_handler_tl1: + wrpr %g0, %tl +/* PREEMPTIBLE_HANDLER cpu_mondo */ /* TT = 0x80, TL > 0, spill_0_normal handler */ @@ -660,6 +775,4 @@ .endm - -#if 0 /* * Preemptible trap handler for handling traps from kernel. @@ -677,163 +790,4 @@ nop ! it will be easy to find - /* prevent unnecessary CLEANWIN exceptions */ - wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(0), %wstate -1: - /* - * Prevent SAVE instruction from causing a spill exception. If the - * CANSAVE register is zero, explicitly spill register window - * at CWP + 2. - */ - - rdpr %cansave, %g3 - brnz %g3, 2f - nop - INLINE_SPILL %g3, %g4 - -2: - /* ask for new register window */ - save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp - - /* copy higher level routine's address and its argument */ - mov %g1, %l0 - mov %g2, %o0 - - /* - * Save TSTATE, TPC and TNPC aside. - */ - rdpr %tstate, %g1 - rdpr %tpc, %g2 - rdpr %tnpc, %g3 - - stx %g1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE] - stx %g2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC] - stx %g3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC] - - /* - * Save the Y register. - * This register is deprecated according to SPARC V9 specification - * and is only present for backward compatibility with previous - * versions of the SPARC architecture. - * Surprisingly, gcc makes use of this register without a notice. - */ - rd %y, %g4 - stx %g4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y] - - /* switch to TL = 0, explicitly enable FPU */ - wrpr %g0, 0, %tl - wrpr %g0, 0, %gl - wrpr %g0, PSTATE_PRIV_BIT | PSTATE_PEF_BIT, %pstate - - /* g1 -> l1, ..., g7 -> l7 */ - SAVE_GLOBALS - - /* call higher-level service routine, pass istate as its 2nd parameter */ - call %l0 - add %sp, PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC, %o1 - - /* l1 -> g1, ..., l7 -> g7 */ - RESTORE_GLOBALS - - /* we must prserve the PEF bit */ - rdpr %pstate, %l1 - - /* TL := 1, GL := 1 */ - wrpr %g0, PSTATE_PRIV_BIT, %pstate - wrpr %g0, 1, %tl - wrpr %g0, 1, %gl - - /* Read TSTATE, TPC and TNPC from saved copy. */ - ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE], %g1 - ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC], %g2 - ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC], %g3 - - /* Copy PSTATE.PEF to the in-register copy of TSTATE. */ - and %l1, PSTATE_PEF_BIT, %l1 - sllx %l1, TSTATE_PSTATE_SHIFT, %l1 - sethi %hi(TSTATE_PEF_BIT), %g4 ! reset the PEF bit to 0 ... - andn %g1, %g4, %g1 - or %g1, %l1, %g1 ! ... "or" it with saved PEF - - /* Restore TSTATE, TPC and TNPC from saved copies. */ - wrpr %g1, 0, %tstate - wrpr %g2, 0, %tpc - wrpr %g3, 0, %tnpc - - /* Restore Y. */ - ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y], %g4 - wr %g4, %y - - /* If TSTATE.CWP + 1 == CWP, then we do not have to fix CWP. */ - and %g1, TSTATE_CWP_MASK, %l0 - inc %l0 - and %l0, NWINDOWS - 1, %l0 ! %l0 mod NWINDOWS - rdpr %cwp, %l1 - cmp %l0, %l1 - bz 4f ! CWP is ok - nop - -3: - /* - * Fix CWP. - * In order to recapitulate, the input registers in the current - * window are the output registers of the window to which we want - * to restore. Because the fill trap fills only input and local - * registers of a window, we need to preserve those output - * registers manually. - */ - mov %sp, %g2 - stx %i0, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0] - stx %i1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1] - stx %i2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2] - stx %i3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3] - stx %i4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4] - stx %i5, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5] - stx %i6, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6] - stx %i7, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7] - wrpr %l0, 0, %cwp - mov %g2, %sp - ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0], %i0 - ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1], %i1 - ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2], %i2 - ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3], %i3 - ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4], %i4 - ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5], %i5 - ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6], %i6 - ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7], %i7 - -4: - /* - * Prevent RESTORE instruction from causing a fill exception. If the - * CANRESTORE register is zero, explicitly fill register window - * at CWP - 1. - */ - rdpr %canrestore, %g1 - brnz %g1, 5f - nop - INLINE_FILL %g3, %g4 - -5: - restore - - retry -.endm - -#endif - -/* - * Preemptible trap handler for handling traps from kernel. - */ -.macro PREEMPTIBLE_HANDLER_KERNEL - - /* - * ASSERT(%tl == 1) - */ - rdpr %tl, %g3 - cmp %g3, 1 - be 1f - nop -0: ba 0b ! this is for debugging, if we ever get here - nop ! it will be easy to find - 1: /* prevent unnecessary CLEANWIN exceptions */ @@ -872,6 +826,4 @@ retry .endm - - /* @@ -1092,5 +1044,5 @@ and %g1, NWINDOWS - 1, %g1 wrpr %g1, 0, %cwp ! CWP-- - + .if \is_syscall done @@ -1100,6 +1052,4 @@ .endm - - /* Preemptible trap handler for TL=1. @@ -1132,3 +1082,2 @@ trap_instruction_handler: PREEMPTIBLE_HANDLER_TEMPLATE 1 - Index: kernel/generic/include/errno.h =================================================================== --- kernel/generic/include/errno.h (revision b03a6661abd7275f3449da5ceb08f6e13194c4f3) +++ kernel/generic/include/errno.h (revision c2efbb4ffae4b59dd2f12995a3926eb4251bfa3d) @@ -57,11 +57,6 @@ #define EADDRNOTAVAIL -12 /* Address not available. */ #define ETIMEOUT -13 /* Timeout expired */ -//MH -#ifndef EINVAL #define EINVAL -14 /* Invalid value */ -#endif -#ifndef EBUSY #define EBUSY -15 /* Resource is busy */ -#endif #define EOVERFLOW -16 /* The result does not fit its size. */ #define EINTR -17 /* Operation was interrupted. */