Changeset c2efbb4 in mainline for kernel/arch/amd64/include

Timestamp:

2010-02-20T20:54:53Z (16 years ago)

Author:

Pavel Rimsky <pavel@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/fix-logger-deadlock, topic/msim-upgrade, topic/simplify-dev-export

Children:

721d4e85, 95c4776

Parents:

f516bc2 (diff), b03a666 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Synchronize with head.

Location:

kernel/arch/amd64/include

Files:

• atomic.h (modified) (7 diffs)
• interrupt.h (modified) (1 diff)
• memstr.h (modified) (2 diffs)
• types.h (modified) (1 diff)

kernel/arch/amd64/include/atomic.h

@@ -40 +40 @@
 #include <preemption.h>
 
-static inline void atomic_inc(atomic_t *val) {
+static inline void atomic_inc(atomic_t *val)
+{
 #ifdef CONFIG_SMP
         asm volatile (
@@ -54 +55 @@
 }
 
-static inline void atomic_dec(atomic_t *val) {
+static inline void atomic_dec(atomic_t *val)
+{
 #ifdef CONFIG_SMP
         asm volatile (
@@ -68 +70 @@
 }
 
-static inline long atomic_postinc(atomic_t *val) 
+static inline atomic_count_t atomic_postinc(atomic_t *val)
 {
-        long r = 1;
+        atomic_count_t r = 1;
         
         asm volatile (
                 "lock xaddq %[r], %[count]\n"
-                : [count] "+m" (val->count), [r] "+r" (r)
+                : [count] "+m" (val->count),
+                  [r] "+r" (r)
         );
         
@@ -80 +83 @@
 }
 
-static inline long atomic_postdec(atomic_t *val) 
+static inline atomic_count_t atomic_postdec(atomic_t *val)
 {
-        long r = -1;
+        atomic_count_t r = -1;
         
         asm volatile (
                 "lock xaddq %[r], %[count]\n"
-                : [count] "+m" (val->count), [r] "+r" (r)
+                : [count] "+m" (val->count),
+                  [r] "+r" (r)
         );
         
@@ -95 +99 @@
 #define atomic_predec(val)  (atomic_postdec(val) - 1)
 
-static inline uint64_t test_and_set(atomic_t *val) {
-        uint64_t v;
+static inline atomic_count_t test_and_set(atomic_t *val)
+{
+        atomic_count_t v;
         
         asm volatile (
                 "movq $1, %[v]\n"
                 "xchgq %[v], %[count]\n"
-                : [v] "=r" (v), [count] "+m" (val->count)
+                : [v] "=r" (v),
+                  [count] "+m" (val->count)
         );
         
@@ -107 +113 @@
 }
 
-
 /** amd64 specific fast spinlock */
 static inline void atomic_lock_arch(atomic_t *val)
 {
-        uint64_t tmp;
+        atomic_count_t tmp;
         
         preemption_disable();
@@ -125 +130 @@
                 "testq %[tmp], %[tmp]\n"
                 "jnz 0b\n"
-                : [count] "+m" (val->count), [tmp] "=&r" (tmp)
+                : [count] "+m" (val->count),
+                  [tmp] "=&r" (tmp)
         );
+        
         /*
          * Prevent critical section code from bleeding out this way up.

kernel/arch/amd64/include/interrupt.h

@@ -54 +54 @@
 #define IRQ_PIC_SPUR            7
 #define IRQ_MOUSE               12
+#define IRQ_DP8390              9
 
 /* this one must have four least significant bits set to ones */

kernel/arch/amd64/include/memstr.h

@@ -27 +27 @@
  */
 
-/** @addtogroup amd64   
+/** @addtogroup amd64
  * @{
  */
@@ -38 +38 @@
 #define memcpy(dst, src, cnt)  __builtin_memcpy((dst), (src), (cnt))
 
-extern void memsetw(void *dst, size_t cnt, uint16_t x);
-extern void memsetb(void *dst, size_t cnt, uint8_t x);
-
-extern int memcmp(const void *a, const void *b, size_t cnt);
+extern void memsetw(void *, size_t, uint16_t);
+extern void memsetb(void *, size_t, uint8_t);
 
 #endif

kernel/arch/amd64/include/types.h

@@ -55 +55 @@
 typedef uint64_t unative_t;
 typedef int64_t native_t;
+typedef uint64_t atomic_count_t;
 
 typedef struct {