Index: kernel/genarch/src/drivers/am335x/timer.c =================================================================== --- kernel/genarch/src/drivers/am335x/timer.c (revision c2b2de7ea7c77612cde2379131a6f1e3b0544307) +++ kernel/genarch/src/drivers/am335x/timer.c (revision c2b2de7ea7c77612cde2379131a6f1e3b0544307) @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2012 Maurizio Lombardi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup genarch + * @{ + */ +/** + * @file + * @brief Texas Instruments AM335x timer driver. + */ + +#include +#include +#include + + +typedef struct timer_regs_mmap { + uintptr_t base; + size_t size; +} timer_regs_mmap_t; + +static const timer_regs_mmap_t regs_map[TIMERS_MAX] = { + { .base = AM335x_DMTIMER0_BASE_ADDRESS, .size = AM335x_DMTIMER0_SIZE }, + {0, 0}, + { .base = AM335x_DMTIMER2_BASE_ADDRESS, .size = AM335x_DMTIMER2_SIZE }, + { .base = AM335x_DMTIMER3_BASE_ADDRESS, .size = AM335x_DMTIMER3_SIZE }, + { .base = AM335x_DMTIMER4_BASE_ADDRESS, .size = AM335x_DMTIMER4_SIZE }, + { .base = AM335x_DMTIMER5_BASE_ADDRESS, .size = AM335x_DMTIMER5_SIZE }, + { .base = AM335x_DMTIMER6_BASE_ADDRESS, .size = AM335x_DMTIMER6_SIZE }, + { .base = AM335x_DMTIMER7_BASE_ADDRESS, .size = AM335x_DMTIMER7_SIZE }, +}; + +void +am335x_timer_init(am335x_timer_t *timer, am335x_timer_id_t id, unsigned hz) +{ + uintptr_t base_addr; + size_t size; + + ASSERT(id < TIMERS_MAX); + + if (id == DMTIMER1_1MS) + return; /* Not supported yet */ + + base_addr = regs_map[id].base; + size = regs_map[id].size; + + timer->regs = (void *) km_map(base_addr, size, PAGE_NOT_CACHEABLE); + timer->id = id; + + am335x_timer_regs_t *regs = timer->regs; + + /* Stop the timer */ + am335x_timer_stop(timer); + + /* Perform a soft reset */ + am335x_timer_reset(timer); + + /* Disable the prescaler */ + regs->tclr &= ~AM335x_TIMER_TCLR_PRE_FLAG; + + /* Enable auto-reload mode */ + regs->tclr |= AM335x_TIMER_TCLR_AR_FLAG; + + /* XXX Here we assume that the timer clock source + * is running at 32 Khz but this is not always the + * case; DMTIMER[2 - 7] can use the internal system 24 Mhz + * clock source or an external clock also. + */ + unsigned const count = 0xFFFFFFFE - 32768 / hz; + regs->tcrr = count; + regs->tldr = count; +} + +void +am335x_timer_intr_ack(am335x_timer_t *timer) +{ + /* Clear pending OVF event */ + timer->regs->irqstatus |= AM335x_TIMER_IRQSTATUS_OVF_FLAG; +} + +void +am335x_timer_reset(am335x_timer_t *timer) +{ + /* Initiate soft reset */ + timer->regs->tiocp_cfg |= AM335x_TIMER_TIOCPCFG_SOFTRESET_FLAG; + /* Wait until the reset is done */ + while (timer->regs->tiocp_cfg & AM335x_TIMER_TIOCPCFG_SOFTRESET_FLAG); +} + +void +am335x_timer_stop(am335x_timer_t *timer) +{ + /* Disable the interrupt */ + timer->regs->irqenable_clr |= AM335x_TIMER_IRQENABLE_CLR_OVF_FLAG; + /* Stop the timer */ + timer->regs->tclr &= ~AM335x_TIMER_TCLR_ST_FLAG; +} + +void +am335x_timer_start(am335x_timer_t *timer) +{ + /* Enable the interrupt */ + timer->regs->irqenable_set |= AM335x_TIMER_IRQENABLE_SET_OVF_FLAG; + /* Start the clock */ + timer->regs->tclr |= AM335x_TIMER_TCLR_ST_FLAG; +} + +/** + * @} + */ + Index: kernel/genarch/src/drivers/am335x/uart.c =================================================================== --- kernel/genarch/src/drivers/am335x/uart.c (revision c2b2de7ea7c77612cde2379131a6f1e3b0544307) +++ kernel/genarch/src/drivers/am335x/uart.c (revision c2b2de7ea7c77612cde2379131a6f1e3b0544307) @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup genarch + * @{ + */ +/** + * @file + * @brief Texas Instruments AM335x on-chip uart serial line driver. + */ + +#include +#include +#include +#include + +static void am335x_uart_txb(am335x_uart_t *uart, uint8_t b) +{ + /* Wait for buffer */ + while (uart->regs->ssr & AM335x_UART_SSR_TX_FIFO_FULL_FLAG); + /* Write to the outgoing fifo */ + uart->regs->thr = b; +} + +static void am335x_uart_putchar(outdev_t *dev, wchar_t ch) +{ + am335x_uart_t *uart = dev->data; + if (!ascii_check(ch)) { + am335x_uart_txb(uart, U_SPECIAL); + } else { + if (ch == '\n') + am335x_uart_txb(uart, '\r'); + am335x_uart_txb(uart, ch); + } +} + +static outdev_operations_t am335x_uart_ops = { + .redraw = NULL, + .write = am335x_uart_putchar, +}; + +static irq_ownership_t am335x_uart_claim(irq_t *irq) +{ + return IRQ_ACCEPT; +} + +static void am335x_uart_handler(irq_t *irq) +{ + am335x_uart_t *uart = irq->instance; + while ((uart->regs->rx_fifo_lvl)) { + const uint8_t val = uart->regs->rhr; + if (uart->indev && val) { + indev_push_character(uart->indev, val); + } + } +} + +bool am335x_uart_init( + am335x_uart_t *uart, inr_t interrupt, uintptr_t addr, size_t size) +{ + ASSERT(uart); + uart->regs = (void *)km_map(addr, size, PAGE_NOT_CACHEABLE); + + ASSERT(uart->regs); + + /* Soft reset the port */ + uart->regs->sysc = AM335x_UART_SYSC_SOFTRESET_FLAG; + while (!(uart->regs->syss & AM335x_UART_SYSS_RESETDONE_FLAG)) ; + + /* Enable access to EFR register */ + const uint8_t lcr = uart->regs->lcr; /* Save old value */ + uart->regs->lcr = 0xbf; /* Sets config mode B */ + + /* Enable access to TCL_TLR register */ + const bool enhanced = uart->regs->efr & AM335x_UART_EFR_ENH_FLAG; + uart->regs->efr |= AM335x_UART_EFR_ENH_FLAG; /* Turn on enh. */ + uart->regs->lcr = 0x80; /* Config mode A */ + + /* Set default (val 0) triggers, disable DMA enable FIFOs */ + const bool tcl_tlr = uart->regs->mcr & AM335x_UART_MCR_TCR_TLR_FLAG; + /* Enable access to tcr and tlr registers */ + uart->regs->mcr |= AM335x_UART_MCR_TCR_TLR_FLAG; + + /* Enable FIFOs */ + uart->regs->fcr = AM335x_UART_FCR_FIFO_EN_FLAG; + + /* Enable fine granularity for RX FIFO and set trigger level to 1, + * TX FIFO, trigger level is irrelevant*/ + uart->regs->lcr = 0xbf; /* Sets config mode B */ + uart->regs->scr = AM335x_UART_SCR_RX_TRIG_GRANU1_FLAG; + uart->regs->tlr = 1 << AM335x_UART_TLR_RX_FIFO_TRIG_SHIFT; + + /* Restore enhanced */ + if (!enhanced) + uart->regs->efr &= ~AM335x_UART_EFR_ENH_FLAG; + + uart->regs->lcr = 0x80; /* Config mode A */ + /* Restore tcl_lcr access flag*/ + if (!tcl_tlr) + uart->regs->mcr &= ~AM335x_UART_MCR_TCR_TLR_FLAG; + + /* Restore lcr */ + uart->regs->lcr = lcr; + + /* Disable interrupts */ + uart->regs->ier = 0; + + /* Setup outdev */ + outdev_initialize("am335x_uart_dev", &uart->outdev, &am335x_uart_ops); + uart->outdev.data = uart; + + /* Initialize IRQ */ + irq_initialize(&uart->irq); + uart->irq.devno = device_assign_devno(); + uart->irq.inr = interrupt; + uart->irq.claim = am335x_uart_claim; + uart->irq.handler = am335x_uart_handler; + uart->irq.instance = uart; + + return true; +} + +void am335x_uart_input_wire(am335x_uart_t *uart, indev_t *indev) +{ + ASSERT(uart); + /* Set indev */ + uart->indev = indev; + /* Register interrupt. */ + irq_register(&uart->irq); + /* Enable interrupt on receive */ + uart->regs->ier |= AM335x_UART_IER_RHR_IRQ_FLAG; +} + +/** + * @} + */ + Index: kernel/genarch/src/drivers/amdm37x/uart.c =================================================================== --- kernel/genarch/src/drivers/amdm37x/uart.c (revision c2b2de7ea7c77612cde2379131a6f1e3b0544307) +++ kernel/genarch/src/drivers/amdm37x/uart.c (revision c2b2de7ea7c77612cde2379131a6f1e3b0544307) @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup genarch + * @{ + */ +/** + * @file + * @brief Texas Instruments AMDM37x on-chip uart serial line driver. + */ + +#include +#include +#include +#include + +static void amdm37x_uart_txb(amdm37x_uart_t *uart, uint8_t b) +{ + /* Wait for buffer */ + while (uart->regs->ssr & AMDM37x_UART_SSR_TX_FIFO_FULL_FLAG); + /* Write to the outgoing fifo */ + uart->regs->thr = b; +} + +static void amdm37x_uart_putchar(outdev_t *dev, wchar_t ch) +{ + amdm37x_uart_t *uart = dev->data; + if (!ascii_check(ch)) { + amdm37x_uart_txb(uart, U_SPECIAL); + } else { + if (ch == '\n') + amdm37x_uart_txb(uart, '\r'); + amdm37x_uart_txb(uart, ch); + } +} + +static outdev_operations_t amdm37x_uart_ops = { + .redraw = NULL, + .write = amdm37x_uart_putchar, +}; + +static irq_ownership_t amdm37x_uart_claim(irq_t *irq) +{ + return IRQ_ACCEPT; +} + +static void amdm37x_uart_handler(irq_t *irq) +{ + amdm37x_uart_t *uart = irq->instance; + while ((uart->regs->rx_fifo_lvl)) { + const uint8_t val = uart->regs->rhr; + if (uart->indev && val) { + indev_push_character(uart->indev, val); + } + } +} + +bool amdm37x_uart_init( + amdm37x_uart_t *uart, inr_t interrupt, uintptr_t addr, size_t size) +{ + ASSERT(uart); + uart->regs = (void *)km_map(addr, size, PAGE_NOT_CACHEABLE); + + ASSERT(uart->regs); + + /* See TI OMAP35X TRM ch 17.5.1.1 p. 2732 for startup routine */ +#if 0 + /* Soft reset the port */ + uart->regs->sysc = AMDM37x_UART_SYSC_SOFTRESET_FLAG; + while (!(uart->regs->syss & AMDM37x_UART_SYSS_RESETDONE_FLAG)) ; +#endif + + /* Enable access to EFR register */ + const uint8_t lcr = uart->regs->lcr; /* Save old value */ + uart->regs->lcr = 0xbf; /* Sets config mode B */ + + /* Enable access to TCL_TLR register */ + const bool enhanced = uart->regs->efr & AMDM37x_UART_EFR_ENH_FLAG; + uart->regs->efr |= AMDM37x_UART_EFR_ENH_FLAG; /* Turn on enh. */ + uart->regs->lcr = 0x80; /* Config mode A */ + + /* Set default (val 0) triggers, disable DMA enable FIFOs */ + const bool tcl_tlr = uart->regs->mcr & AMDM37x_UART_MCR_TCR_TLR_FLAG; + /* Enable access to tcr and tlr registers */ + uart->regs->mcr |= AMDM37x_UART_MCR_TCR_TLR_FLAG; + + /* Enable FIFOs */ + uart->regs->fcr = AMDM37x_UART_FCR_FIFO_EN_FLAG; + + /* Eneble fine granularity for RX FIFO and set trigger level to 1, + * TX FIFO, trigger level is irelevant*/ + uart->regs->lcr = 0xbf; /* Sets config mode B */ + uart->regs->scr = AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG; + uart->regs->tlr = 1 << AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT; + + /* Restore enhanced */ + if (!enhanced) + uart->regs->efr &= ~AMDM37x_UART_EFR_ENH_FLAG; + + uart->regs->lcr = 0x80; /* Config mode A */ + /* Restore tcl_lcr access flag*/ + if (!tcl_tlr) + uart->regs->mcr &= ~AMDM37x_UART_MCR_TCR_TLR_FLAG; + + /* Restore lcr */ + uart->regs->lcr = lcr; + + /* Disable interrupts */ + uart->regs->ier = 0; + + /* Setup outdev */ + outdev_initialize("amdm37x_uart_dev", &uart->outdev, &amdm37x_uart_ops); + uart->outdev.data = uart; + + /* Initialize IRQ */ + irq_initialize(&uart->irq); + uart->irq.devno = device_assign_devno(); + uart->irq.inr = interrupt; + uart->irq.claim = amdm37x_uart_claim; + uart->irq.handler = amdm37x_uart_handler; + uart->irq.instance = uart; + + return true; +} + +void amdm37x_uart_input_wire(amdm37x_uart_t *uart, indev_t *indev) +{ + ASSERT(uart); + /* Set indev */ + uart->indev = indev; + /* Register interrupt. */ + irq_register(&uart->irq); + /* Enable interrupt on receive */ + uart->regs->ier |= AMDM37x_UART_IER_RHR_IRQ_FLAG; +} + +/** + * @} + */ Index: kernel/genarch/src/drivers/amdm37x_uart/amdm37x_uart.c =================================================================== --- kernel/genarch/src/drivers/amdm37x_uart/amdm37x_uart.c (revision e2a6b727e4e48e0863bbeff4eadd944af3ceecdd) +++ (revision ) @@ -1,163 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** @addtogroup genarch - * @{ - */ -/** - * @file - * @brief Texas Instruments AMDM37x on-chip uart serial line driver. - */ - -#include -#include -#include -#include - -static void amdm37x_uart_txb(amdm37x_uart_t *uart, uint8_t b) -{ - /* Wait for buffer */ - while (uart->regs->ssr & AMDM37x_UART_SSR_TX_FIFO_FULL_FLAG); - /* Write to the outgoing fifo */ - uart->regs->thr = b; -} - -static void amdm37x_uart_putchar(outdev_t *dev, wchar_t ch) -{ - amdm37x_uart_t *uart = dev->data; - if (!ascii_check(ch)) { - amdm37x_uart_txb(uart, U_SPECIAL); - } else { - if (ch == '\n') - amdm37x_uart_txb(uart, '\r'); - amdm37x_uart_txb(uart, ch); - } -} - -static outdev_operations_t amdm37x_uart_ops = { - .redraw = NULL, - .write = amdm37x_uart_putchar, -}; - -static irq_ownership_t amdm37x_uart_claim(irq_t *irq) -{ - return IRQ_ACCEPT; -} - -static void amdm37x_uart_handler(irq_t *irq) -{ - amdm37x_uart_t *uart = irq->instance; - while ((uart->regs->rx_fifo_lvl)) { - const uint8_t val = uart->regs->rhr; - if (uart->indev && val) { - indev_push_character(uart->indev, val); - } - } -} - -bool amdm37x_uart_init( - amdm37x_uart_t *uart, inr_t interrupt, uintptr_t addr, size_t size) -{ - ASSERT(uart); - uart->regs = (void *)km_map(addr, size, PAGE_NOT_CACHEABLE); - - ASSERT(uart->regs); - - /* See TI OMAP35X TRM ch 17.5.1.1 p. 2732 for startup routine */ -#if 0 - /* Soft reset the port */ - uart->regs->sysc = AMDM37x_UART_SYSC_SOFTRESET_FLAG; - while (!(uart->regs->syss & AMDM37x_UART_SYSS_RESETDONE_FLAG)) ; -#endif - - /* Enable access to EFR register */ - const uint8_t lcr = uart->regs->lcr; /* Save old value */ - uart->regs->lcr = 0xbf; /* Sets config mode B */ - - /* Enable access to TCL_TLR register */ - const bool enhanced = uart->regs->efr & AMDM37x_UART_EFR_ENH_FLAG; - uart->regs->efr |= AMDM37x_UART_EFR_ENH_FLAG; /* Turn on enh. */ - uart->regs->lcr = 0x80; /* Config mode A */ - - /* Set default (val 0) triggers, disable DMA enable FIFOs */ - const bool tcl_tlr = uart->regs->mcr & AMDM37x_UART_MCR_TCR_TLR_FLAG; - /* Enable access to tcr and tlr registers */ - uart->regs->mcr |= AMDM37x_UART_MCR_TCR_TLR_FLAG; - - /* Enable FIFOs */ - uart->regs->fcr = AMDM37x_UART_FCR_FIFO_EN_FLAG; - - /* Eneble fine granularity for RX FIFO and set trigger level to 1, - * TX FIFO, trigger level is irelevant*/ - uart->regs->lcr = 0xbf; /* Sets config mode B */ - uart->regs->scr = AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG; - uart->regs->tlr = 1 << AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT; - - /* Restore enhanced */ - if (!enhanced) - uart->regs->efr &= ~AMDM37x_UART_EFR_ENH_FLAG; - - uart->regs->lcr = 0x80; /* Config mode A */ - /* Restore tcl_lcr access flag*/ - if (!tcl_tlr) - uart->regs->mcr &= ~AMDM37x_UART_MCR_TCR_TLR_FLAG; - - /* Restore lcr */ - uart->regs->lcr = lcr; - - /* Disable interrupts */ - uart->regs->ier = 0; - - /* Setup outdev */ - outdev_initialize("amdm37x_uart_dev", &uart->outdev, &amdm37x_uart_ops); - uart->outdev.data = uart; - - /* Initialize IRQ */ - irq_initialize(&uart->irq); - uart->irq.devno = device_assign_devno(); - uart->irq.inr = interrupt; - uart->irq.claim = amdm37x_uart_claim; - uart->irq.handler = amdm37x_uart_handler; - uart->irq.instance = uart; - - return true; -} - -void amdm37x_uart_input_wire(amdm37x_uart_t *uart, indev_t *indev) -{ - ASSERT(uart); - /* Set indev */ - uart->indev = indev; - /* Register interrupt. */ - irq_register(&uart->irq); - /* Enable interrupt on receive */ - uart->regs->ier |= AMDM37x_UART_IER_RHR_IRQ_FLAG; -} - -/** - * @} - */