Index: arch/ia32/src/asm.S
===================================================================
--- arch/ia32/src/asm.S	(revision 5d945376398e9f926c6c1d1c9425dd08ae2c3cf2)
+++ arch/ia32/src/asm.S	(revision c19213448332703a2811e89be57f66bfeff5c246)
@@ -115,4 +115,13 @@
 	pop %es
 	pop %ds
+
+
+# CLNT
+  pushfl;
+	pop %eax;
+	and $0xFFFFBFFF;
+	push %eax;
+	popfl;
+	
 
 
Index: arch/ia32/src/cpu/cpu.c
===================================================================
--- arch/ia32/src/cpu/cpu.c	(revision 5d945376398e9f926c6c1d1c9425dd08ae2c3cf2)
+++ arch/ia32/src/cpu/cpu.c	(revision c19213448332703a2811e89be57f66bfeff5c246)
@@ -50,4 +50,5 @@
 #define INTEL_CPUID_EDX 0x49656e69
 
+
 enum vendor {
 	VendorUnknown=0,
@@ -87,4 +88,5 @@
 	);	
 }
+
 
 
Index: arch/ia32/src/pm.c
===================================================================
--- arch/ia32/src/pm.c	(revision 5d945376398e9f926c6c1d1c9425dd08ae2c3cf2)
+++ arch/ia32/src/pm.c	(revision c19213448332703a2811e89be57f66bfeff5c246)
@@ -129,4 +129,23 @@
 
 
+
+static void clean_IOPL_NT_flags(void)
+{
+  asm
+	(
+    "pushfl;"
+		"pop %%eax;"
+		"and $0xffff8fff,%%eax;"
+		"push %%eax;"
+		"popfl;"
+		:
+		:
+		:"%eax"
+	);
+}
+
+
+
+
 void pm_init(void)
 {
@@ -166,3 +185,5 @@
 	 */
 	__asm__("ltr %0" : : "r" ((__u16) selector(TSS_DES)));
+	
+	clean_IOPL_NT_flags();
 }
Index: arch/ia32/src/userspace.c
===================================================================
--- arch/ia32/src/userspace.c	(revision 5d945376398e9f926c6c1d1c9425dd08ae2c3cf2)
+++ arch/ia32/src/userspace.c	(revision c19213448332703a2811e89be57f66bfeff5c246)
@@ -47,4 +47,11 @@
 
 	__asm__ volatile (""
+    // CLNT
+		"pushfl;"
+		"pop %%eax;"
+		"and $0xFFFFBFFF;"
+		"push %%eax;"
+		"popfl;"
+
 		"pushl %0\n"
 		"pushl %1\n"
Index: doc/TODO
===================================================================
--- doc/TODO	(revision 5d945376398e9f926c6c1d1c9425dd08ae2c3cf2)
+++ doc/TODO	(revision c19213448332703a2811e89be57f66bfeff5c246)
@@ -11,9 +11,9 @@
 
 + save/restore floating point context on context switch 
-  + [ia32] lazy context switch using TS flag [DONE]
+  + [ia32] lazy context switch using TS flag                              [DONE]
 + [ia32] MMX,SSE1-.. initialization
 + [ia32] review privilege separation
-  + zero IOPL in EFLAGS
-  + before IRET (from SYSCALL), zero NT in EFLAGS
+  + zero IOPL in EFLAGS                                                   [DONE]
+  + before IRET (from SYSCALL), zero NT in EFLAGS                         [DONE]
 + [ia32] review the cache controling bits in CR0 register
 + [ia32] zero the alignment exception bit in EFLAGS