Index: uspace/drv/infrastructure/rootamdm37x/prm/clock_control.h
===================================================================
--- uspace/drv/infrastructure/rootamdm37x/prm/clock_control.h	(revision d27a9c8f596ca95ee3af967261abc7c7ede2fa69)
+++ uspace/drv/infrastructure/rootamdm37x/prm/clock_control.h	(revision bfc6e116d31b5115a412845ad8503f20b5004f4d)
@@ -43,7 +43,4 @@
 
 /** Clock control PRM register map
- *
- * Periph DPLL == DPLL4
- * Core DPLL == DPLL3
  */
 typedef struct {
@@ -52,10 +49,10 @@
 #define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_12M   (0x0)
 #define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_13M   (0x1)
-#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_19.2M   (0x2)
+#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_19_2M   (0x2)
 #define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_26M   (0x3)
-#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_38.4M   (0x4)
-#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_16.8M   (0x5)
+#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_38_4M   (0x4)
+#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_16_8M   (0x5)
 
-	PADD32[12]
+	PADD32[12];
 	ioport32_t clkout_ctrl;
 #define CLOCK_CONTROL_PRM_CLKOUT_CTRL_CLKOUOUT_EN_FLAG   (1 << 7)
@@ -63,4 +60,19 @@
 } clock_control_prm_regs_t;
 
+static unsigned sys_clk_freq_kHz(unsigned reg_val)
+{
+	switch(reg_val)
+	{
+	case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_12M: return 12000;
+	case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_13M: return 13000;
+	case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_19_2M: return 19200;
+	case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_26M: return 26000;
+	case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_38_4M: return 38400;
+	case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_16_8M: return 16800;
+	}
+	return 0;
+}
+
+
 #endif
 /**