Index: uspace/drv/nic/e1k/Makefile =================================================================== --- uspace/drv/nic/e1k/Makefile (revision bf848717e8d508127f8be22655d603fdd89fe773) +++ uspace/drv/nic/e1k/Makefile (revision bf848717e8d508127f8be22655d603fdd89fe773) @@ -0,0 +1,37 @@ +# +# Copyright (c) 2011 Radim Vansa +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +USPACE_PREFIX = ../../.. +LIBS = $(LIBDRV_PREFIX)/libdrv.a $(LIBNET_PREFIX)/libnet.a $(LIBNIC_PREFIX)/libnic.a +EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include -I$(LIBNET_PREFIX)/include -I$(LIBNIC_PREFIX)/include +BINARY = e1k + +SOURCES = \ + e1k.c + +include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/nic/e1k/e1k.c =================================================================== --- uspace/drv/nic/e1k/e1k.c (revision bf848717e8d508127f8be22655d603fdd89fe773) +++ uspace/drv/nic/e1k/e1k.c (revision bf848717e8d508127f8be22655d603fdd89fe773) @@ -0,0 +1,2197 @@ +/* + * Copyright (c) 2011 Zdenek Bouska + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @file e1000.c + * + * Driver for Intel Pro/1000 8254x Family of Gigabit Ethernet Controllers + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "e1000_defs.h" + +/// The driver name +#define NAME "e1000" + +#define E1000_DEFAULT_INTERRUPT_INTEVAL_USEC 250 + + +// Must be power of 8 +#define E1000_RX_PACKETS_COUNT 128 +#define E1000_TX_PACKETS_COUNT 128 + +#define E1000_RECEIVE_ADDRESS 16 + +/** Maximum receiving packet size */ +#define E1000_MAX_RECEIVE_PACKET_SIZE 2048 + +/** nic_driver_data_t* -> e1000_t* cast */ +#define DRIVER_DATA_NIC(nic_data) ((e1000_t*) nic_get_specific(nic_data)) +/** device_t* -> nic_driver_data_t* cast */ +#define NIC_DATA_DEV(dev) ((nic_t*)((dev)->driver_data)) +/** device_t* -> e1000_t* cast */ +#define DRIVER_DATA_DEV(dev) (DRIVER_DATA_NIC(NIC_DATA_DEV(dev))) + +/** Cast pointer to uint32_t + * + * @param ptr The pointer to cast + * @return The uint32_t pointer representation. The low 32 bit is taken + * in the case of the 64 bit pointers + */ +#define PTR_TO_U64(ptr) ((uint64_t)((size_t)(ptr))) + +/** Cast the memaddr part to the void* + * + * @param memaddr The memaddr value + */ +#define MEMADDR_TO_PTR(memaddr) ((void*)((size_t)(memaddr))) + +#define E1000_REG_BASE(e1000_data) (e1000_data->virt_reg_base) +#define E1000_REG_ADDR(e1000_data, reg) ((uint32_t *)(E1000_REG_BASE(e1000_data) + reg)) +#define E1000_REG_READ(e1000_data, reg) (pio_read_32(E1000_REG_ADDR(e1000_data, reg))) +#define E1000_REG_WRITE(e1000_data, reg, value) (pio_write_32(E1000_REG_ADDR(e1000_data, reg), value)) + + +/** E1000 device data */ +typedef struct e1000_data { + /** Physical registers base address */ + void * phys_reg_base; + /** Virtual registers base address */ + void * virt_reg_base; + /** Tx ring */ + dma_mem_t tx_ring; + /** Packets in tx ring */ + packet_t ** tx_ring_packets; + /** Rx ring */ + dma_mem_t rx_ring; + /** Packets in rx ring */ + packet_t ** rx_ring_packets; + /** VLAN tag */ + uint16_t vlan_tag; + /** add VLAN tag to packet */ + int vlan_tag_add; + /** Used unicast Receive Address count */ + unsigned int unicast_ra_count; + /** Used milticast Receive addrress count */ + unsigned int multicast_ra_count; + /** PCI device ID */ + uint16_t device_id; + /** The irq assigned */ + int irq; + /** Lock for CTRL register */ + fibril_mutex_t ctrl_lock; + /** Lock for receiver */ + fibril_mutex_t rx_lock; + /** Lock for transmitter */ + fibril_mutex_t tx_lock; + /** Lock for EEPROM access */ + fibril_mutex_t eeprom_lock; +} e1000_t; + +/** Global mutex for work with shared irq structure */ +FIBRIL_MUTEX_INITIALIZE(irq_reg_mutex); + +static int e1000_get_address(e1000_t *, nic_address_t *); +static void e1000_eeprom_get_address(e1000_t *, nic_address_t *address); +static int e1000_set_addr(ddf_fun_t *dev, const nic_address_t *addr); + +static int e1000_defective_get_mode(ddf_fun_t *device, uint32_t *mode); +static int e1000_defective_set_mode(ddf_fun_t *device, uint32_t mode); + +static int e1000_get_cable_state(ddf_fun_t *dev, nic_cable_state_t *state); +static int e1000_get_device_info(ddf_fun_t *dev, nic_device_info_t *info); +static int e1000_get_operation_mode(ddf_fun_t *device, int *speed, + nic_channel_mode_t *duplex, nic_role_t *role); +static int e1000_set_operation_mode(ddf_fun_t *device, int speed, + nic_channel_mode_t duplex, nic_role_t); +static int e1000_autoneg_enable(ddf_fun_t *device, uint32_t advertisement); +static int e1000_autoneg_disable(ddf_fun_t *device); +static int e1000_autoneg_restart(ddf_fun_t *device); + +static int e1000_vlan_set_tag(ddf_fun_t *device, uint16_t tag, int add, int strip); + +/** Network interface options for E1000 card driver */ +static nic_iface_t e1000_nic_iface; + +/** Network interface options for E1000 card driver */ +static nic_iface_t e1000_nic_iface = { + .set_address = &e1000_set_addr, + .get_device_info = &e1000_get_device_info, + .get_cable_state = &e1000_get_cable_state, + .get_operation_mode = &e1000_get_operation_mode, + .set_operation_mode = &e1000_set_operation_mode, + .autoneg_enable = &e1000_autoneg_enable, + .autoneg_disable = &e1000_autoneg_disable, + .autoneg_restart = &e1000_autoneg_restart, + .vlan_set_tag = &e1000_vlan_set_tag, + + .defective_get_mode = &e1000_defective_get_mode, + .defective_set_mode = &e1000_defective_set_mode, + +}; + +/** Basic device operations for E1000 driver */ +static ddf_dev_ops_t e1000_dev_ops; + +static int e1000_add_device(ddf_dev_t *dev); + +/** Basic driver operations for E1000 driver */ +static driver_ops_t e1000_driver_ops = { + .add_device = e1000_add_device +}; + +/** Driver structure for E1000 driver */ +static driver_t e1000_driver = { + .name = NAME, + .driver_ops = &e1000_driver_ops +}; + +/* The default implementation callbacks */ +static int e1000_on_activating(nic_t *nic_data); +static int e1000_on_stopping(nic_t *nic_data); +static void e1000_write_packet(nic_t *nic_data, packet_t *packet); + +/** Commands to deal with interrupt + * + */ +irq_cmd_t e1000_irq_commands[] = { + { + /* Get the interrupt status */ + .cmd = CMD_PIO_READ_32, + .addr = NULL, + .dstarg = 2 + }, + { + .cmd = CMD_PREDICATE, + .value = 2, + .srcarg = 2 + }, + { + /* Disable interrupts until interrupt routine is finished */ + .cmd = CMD_PIO_WRITE_32, + .addr = NULL, + .value = 0xFFFFFFFF + }, + { + .cmd = CMD_ACCEPT + } +}; + +/** Interrupt code definition */ +irq_code_t e1000_irq_code = { + .cmdcount = sizeof(e1000_irq_commands)/sizeof(irq_cmd_t), + .cmds = e1000_irq_commands +}; + +/** Get the device information + * + * @param dev The NIC device + * @param info The information to fill + * @return EOK + */ +static int e1000_get_device_info(ddf_fun_t *dev, nic_device_info_t *info) +{ + assert(dev); + assert(info); + + bzero(info, sizeof(nic_device_info_t)); + + info->vendor_id = 0x8086; + str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH, "Intel Corporation"); + str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH, "Intel Pro"); + info->ethernet_support[ETH_10M] = ETH_10BASE_T; + info->ethernet_support[ETH_100M] = ETH_100BASE_TX; + info->ethernet_support[ETH_1000M] = ETH_1000BASE_T; + return EOK; +} + +/** Check the cable state + * + * @param[in] dev The device + * @param[out] state The state to fill + * @return EOK + */ +static int e1000_get_cable_state(ddf_fun_t *dev, nic_cable_state_t *state) +{ + assert(dev); + assert(DRIVER_DATA_DEV(dev)); + assert(state); + + e1000_t *e1000_data = DRIVER_DATA_DEV(dev); + if (E1000_REG_READ(e1000_data, E1000_STATUS) & (STATUS_LU)) { + *state = NIC_CS_PLUGGED; + } else { + *state = NIC_CS_UNPLUGGED; + } + + return EOK; +} + +static uint16_t e1000_calculate_itr_interval_from_usecs(suseconds_t useconds) { + return useconds * 4; +} + +/** Get operation mode of the device + */ +static int e1000_get_operation_mode(ddf_fun_t *dev, int *speed, + nic_channel_mode_t *duplex, nic_role_t *role) +{ + e1000_t *e1000_data = DRIVER_DATA_DEV(dev); + uint32_t status = E1000_REG_READ(e1000_data, E1000_STATUS); + + if (status & STATUS_FD) { + *duplex = NIC_CM_FULL_DUPLEX; + } else { + *duplex = NIC_CM_HALF_DUPLEX; + } + + uint32_t speed_bits = + (status >> STATUS_SPEED_SHIFT) & STATUS_SPEED_ALL; + + if (speed_bits == STATUS_SPEED_10) { + *speed = 10; + } else if (speed_bits == STATUS_SPEED_100) { + *speed = 100; + } else if ((speed_bits == STATUS_SPEED_1000A) + || (speed_bits == STATUS_SPEED_1000B)) { + *speed = 1000; + } + + *role = NIC_ROLE_UNKNOWN; + return EOK; +} + +static void e1000_link_restart(e1000_t * e1000_data) +{ + fibril_mutex_lock(&e1000_data->ctrl_lock);; + uint32_t ctrl = E1000_REG_READ(e1000_data, E1000_CTRL); + + if (ctrl & CTRL_SLU) { + ctrl &= ~(CTRL_SLU); + fibril_mutex_unlock(&e1000_data->ctrl_lock); + usleep(10); + fibril_mutex_lock(&e1000_data->ctrl_lock); + ctrl |= CTRL_SLU; + } + fibril_mutex_unlock(&e1000_data->ctrl_lock); + + e1000_link_restart(e1000_data); + +} + +/** Set operation mode of the device + * + */ +static int e1000_set_operation_mode(ddf_fun_t *dev, int speed, + nic_channel_mode_t duplex, nic_role_t role) +{ + if (speed != 10 && speed != 100 && speed != 1000) + return EINVAL; + if (duplex != NIC_CM_HALF_DUPLEX && duplex != NIC_CM_FULL_DUPLEX) + return EINVAL; + + e1000_t *e1000_data = DRIVER_DATA_DEV(dev); + fibril_mutex_lock(&e1000_data->ctrl_lock);; + uint32_t ctrl = E1000_REG_READ(e1000_data, E1000_CTRL); + + ctrl |= CTRL_FRCSPD; + ctrl |= CTRL_FRCDPLX; + ctrl &= ~(CTRL_ASDE); + + if (duplex == NIC_CM_FULL_DUPLEX) { + ctrl |= CTRL_FD; + } else { + ctrl &= ~(CTRL_FD); + } + + + ctrl &= ~(CTRL_SPEED_MASK); + if (speed == 1000) { + ctrl |= CTRL_SPEED_1000 << CTRL_SPEED_SHIFT; + } else if (speed == 100) { + ctrl |= CTRL_SPEED_100 << CTRL_SPEED_SHIFT; + } else { + ctrl |= CTRL_SPEED_10 << CTRL_SPEED_SHIFT; + } + + E1000_REG_WRITE(e1000_data, E1000_CTRL, ctrl); + fibril_mutex_unlock(&e1000_data->ctrl_lock); + + e1000_link_restart(e1000_data); + + return EOK; +} + +/** Enable autonegoation + * + * @param dev The device to update + * @param advertisement Ignored on E1000 + * @returns EOK if advertisement mode set successfully + */ +static int e1000_autoneg_enable(ddf_fun_t *dev, uint32_t advertisement) +{ + e1000_t *e1000_data = DRIVER_DATA_DEV(dev); + fibril_mutex_lock(&e1000_data->ctrl_lock); + uint32_t ctrl = E1000_REG_READ(e1000_data, E1000_CTRL); + + ctrl &= ~(CTRL_FRCSPD); + ctrl &= ~(CTRL_FRCDPLX); + ctrl |= CTRL_ASDE; + + E1000_REG_WRITE(e1000_data, E1000_CTRL, ctrl); + fibril_mutex_unlock(&e1000_data->ctrl_lock); + + e1000_link_restart(e1000_data); + + return EOK; +} + +/** Disable autonegoation + * + * @param dev The device to update + * @returns EOK + */ +static int e1000_autoneg_disable(ddf_fun_t *dev) +{ + e1000_t *e1000_data = DRIVER_DATA_DEV(dev); + fibril_mutex_lock(&e1000_data->ctrl_lock); + uint32_t ctrl = E1000_REG_READ(e1000_data, E1000_CTRL); + + ctrl |= CTRL_FRCSPD; + ctrl |= CTRL_FRCDPLX; + ctrl &= ~(CTRL_ASDE); + + E1000_REG_WRITE(e1000_data, E1000_CTRL, ctrl); + fibril_mutex_unlock(&e1000_data->ctrl_lock); + + e1000_link_restart(e1000_data); + + return EOK; +} + +/** Restart autonegoation + * + * @param dev The device to update + * @returns EOK if advertisement mode set successfully + */ +static int e1000_autoneg_restart(ddf_fun_t *dev) +{ + return e1000_autoneg_enable(dev, 0); +} + + +/** Get state of acceptance of weird packets + * + * @param device The device to check + * @param [out] mode The current mode + */ +static int e1000_defective_get_mode(ddf_fun_t *device, uint32_t *mode) +{ + e1000_t *e1000_data = DRIVER_DATA_DEV(device); + *mode = 0; + uint32_t rctl = E1000_REG_READ(e1000_data, E1000_RCTL); + if (rctl & RCTL_SBP) { + *mode = NIC_DEFECTIVE_BAD_CRC | NIC_DEFECTIVE_SHORT; + } + return EOK; +}; + +/** Set acceptance of weird packets + * + * @param device The device to update + * @param mode The mode to set + * @returns ENOTSUP if the mode is not supported + * @returns EOK of mode was set + */ +static int e1000_defective_set_mode(ddf_fun_t *device, uint32_t mode) +{ + + e1000_t *e1000_data = DRIVER_DATA_DEV(device); + fibril_mutex_lock(&e1000_data->rx_lock); + + int rc = EOK; + uint32_t rctl = E1000_REG_READ(e1000_data, E1000_RCTL); + bool short_mode = (mode & NIC_DEFECTIVE_SHORT ? true : false); + bool bad_mode = (mode & NIC_DEFECTIVE_BAD_CRC ? true : false); + if (short_mode && bad_mode) { + rctl |= RCTL_SBP; + } else if ((!short_mode) && (!bad_mode)) { + rctl &= ~RCTL_SBP; + } else { + rc = ENOTSUP; + } + E1000_REG_WRITE(e1000_data, E1000_RCTL, rctl); + fibril_mutex_unlock(&e1000_data->rx_lock); + return rc; +}; + + +/** Write receive address to RA registr + * + * @param e1000_data The E1000 data structure + * @param position RA register position + * @param address Ethernet address + * @param set_av_bit Set the Addtess Valid bit + */ +static void e1000_write_receive_address(e1000_t *e1000_data, + unsigned int position, const nic_address_t * address, + bool set_av_bit) +{ + uint8_t *mac0 = (uint8_t *)address->address; + uint8_t *mac1 = (uint8_t *)address->address + 1; + uint8_t *mac2 = (uint8_t *)address->address + 2; + uint8_t *mac3 = (uint8_t *)address->address + 3; + uint8_t *mac4 = (uint8_t *)address->address + 4; + uint8_t *mac5 = (uint8_t *)address->address + 5; + + uint32_t rah; + uint32_t ral; + + ral = ((*mac3) << 24) | ((*mac2) << 16) | ((*mac1) << 8) | (*mac0); + rah = ((*mac5) << 8) | ((*mac4)); + if (set_av_bit) { + rah |= RAH_AV; + } else { + rah |= E1000_REG_READ(e1000_data, E1000_RAH_ARRAY(position)) + & RAH_AV; + } + + E1000_REG_WRITE(e1000_data, E1000_RAH_ARRAY(position), rah); + E1000_REG_WRITE(e1000_data, E1000_RAL_ARRAY(position), ral); +} + +/** Disable receive address in RA registr + * Clears Address Valid bit + * + * @param e1000_data The E1000 data structure + * @param position RA register position + */ +static void e1000_disable_receive_address(e1000_t *e1000_data, + unsigned int position) +{ + uint32_t rah = E1000_REG_READ(e1000_data, E1000_RAH_ARRAY(position)); + rah = rah & ~RAH_AV; + E1000_REG_WRITE(e1000_data, E1000_RAH_ARRAY(position), rah); +} + +/** Clears all unicast addresses from RA registers + * + * @param e1000_data The E1000 data structure + */ +static void e1000_clear_unicast_receive_addresses(e1000_t *e1000_data) +{ + unsigned int ra_num; + for(ra_num = 1; ra_num <= e1000_data->unicast_ra_count; ra_num++) { + e1000_disable_receive_address(e1000_data, ra_num); + } + e1000_data->unicast_ra_count = 0; +} + +/** Clears all multicast addresses from RA registers + * + * @param e1000_data The E1000 data structure + */ +static void e1000_clear_multicast_receive_addresses(e1000_t *e1000_data) +{ + unsigned int first_multicast_ra_num = + E1000_RECEIVE_ADDRESS - e1000_data->multicast_ra_count; + unsigned int ra_num; + for (ra_num = E1000_RECEIVE_ADDRESS - 1; + ra_num >= first_multicast_ra_num; ra_num--) { + e1000_disable_receive_address(e1000_data, ra_num); + } + e1000_data->multicast_ra_count = 0; +} + +/** + * Returns receive address filter positions count usable for unicast + * + * @param e1000_data The E1000 data structure + * @return receive address filter positions count usable for unicast + */ +static unsigned int get_free_unicast_address_count(e1000_t *e1000_data) +{ + return E1000_RECEIVE_ADDRESS - 1 - e1000_data->multicast_ra_count; +} + +/** + * Returns receive address filter positions count usable for multicast + * + * @param e1000_data The E1000 data structure + * @return receive address filter positions count usable for multicast + */ +static unsigned int get_free_multicast_address_count(e1000_t *e1000_data) +{ + return E1000_RECEIVE_ADDRESS - 1 - e1000_data->unicast_ra_count; +} + +/** + * Writes unicast receive addresses to receive address filter registers + * + * @param e1000_data The E1000 data structure + * @param addr Pointer to address array + * @param addr_cnt Address array count + */ +static void e1000_add_unicast_receive_addresses(e1000_t *e1000_data, + const nic_address_t * addr, size_t addr_cnt) +{ + assert(addr_cnt <= get_free_unicast_address_count(e1000_data)); + nic_address_t * addr_iterator = (nic_address_t *) addr; + unsigned int ra_num; + // ra_num=0 is primary address + for (ra_num = 1; ra_num <= addr_cnt; ra_num++) { + e1000_write_receive_address(e1000_data, ra_num, addr_iterator, true); + addr_iterator++; + } +} + +/** + * Writes multicast receive addresses to receive address filter registers + * + * @param e1000_data The E1000 data structure + * @param addr Pointer to address array + * @param addr_cnt Address array count + */ +static void e1000_add_multicast_receive_addresses(e1000_t *e1000_data, + const nic_address_t * addr, size_t addr_cnt) +{ + nic_address_t * addr_iterator = (nic_address_t *) addr; + assert(addr_cnt <= get_free_multicast_address_count(e1000_data)); + unsigned int first_multicast_ra_num = E1000_RECEIVE_ADDRESS - addr_cnt; + unsigned int ra_num; + for ( + ra_num = E1000_RECEIVE_ADDRESS - 1; + ra_num >= first_multicast_ra_num; + ra_num-- + ) { + e1000_write_receive_address(e1000_data, ra_num, addr_iterator, true); + addr_iterator++; + } +} + +/** + * Disables receiving packets for default address + * + * @param e1000_data The E1000 data structure + */ +static void disable_ra0_address_filter(e1000_t *e1000_data) +{ + uint32_t rah0 = E1000_REG_READ(e1000_data, E1000_RAH_ARRAY(0)); + rah0 = rah0 & ~RAH_AV; + E1000_REG_WRITE(e1000_data, E1000_RAH_ARRAY(0), rah0); +} + +/** + * Enables receiving packets for default address + * + * @param e1000_data The E1000 data structure + */ +static void enable_ra0_address_filter(e1000_t *e1000_data) +{ + uint32_t rah0 = E1000_REG_READ(e1000_data, E1000_RAH_ARRAY(0)); + rah0 = rah0 | RAH_AV; + E1000_REG_WRITE(e1000_data, E1000_RAH_ARRAY(0), rah0); +} + +/** + * Disables unicast promiscuous mode + * + * @param e1000_data The E1000 data structure + */ +static void e1000_disable_unicast_promisc(e1000_t *e1000_data) +{ + uint32_t rctl = E1000_REG_READ(e1000_data, E1000_RCTL); + rctl = rctl & ~RCTL_UPE; + E1000_REG_WRITE(e1000_data, E1000_RCTL, rctl); +} + +/** + * Enables unicast promiscuous mode + * + * @param e1000_data The E1000 data structure + */ +static void e1000_enable_unicast_promisc(e1000_t *e1000_data) +{ + uint32_t rctl = E1000_REG_READ(e1000_data, E1000_RCTL); + rctl = rctl | RCTL_UPE; + E1000_REG_WRITE(e1000_data, E1000_RCTL, rctl); +} + +/** + * Disables multicast promiscuous mode + * + * @param e1000_data The E1000 data structure + */ +static void e1000_disable_multicast_promisc(e1000_t *e1000_data) +{ + uint32_t rctl = E1000_REG_READ(e1000_data, E1000_RCTL); + rctl = rctl & ~RCTL_MPE; + E1000_REG_WRITE(e1000_data, E1000_RCTL, rctl); +} + +/** + * Enables multicast promiscuous mode + * + * @param e1000_data The E1000 data structure + */ +static void e1000_enable_multicast_promisc(e1000_t *e1000_data) +{ + uint32_t rctl = E1000_REG_READ(e1000_data, E1000_RCTL); + rctl = rctl | RCTL_MPE; + E1000_REG_WRITE(e1000_data, E1000_RCTL, rctl); +} + +/** + * Enables accepting of broadcast packets + * + * @param e1000_data The E1000 data structure + */ +static void e1000_enable_broadcast_accept(e1000_t *e1000_data) +{ + uint32_t rctl = E1000_REG_READ(e1000_data, E1000_RCTL); + rctl = rctl | RCTL_BAM; + E1000_REG_WRITE(e1000_data, E1000_RCTL, rctl); +} + +/** + * Disables accepting of broadcast packets + * + * @param e1000_data The E1000 data structure + */ +static void e1000_disable_broadcast_accept(e1000_t *e1000_data) +{ + uint32_t rctl = E1000_REG_READ(e1000_data, E1000_RCTL); + rctl = rctl & ~RCTL_BAM; + E1000_REG_WRITE(e1000_data, E1000_RCTL, rctl); +} + +/** + * Enables VLAN filtering according to VFTA registers + * + * @param e1000_data The E1000 data structure + */ +static void e1000_enable_vlan_filter(e1000_t *e1000_data) +{ + uint32_t rctl = E1000_REG_READ(e1000_data, E1000_RCTL); + rctl = rctl | RCTL_VFE; + E1000_REG_WRITE(e1000_data, E1000_RCTL, rctl); +} + +/** + * Disables VLAN filtering + * + * @param e1000_data The E1000 data structure + */ +static void e1000_disable_vlan_filter(e1000_t *e1000_data) +{ + uint32_t rctl = E1000_REG_READ(e1000_data, E1000_RCTL); + rctl = rctl & ~RCTL_VFE; + E1000_REG_WRITE(e1000_data, E1000_RCTL, rctl); +} + + +/** Set multicast packets acceptance mode + * + * @param nic_data The nic device to update + * @param mode The mode to set + * @param addr address list - used in mode=NIC_MULTICAST_LIST + * @param addr_cnt length of address list - used in mode=NIC_MULTICAST_LIST + * + * @returns EOK + */ +static int e1000_on_multicast_mode_change(nic_t *nic_data, + nic_multicast_mode_t mode, const nic_address_t * addr, size_t addr_cnt) +{ + int rc = EOK; + e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data); + fibril_mutex_lock(&e1000_data->rx_lock); + switch (mode) { + case NIC_MULTICAST_BLOCKED: + e1000_clear_multicast_receive_addresses(e1000_data); + e1000_disable_multicast_promisc(e1000_data); + nic_report_hw_filtering(nic_data, -1, 1, -1); + break; + case NIC_MULTICAST_LIST: + e1000_clear_multicast_receive_addresses(e1000_data); + if (addr_cnt > get_free_multicast_address_count(e1000_data)) { + //TODO: fill MTA table + //not neccessary - it only saves some compares in NIC library + e1000_enable_multicast_promisc(e1000_data); + nic_report_hw_filtering(nic_data, -1, 0, -1); + } else { + e1000_disable_multicast_promisc(e1000_data); + e1000_add_multicast_receive_addresses(e1000_data, addr, addr_cnt); + nic_report_hw_filtering(nic_data, -1, 1, -1); + } + break; + case NIC_MULTICAST_PROMISC: + e1000_enable_multicast_promisc(e1000_data); + e1000_clear_multicast_receive_addresses(e1000_data); + nic_report_hw_filtering(nic_data, -1, 1, -1); + break; + default: + rc = ENOTSUP; + break; + } + fibril_mutex_unlock(&e1000_data->rx_lock); + return rc; +} +/** Set unicast packets acceptance mode + * + * @param nic_data The nic device to update + * @param mode The mode to set + * @param addr address list - used in mode=NIC_MULTICAST_LIST + * @param addr_cnt length of address list - used in mode=NIC_MULTICAST_LIST + * + * @returns EOK + */ +static int e1000_on_unicast_mode_change(nic_t *nic_data, + nic_unicast_mode_t mode, const nic_address_t * addr, size_t addr_cnt) +{ + int rc = EOK; + e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data); + fibril_mutex_lock(&e1000_data->rx_lock); + switch (mode) { + case NIC_UNICAST_BLOCKED: + disable_ra0_address_filter(e1000_data); + e1000_clear_unicast_receive_addresses(e1000_data); + e1000_disable_unicast_promisc(e1000_data); + nic_report_hw_filtering(nic_data, 1, -1, -1); + break; + case NIC_UNICAST_DEFAULT: + enable_ra0_address_filter(e1000_data); + e1000_clear_unicast_receive_addresses(e1000_data); + e1000_disable_unicast_promisc(e1000_data); + nic_report_hw_filtering(nic_data, 1, -1, -1); + break; + case NIC_UNICAST_LIST: + enable_ra0_address_filter(e1000_data); + e1000_clear_unicast_receive_addresses(e1000_data); + if (addr_cnt > get_free_unicast_address_count(e1000_data)) { + e1000_enable_unicast_promisc(e1000_data); + nic_report_hw_filtering(nic_data, 0, -1, -1); + } else { + e1000_disable_unicast_promisc(e1000_data); + e1000_add_unicast_receive_addresses(e1000_data, addr, addr_cnt); + nic_report_hw_filtering(nic_data, 1, -1, -1); + } + break; + case NIC_UNICAST_PROMISC: + e1000_enable_unicast_promisc(e1000_data); + enable_ra0_address_filter(e1000_data); + e1000_clear_unicast_receive_addresses(e1000_data); + nic_report_hw_filtering(nic_data, 1, -1, -1); + break; + default: + rc = ENOTSUP; + break; + } + fibril_mutex_unlock(&e1000_data->rx_lock); + return rc; +} + +/** Set broadcast packets acceptance mode + * + * @param nic_data The nic device to update + * @param mode The mode to set + * + * @returns EOK + */ +static int e1000_on_broadcast_mode_change(nic_t *nic_data, + nic_broadcast_mode_t mode) +{ + int rc = EOK; + e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data); + fibril_mutex_lock(&e1000_data->rx_lock); + + switch (mode) { + case NIC_BROADCAST_BLOCKED: + e1000_disable_broadcast_accept(e1000_data); + break; + case NIC_BROADCAST_ACCEPTED: + e1000_enable_broadcast_accept(e1000_data); + break; + default: + rc = ENOTSUP; + break; + } + fibril_mutex_unlock(&e1000_data->rx_lock); + return rc; +} + +/** + * Checks if receiving is enabled + * + * @param e1000_data The E1000 data structure + * @return true if receiving is enabled + */ +static bool e1000_is_rx_enabled(e1000_t *e1000_data) +{ + if (E1000_REG_READ(e1000_data, E1000_RCTL) & (RCTL_EN)) { + return true; + } else { + return false; + } +} + +/** + * Enables receiving + * + * @param e1000_data The E1000 data structure + */ +static void e1000_enable_rx(e1000_t *e1000_data) +{ + //setting Receive Enable Bit + E1000_REG_WRITE(e1000_data, E1000_RCTL, + E1000_REG_READ(e1000_data, E1000_RCTL) | (RCTL_EN)); +} + +/** + * Disables receiving + * + * @param e1000_data The E1000 data structure + */ +static void e1000_disable_rx(e1000_t *e1000_data) +{ + //clearing Receive Enable Bit + E1000_REG_WRITE(e1000_data, E1000_RCTL, + E1000_REG_READ(e1000_data, E1000_RCTL) & ~(RCTL_EN)); +} + + +/** Set VLAN mask + * + * @param nic_data The nic device to update + * @param vlan_mask VLAN mask + */ +static void e1000_on_vlan_mask_change(nic_t *nic_data, + const nic_vlan_mask_t * vlan_mask) +{ + e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data); + + fibril_mutex_lock(&e1000_data->rx_lock); + if (vlan_mask) { + bool rx_enabled = e1000_is_rx_enabled(e1000_data); + if (rx_enabled) { + //Disable receiving, so that packet matching + //partially written wlan is not received + e1000_disable_rx(e1000_data); + } + int i; + for (i = 0; i < NIC_VLAN_BITMAP_SIZE; i += 4) { + uint32_t bitmap_part = + ((uint32_t) vlan_mask->bitmap[i]) | + (((uint32_t) vlan_mask->bitmap[i + 1]) << 8) | + (((uint32_t) vlan_mask->bitmap[i + 2]) << 16) | + (((uint32_t) vlan_mask->bitmap[i + 3]) << 24); + E1000_REG_WRITE(e1000_data, E1000_VFTA_ARRAY(i / 4), bitmap_part); + } + e1000_enable_vlan_filter(e1000_data); + if (rx_enabled) { + e1000_enable_rx(e1000_data); + } + } else { + e1000_disable_vlan_filter(e1000_data); + } + fibril_mutex_unlock(&e1000_data->rx_lock); + +} + +/** Set VLAN mask + * + * @param device The E1000 device + * @param tag VLAN tag + * + * @return EOK + * @return ENOTSUP + */ +static int e1000_vlan_set_tag(ddf_fun_t *device, uint16_t tag, int add, + int strip) +{ + + //VLAN CFI bit cannot be set + if (tag & VLANTAG_CFI) { + return ENOTSUP; + } + if (!strip && add) { + //CTRL.VME is neccessary for both strip and add + //but CTRL.VME means stripping tags on receive + return ENOTSUP; + } + + e1000_t *e1000_data = DRIVER_DATA_DEV(device); + e1000_data->vlan_tag = tag; + e1000_data->vlan_tag_add = add; + + fibril_mutex_lock(&e1000_data->ctrl_lock); + uint32_t ctrl = E1000_REG_READ(e1000_data, E1000_CTRL); + if (strip) { + ctrl |= CTRL_VME; + } else { + ctrl &= ~CTRL_VME; + } + E1000_REG_WRITE(e1000_data, E1000_CTRL, ctrl); + fibril_mutex_unlock(&e1000_data->ctrl_lock); + + return EOK; +} + +/** Fill receive descriptor with new empty packet + * stores packet in e1000_data->rx_ring_packets + * + * @param nic_data NIC data stricture + * @param offset Receive descriptor offset + */ +static void e1000_fill_new_rx_descriptor(nic_t *nic_data, unsigned int offset) +{ + e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data); + + packet_t *packet = nic_alloc_packet(nic_data, E1000_MAX_RECEIVE_PACKET_SIZE); + + assert(packet); + + *(e1000_data->rx_ring_packets + offset) = packet; + e1000_rx_descriptor_t * rx_descriptor = (e1000_rx_descriptor_t *) + (e1000_data->rx_ring.virtual + + offset * sizeof(e1000_rx_descriptor_t)); + + void * phys_addr = nic_dma_lock_packet(packet); + + if (phys_addr) { + rx_descriptor->phys_addr = PTR_TO_U64(phys_addr + + packet->data_start); + } else { + rx_descriptor->phys_addr = 0; + } + rx_descriptor->length = 0; + rx_descriptor->checksum = 0; + rx_descriptor->status = 0; + rx_descriptor->errors = 0; + rx_descriptor->special = 0; + +} + +/** Clear receive descriptor + * + * @param e1000_data E1000 data + * @param offset Receive descriptor offset + */ +static void e1000_clear_rx_descriptor(e1000_t *e1000_data, unsigned int offset) { + + e1000_rx_descriptor_t * rx_descriptor = (e1000_rx_descriptor_t *) + (e1000_data->rx_ring.virtual + + offset * sizeof(e1000_rx_descriptor_t)); + + rx_descriptor->length = 0; + rx_descriptor->checksum = 0; + rx_descriptor->status = 0; + rx_descriptor->errors = 0; + rx_descriptor->special = 0; +} + +/** Clear receive descriptor + * + * @param nic_data NIC data + * @param offset Receive descriptor offset + */ +static void e1000_clear_tx_descriptor(nic_t *nic_data, unsigned int offset) +{ + e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data); + + e1000_tx_descriptor_t * tx_descriptor = (e1000_tx_descriptor_t *) + (e1000_data->tx_ring.virtual + + offset * sizeof(e1000_tx_descriptor_t)); + + if (tx_descriptor->length) { + packet_t * old_packet = *(e1000_data->tx_ring_packets + offset); + if (old_packet) { + nic_release_packet(nic_data, old_packet); + } + } + tx_descriptor->phys_addr = 0; + tx_descriptor->length = 0; + tx_descriptor->checksum_offset = 0; + tx_descriptor->command = 0; + tx_descriptor->status = 0; + tx_descriptor->checksum_start_field = 0; + tx_descriptor->special = 0; +} + +/** Increment tail pointer for receive or transmit ring + * + * @param tail old Tail + * @param descriptors_count ring length + * + * @return new tail + */ +static uint32_t e1000_inc_tail(uint32_t tail, uint32_t descriptors_count) +{ + if (tail + 1 == descriptors_count) { + return 0; + } else { + return tail + 1; + } +} + +/** Receive packets + * + * @param nic_data The NIC data + */ + +static void e1000_receive_packets(nic_t *nic_data) +{ + e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data); + + fibril_mutex_lock(&e1000_data->rx_lock); + + uint32_t * tail_addr = E1000_REG_ADDR(e1000_data, E1000_RDT); + uint32_t next_tail; + next_tail = e1000_inc_tail(*tail_addr, E1000_RX_PACKETS_COUNT); + e1000_rx_descriptor_t * rx_descriptor = (e1000_rx_descriptor_t *) + (e1000_data->rx_ring.virtual + + next_tail * sizeof(e1000_rx_descriptor_t)); + while (rx_descriptor->status & 0x1) { + uint32_t packet_size = rx_descriptor->length - E1000_CRC_SIZE; + + packet_t * packet = *(e1000_data->rx_ring_packets + next_tail); + packet_suffix(packet, packet_size); + + nic_dma_unlock_packet(packet); + nic_received_packet(nic_data, packet); + + e1000_fill_new_rx_descriptor(nic_data, next_tail); + + *tail_addr = e1000_inc_tail(* tail_addr, E1000_RX_PACKETS_COUNT); + next_tail = e1000_inc_tail(*tail_addr, E1000_RX_PACKETS_COUNT); + + rx_descriptor = (e1000_rx_descriptor_t *) + (e1000_data->rx_ring.virtual + + next_tail * sizeof(e1000_rx_descriptor_t)); + } + + fibril_mutex_unlock(&e1000_data->rx_lock); +} + +/** + * Enable E1000 interupts + * + * @param e1000_data The E1000 data structure + */ +static void e1000_enable_interrupts(e1000_t * e1000_data) +{ + E1000_REG_WRITE(e1000_data, E1000_IMS, ICR_RXT0); +} + +/** + * Disable E1000 interupts + * + * @param e1000_data The E1000 data structure + */ +static void e1000_disable_interrupts(e1000_t * e1000_data) +{ + E1000_REG_WRITE(e1000_data, E1000_IMS, 0); +} + +/** Interrupt handler implementation + * It is called from e1000_interrupt_handler() and e1000_poll() + * + * @param nic_data The NIC data + * @param icr ICR register value + */ +static void e1000_interrupt_handler_impl(nic_t * nic_data, uint32_t icr) { + if (icr & ICR_RXT0) { + e1000_receive_packets(nic_data); + } +} + +/** Handle device interrupt + * + * @param dev The e1000 device + * @param iid The IPC call id + * @param icall The IPC call structure + */ +static void e1000_interrupt_handler(ddf_dev_t *dev, ipc_callid_t iid, + ipc_call_t *icall) +{ + uint32_t icr = (uint32_t) IPC_GET_ARG2(*icall); + nic_t *nic_data = NIC_DATA_DEV(dev); + e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data); + + e1000_interrupt_handler_impl(nic_data, icr); + e1000_enable_interrupts(e1000_data); +}; + +/** Register interrupt handler for the card in the system + * + * Note: the global irq_reg_mutex is locked because of work with global + * structure. + * + * @param nic_data The driver data + * @return EOK if the handler was registered, negative error code otherwise + */ +inline static int e1000_register_int_handler(nic_t *nic_data) +{ + e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data); + + /* Lock the mutex in whole driver while working with global structure */ + fibril_mutex_lock(&irq_reg_mutex); + + /* TODO remove this dirty hack after accessing memmory mapped registers + * from interrupt pseudeocode is fixed + * + * dirty hack allowing accessing E1000 registers from interrupt + * handler + * 0xffff800000000000 is PA2KA mapping on amd64 + * on ia32 adding it does nothing + * see also + * kernel/arch/amd64/src/mm/page.c + * kernel/arch/ia32/src/mm/page.c + * */ + e1000_irq_code.cmds[0].addr = 0xffff800000000000 + + e1000_data->phys_reg_base + E1000_ICR; + e1000_irq_code.cmds[2].addr = 0xffff800000000000 + + e1000_data->phys_reg_base + E1000_IMC; + /* End of dirty hack */ + + int rc = register_interrupt_handler( + nic_get_ddf_dev(nic_data), + e1000_data->irq, + e1000_interrupt_handler, + &e1000_irq_code + ); + + fibril_mutex_unlock(&irq_reg_mutex); + + return rc; +} + +/** Force receiving all packets in the receive buffer + * + * @param nic_data The NIC data + */ +static void e1000_poll(nic_t *nic_data) +{ + assert(nic_data); + e1000_t *e1000_data = nic_get_specific(nic_data); + assert(e1000_data); + + uint32_t icr = E1000_REG_READ(e1000_data, E1000_ICR); + e1000_interrupt_handler_impl(nic_data, icr); +} + +/** Calculates ITR register interrupt from timeval structure + * + * @param period Period + */ +static uint16_t e1000_calculate_itr_interval(const struct timeval *period) { + //TODO use also tv_sec + return e1000_calculate_itr_interval_from_usecs(period->tv_usec); +} + +/** Set polling mode + * + * @param device The device to set + * @param mode The mode to set + * @param period The period for NIC_POLL_PERIODIC + * + * @returns EOK if succeed + * @returns ENOTSUP if the mode is not supported + */ +static int e1000_poll_mode_change(nic_t *nic_data, nic_poll_mode_t mode, + const struct timeval *period) +{ + assert(nic_data); + + e1000_t *e1000_data = nic_get_specific(nic_data); + assert(e1000_data); + + switch(mode) { + case NIC_POLL_IMMEDIATE: + E1000_REG_WRITE(e1000_data, E1000_ITR, 0); + e1000_enable_interrupts(e1000_data); + break; + case NIC_POLL_ON_DEMAND: + e1000_disable_interrupts(e1000_data); + break; + case NIC_POLL_PERIODIC: + assert(period); + uint16_t itr_interval = e1000_calculate_itr_interval(period); + E1000_REG_WRITE(e1000_data, E1000_ITR, (uint32_t) itr_interval); + e1000_enable_interrupts(e1000_data); + break; + default: + return ENOTSUP; + } + + return EOK; +} + +/** + * Initialize receive registers + * + * @param e1000_data The E1000 data structure + */ +static void e1000_initialize_rx_registers(e1000_t * e1000_data) +{ + E1000_REG_WRITE(e1000_data, E1000_RDLEN, E1000_RX_PACKETS_COUNT * 16); + E1000_REG_WRITE(e1000_data, E1000_RDH, 0); + //It is not posible to let HW use all descriptors + E1000_REG_WRITE(e1000_data, E1000_RDT, E1000_RX_PACKETS_COUNT - 1); + + //set broadcast enable bit + E1000_REG_WRITE(e1000_data, E1000_RCTL, RCTL_BAM); +} + +/** Initializes receive structure + * + * @param nic_data The NIC data + * @return EOK if succeed, negative error code otherwise + */ +static int e1000_initialize_rx_structure(nic_t *nic_data) +{ + e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data); + fibril_mutex_lock(&e1000_data->rx_lock); + + e1000_data->rx_ring.size = ALIGN_UP(E1000_RX_PACKETS_COUNT * + sizeof(e1000_rx_descriptor_t), PAGE_SIZE) / PAGE_SIZE; + e1000_data->rx_ring.mapping_flags = AS_AREA_READ | AS_AREA_WRITE; + int rc = dma_allocate_anonymous(&e1000_data->rx_ring, 0); + if( rc != EOK ) { + nlog_error("Can not allocate rx ring."); + return rc; + } + + E1000_REG_WRITE(e1000_data, E1000_RDBAH, + (uint32_t) (PTR_TO_U64(e1000_data->rx_ring.physical) >> 32)); + E1000_REG_WRITE(e1000_data, E1000_RDBAL, + (uint32_t) PTR_TO_U64(e1000_data->rx_ring.physical)); + + e1000_data->rx_ring_packets = + malloc(E1000_RX_PACKETS_COUNT * sizeof(packet_t *)); + + //write descriptor + unsigned int offset; + for (offset = 0; offset < E1000_RX_PACKETS_COUNT; offset++) { + e1000_fill_new_rx_descriptor(nic_data, offset); + } + + e1000_initialize_rx_registers(e1000_data); + + fibril_mutex_unlock(&e1000_data->rx_lock); + + return EOK; +} + +/** Uninitializes receive structure + * + * @param nic_data The NIC data + */ +static void e1000_uninitialize_rx_structure(nic_t *nic_data) +{ + e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data); + + //write descriptor + unsigned int offset; + for (offset = 0; offset < E1000_RX_PACKETS_COUNT; offset++) { + packet_t * packet = *(e1000_data->rx_ring_packets + offset); + nic_dma_unlock_packet(packet); + nic_release_packet(nic_data, packet); + } + + free(e1000_data->rx_ring_packets); + + dma_free(&e1000_data->rx_ring); +} + +/** Clear receive descriptor ring + * + * @param e1000_data The E1000 data + */ +static void e1000_clear_rx_ring(e1000_t * e1000_data) +{ + //write descriptor + unsigned int offset; + for (offset = 0; offset < E1000_RX_PACKETS_COUNT; offset++) { + e1000_clear_rx_descriptor(e1000_data, offset); + } +} + +/** Initialize filters + * + * @param e1000_data The E1000 data + */ +static void e1000_initialize_filters(e1000_t *e1000_data) +{ + //initialize address filter + e1000_data->unicast_ra_count = 0; + e1000_data->multicast_ra_count = 0; + e1000_clear_unicast_receive_addresses(e1000_data); +} + +/** Initialize VLAN + * + * @param e1000_data The E1000 data + */ +static void e1000_initialize_vlan(e1000_t *e1000_data) +{ + e1000_data->vlan_tag_add = false; +} + +/** Fill mac address from EEPROM to RA[0] register + * + * @param e1000_data The E1000 data + */ +static void e1000_fill_mac_from_eeprom(e1000_t *e1000_data) +{ + //mac address from eeprom to RA[0] + nic_address_t address; + e1000_eeprom_get_address(e1000_data, &address); + e1000_write_receive_address(e1000_data, 0, &address, true); +} + +/** Initializes other registers + * + * @param dev The E1000 data. + * @return EOK if succeed, negative error code otherwise + */ +static void e1000_initialize_registers(e1000_t * e1000_data) +{ + E1000_REG_WRITE(e1000_data, E1000_ITR, + e1000_calculate_itr_interval_from_usecs( + E1000_DEFAULT_INTERRUPT_INTEVAL_USEC)); + E1000_REG_WRITE(e1000_data, E1000_FCAH, 0); + E1000_REG_WRITE(e1000_data, E1000_FCAL, 0); + E1000_REG_WRITE(e1000_data, E1000_FCT, 0); + E1000_REG_WRITE(e1000_data, E1000_FCTTV, 0); + E1000_REG_WRITE(e1000_data, E1000_VET, VET_VALUE); + E1000_REG_WRITE(e1000_data, E1000_CTRL, CTRL_ASDE); +} + +/** Initializes transmit registers + * + * @param e1000_data The E1000 data. + */ +static void e1000_initialize_tx_registers(e1000_t * e1000_data) +{ + + E1000_REG_WRITE(e1000_data, E1000_TDLEN, E1000_TX_PACKETS_COUNT * 16); + E1000_REG_WRITE(e1000_data, E1000_TDH, 0); + E1000_REG_WRITE(e1000_data, E1000_TDT, 0); + + E1000_REG_WRITE(e1000_data, E1000_TIPG, + 10 << TIPG_IPGT_SHIFT | + 8 << TIPG_IPGR1_SHIFT | + 6 << TIPG_IPGR2_SHIFT + ); + E1000_REG_WRITE(e1000_data, E1000_TCTL, + //Collision Threshold + 0x0F << TCTL_CT_SHIFT | + //Collision DISTANCE + 0x40 << TCTL_COLD_SHIFT | + //Pad Short Packets + TCTL_PSP + ); + +} + +/** Initialize transmit structure + * + * @param e1000_data The E1000 data. + */ +static int e1000_initialize_tx_structure(e1000_t * e1000_data) +{ + + fibril_mutex_lock(&e1000_data->tx_lock); + + e1000_data->tx_ring.size = ALIGN_UP(E1000_TX_PACKETS_COUNT * + sizeof(e1000_tx_descriptor_t), PAGE_SIZE) / PAGE_SIZE; + e1000_data->tx_ring.mapping_flags = AS_AREA_READ | AS_AREA_WRITE; + int rc = dma_allocate_anonymous(&e1000_data->tx_ring, 0); + if( rc != EOK ) { + nlog_error("Can not allocate tx ring."); + return rc; + } + + bzero(e1000_data->tx_ring.virtual, + E1000_TX_PACKETS_COUNT * sizeof(e1000_tx_descriptor_t)); + + E1000_REG_WRITE(e1000_data, E1000_TDBAH, + (uint32_t) (PTR_TO_U64(e1000_data->tx_ring.physical) >> 32)); + E1000_REG_WRITE(e1000_data, E1000_TDBAL, + (uint32_t) PTR_TO_U64(e1000_data->tx_ring.physical)); + + e1000_data->tx_ring_packets = malloc(E1000_TX_PACKETS_COUNT * + sizeof(packet_t *)); + + + e1000_initialize_tx_registers(e1000_data); + + fibril_mutex_unlock(&e1000_data->tx_lock); + + return EOK; +} + +/** Uninitializes transmit structure + * + * @param nic_data The NIC data + */ +static void e1000_uninitialize_tx_structure(e1000_t * e1000_data) +{ + free(e1000_data->tx_ring_packets); + + dma_free(&e1000_data->tx_ring); +} + + +/** Clear transmit descriptor ring + * + * @param nic_data The NIC data + */ +static void e1000_clear_tx_ring(nic_t * nic_data) +{ + //write descriptor + unsigned int offset; + for (offset = 0; offset < E1000_TX_PACKETS_COUNT; offset++) { + e1000_clear_tx_descriptor(nic_data, offset); + } +} + +/** Enable transmit + * + * @param e1000_data The E1000 data + */ +static void e1000_enable_tx(e1000_t *e1000_data) +{ + //setting Transmit Enable Bit + E1000_REG_WRITE(e1000_data, E1000_TCTL, + E1000_REG_READ(e1000_data, E1000_TCTL) | (TCTL_EN)); +} + +/** Disable transmit + * + * @param e1000_data The E1000 data + */ +static void e1000_disable_tx(e1000_t *e1000_data) +{ + //clearing Transmit Enable Bit + E1000_REG_WRITE(e1000_data, E1000_TCTL, + E1000_REG_READ(e1000_data, E1000_TCTL) & ~(TCTL_EN)); +} + +/** Reset E1000 device + * + * @param e1000_data The E1000 data + */ +static int e1000_reset(nic_t *nic_data) +{ + e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data); + + E1000_REG_WRITE(e1000_data, E1000_CTRL, CTRL_RST); + //wait for the reset + usleep(10); + //check if RST_BIT cleared + assert(! (E1000_REG_READ(e1000_data, E1000_CTRL) + & (CTRL_RST))); + + e1000_initialize_registers(e1000_data); + e1000_initialize_rx_registers(e1000_data); + e1000_initialize_tx_registers(e1000_data); + + e1000_fill_mac_from_eeprom(e1000_data); + + e1000_initialize_filters(e1000_data); + + e1000_initialize_vlan(e1000_data); + + return EOK; + +} + + +/** Activate the device to receive and transmit packets + * + * @param nic_data The nic driver data + * @return EOK if activated successfully, error code otherwise + */ +static int e1000_on_activating(nic_t *nic_data) +{ + assert(nic_data); + + e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data); + + fibril_mutex_lock(&e1000_data->rx_lock); + fibril_mutex_lock(&e1000_data->tx_lock); + fibril_mutex_lock(&e1000_data->ctrl_lock); + + e1000_enable_interrupts(e1000_data); + + nic_enable_interrupt(nic_data, e1000_data->irq); + + e1000_clear_rx_ring(e1000_data); + e1000_enable_rx(e1000_data); + + e1000_clear_tx_ring(nic_data); + e1000_enable_tx(e1000_data); + + uint32_t ctrl = E1000_REG_READ(e1000_data, E1000_CTRL); + ctrl |= CTRL_SLU; + E1000_REG_WRITE(e1000_data, E1000_CTRL, ctrl); + + fibril_mutex_unlock(&e1000_data->ctrl_lock); + fibril_mutex_unlock(&e1000_data->tx_lock); + fibril_mutex_unlock(&e1000_data->rx_lock); + + return EOK; +} + +/** Callback for NIC_STATE_DOWN change + * + * @param nic_data The nic driver data + * @return EOK if succeed, error code otherwise + */ +static int e1000_on_down_unlocked(nic_t *nic_data) +{ + e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data); + + uint32_t ctrl = E1000_REG_READ(e1000_data, E1000_CTRL); + ctrl &= ~CTRL_SLU; + E1000_REG_WRITE(e1000_data, E1000_CTRL, ctrl); + + e1000_disable_tx(e1000_data); + + e1000_disable_rx(e1000_data); + + nic_disable_interrupt(nic_data, e1000_data->irq); + + e1000_disable_interrupts(e1000_data); + + //wait for the for the end of all data transfers to descriptors + usleep(100); + + return EOK; +} + +/** Callback for NIC_STATE_DOWN change + * + * @param nic_data The nic driver data + * @return EOK if succeed, error code otherwise + */ +static int e1000_on_down(nic_t *nic_data) +{ + e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data); + + fibril_mutex_lock(&e1000_data->rx_lock); + fibril_mutex_lock(&e1000_data->tx_lock); + fibril_mutex_lock(&e1000_data->ctrl_lock); + + int rc = e1000_on_down_unlocked(nic_data); + + fibril_mutex_unlock(&e1000_data->ctrl_lock); + fibril_mutex_unlock(&e1000_data->tx_lock); + fibril_mutex_unlock(&e1000_data->rx_lock); + + return rc; +} + +/** Callback for NIC_STATE_STOPPED change + * + * @param nic_data The nic driver data + * @return EOK if succeed, error code otherwise + */ +static int e1000_on_stopping(nic_t *nic_data) +{ + e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data); + + fibril_mutex_lock(&e1000_data->rx_lock); + fibril_mutex_lock(&e1000_data->tx_lock); + fibril_mutex_lock(&e1000_data->ctrl_lock); + + int rc = e1000_on_down_unlocked(nic_data); + if (rc == EOK) { + rc = e1000_reset(nic_data); + } + + fibril_mutex_unlock(&e1000_data->ctrl_lock); + fibril_mutex_unlock(&e1000_data->tx_lock); + fibril_mutex_unlock(&e1000_data->rx_lock); + + return rc; +} + + + +/** Create driver data structure + * + * @return Intialized device data structure or NULL + */ +static e1000_t *e1000_create_dev_data(ddf_dev_t *dev) +{ + assert(dev); + assert(!dev->driver_data); + + nic_t *nic_data = nic_create_and_bind(dev); + if (!nic_data) + return NULL; + + e1000_t *e1000_data = malloc(sizeof(e1000_t)); + if (!e1000_data) { + nic_unbind_and_destroy(dev); + return NULL; + } + + bzero(e1000_data, sizeof(e1000_t)); + + nic_set_specific(nic_data, e1000_data); + nic_set_write_packet_handler(nic_data, e1000_write_packet); + nic_set_state_change_handlers( + nic_data, + e1000_on_activating, + e1000_on_down, + e1000_on_stopping + ); + nic_set_filtering_change_handlers( + nic_data, + e1000_on_unicast_mode_change, + e1000_on_multicast_mode_change, + e1000_on_broadcast_mode_change, + NULL, + e1000_on_vlan_mask_change + ); + + nic_set_poll_handlers(nic_data, e1000_poll_mode_change, e1000_poll); + + fibril_mutex_initialize(&e1000_data->ctrl_lock); + fibril_mutex_initialize(&e1000_data->rx_lock); + fibril_mutex_initialize(&e1000_data->tx_lock); + fibril_mutex_initialize(&e1000_data->eeprom_lock); + + return e1000_data; +} + +/** Delete driver data structure if not null and null the pointer + * + * @param data The e1000 device data structure + */ +inline static void e1000_delete_dev_data(ddf_dev_t *dev) +{ + assert(dev); + if (dev->driver_data != NULL) + nic_unbind_and_destroy(dev); +} + +/** Clean up the e1000 device structure. + * + * @param dev The device structure. + */ +static void e1000_dev_cleanup(ddf_dev_t *dev) +{ + assert(dev); + + e1000_delete_dev_data(dev); + + if (dev->parent_sess != NULL) { + async_hangup(dev->parent_sess); + dev->parent_sess = NULL; + } +} + +/** Fill the irq and io_addr part of device data structure + * + * The hw_resources must be obtained before calling this function + * + * @param dev The device structure + * @param hw_resources Drive hardware resources obtained from the parent device + * @return EOK if succeed, negative error code otherwise + */ +static int e1000_fill_resource_info(ddf_dev_t *dev, const hw_res_list_parsed_t + *hw_resources) +{ + assert(dev != NULL); + assert(hw_resources != NULL); + assert(dev->driver_data != NULL); + + e1000_t *e1000_data = DRIVER_DATA_DEV(dev); + + if (hw_resources->irqs.count != 1) { + nlog_error("%s device: unexpected irq count", dev->name); + return EINVAL; + }; + + e1000_data->irq = hw_resources->irqs.irqs[0]; + + e1000_data->phys_reg_base = + MEMADDR_TO_PTR(hw_resources->mem_ranges.ranges[0].address); + //TODO remove when hack is not neccessary + nlog_info("%s DIRTY HACK: FILL THIS ADDRESS %p " + "to kernel/arch/(ia32|amd64)/src/mm/page.c ", dev->name, + e1000_data->phys_reg_base); + + return EOK; +} + +/** Obtain information about hardware resources of the device + * + * The device must be connected to the parent + * + * @param dev The device structure + * @return EOK if succeed, negative error code otherwise + */ +static int e1000_get_resource_info(ddf_dev_t *dev) +{ + assert(dev != NULL); + assert(NIC_DATA_DEV(dev) != NULL); + + hw_res_list_parsed_t hw_res_parsed; + hw_res_list_parsed_init(&hw_res_parsed); + + /* Get hw resources form parent driver */ + int rc = nic_get_resources(NIC_DATA_DEV(dev), &hw_res_parsed); + if (rc != EOK) + return rc; + + /* Fill resources information to the device */ + rc = e1000_fill_resource_info(dev, &hw_res_parsed); + hw_res_list_parsed_clean(&hw_res_parsed); + + return rc; +} + +/** Initialize the e1000 device structure + * + * @param dev The device information + * @return EOK if succeed, negative error code otherwise + */ +static int e1000_device_initialize(ddf_dev_t *dev) +{ + int rc = EOK; + + /* Allocate driver data for the device. */ + e1000_t *e1000_data = e1000_create_dev_data(dev); + if (e1000_data == NULL) { + nlog_error("Not enough memory for initializing %s.", dev->name); + return ENOMEM; + } + + /* Obtain and fill hardware resources info */ + rc = e1000_get_resource_info(dev); + if (rc != EOK) { + nlog_error("Can not obatin hw resources information"); + goto failed; + } + + rc = pci_config_space_read_16(dev->parent_sess, PCI_DEVICE_ID, + &e1000_data->device_id); + if (rc != EOK) { + nlog_error("Can not load PCI device_id."); + goto failed; + } + + return rc; + +failed: + nlog_error("The device initialization failed"); + e1000_dev_cleanup(dev); + return rc; +} + +/** Enable the i/o ports of the device. + * + * @param dev The E1000 device. + * @return EOK if successed, negative error code otherwise + */ +static int e1000_pio_enable(ddf_dev_t *dev) +{ + e1000_t *e1000_data = DRIVER_DATA_DEV(dev); + + /* Gain control over port's registers. */ + if (pio_enable(e1000_data->phys_reg_base, 8 * PAGE_SIZE, + &e1000_data->virt_reg_base)) { //TODO 8*PAGE_SIZE nahradit + nlog_error( + "Cannot gain the memory mapped registers %lx for device %s.", + e1000_data->phys_reg_base, + dev->name + ); + return EADDRNOTAVAIL; + } + + return EOK; +} + +/** The add_device callback of E1000 callback + * + * Probe and initialize the newly added device. + * + * @param dev The E1000 device. + */ +int e1000_add_device(ddf_dev_t *dev) +{ + assert(dev); + + /* Init device structure for e1000 */ + int rc = e1000_device_initialize(dev); + if (rc != EOK) + return rc; + + // Device initialization + nic_t * nic_data = dev->driver_data; + + e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data); + + /* Map registers */ + rc = e1000_pio_enable(dev); + if (rc != EOK) + goto err_destroy; + + e1000_initialize_registers(e1000_data); + + rc = e1000_initialize_tx_structure(e1000_data); + if( rc!= EOK ) + goto err_pio; + + fibril_mutex_lock(&e1000_data->rx_lock); + + e1000_fill_mac_from_eeprom(e1000_data); + e1000_initialize_filters(e1000_data); + + fibril_mutex_unlock(&e1000_data->rx_lock); + + e1000_initialize_vlan(e1000_data); + + rc = nic_register_as_ddf_fun(nic_data, &e1000_dev_ops); + if (rc != EOK) { + nlog_error("Failed to register as DDF function - error %d", rc); + goto err_tx_structure; + } + + rc = e1000_register_int_handler(nic_data); + if (rc != EOK) { + goto err_tx_structure; + } + + rc = nic_connect_to_services(nic_data); + if (rc != EOK) { + nlog_error("Failed to connect to essential services - error %d", rc); + goto err_irq; + } + + rc = e1000_initialize_rx_structure(nic_data); + if (rc != EOK) { + nlog_error("Failed to init rx - error %d", rc); + goto err_irq; + } + + nic_address_t e1000_address; + e1000_get_address(e1000_data, &e1000_address); + rc = nic_report_address(nic_data, &e1000_address); + if (rc != EOK) { + nlog_error("Failed to setup address - error %d", rc); + goto err_rx_structure; + } + + struct timeval period; + period.tv_sec = 0; + period.tv_usec = E1000_DEFAULT_INTERRUPT_INTEVAL_USEC; + rc = nic_report_poll_mode(nic_data, NIC_POLL_PERIODIC, &period); + if (rc != EOK) { + nlog_error("Failed report poll mode %d", rc); + goto err_rx_structure; + } + + nlog_info("The %s device has been successfully initialized.", + dev->name); + + return EOK; + +err_rx_structure: + e1000_uninitialize_rx_structure(nic_data); +err_irq: + unregister_interrupt_handler(dev, DRIVER_DATA_DEV(dev)->irq); +err_tx_structure: + e1000_uninitialize_tx_structure(e1000_data); +err_pio: + // e1000_pio_disable(dev); + /* TODO: find out if the pio_disable is needed */ +err_destroy: + e1000_dev_cleanup(dev); + return rc; +}; + +/** Read 16-bit value from EEPROM of E1000 adapter + * Function uses EERD register. + * + * @param device The E1000 device + * @param eeprom_address 8-bit EEPROM address + * @return 16-bit value from EEPROM + */ +static uint16_t e1000_eeprom_read(e1000_t *e1000_data, uint8_t eeprom_address) +{ + + fibril_mutex_lock(&e1000_data->eeprom_lock); + + uint32_t eerd_done; + uint32_t eerd_address_offset; + + switch (e1000_data->device_id) { + case 0x107c: + case 0x1013: + case 0x1018: + case 0x1019: + case 0x101A: + case 0x1076: + case 0x1077: + case 0x1078: + case 0x10b9: + //82541xx and 82547GI/EI + //TODO add more device ids + eerd_done = + EERD_DONE_82541XX_82547GI_EI; + eerd_address_offset = + EERD_ADDRESS_OFFSET_82541XX_82547GI_EI; + break; + default: + eerd_done = EERD_DONE; + eerd_address_offset = EERD_ADDRESS_OFFSET; + break; + } + + //write address and START bit to EERD register + uint32_t write_data = + EERD_START | (((uint32_t)eeprom_address) << eerd_address_offset); + E1000_REG_WRITE(e1000_data, E1000_EERD, write_data); + + uint32_t eerd = E1000_REG_READ(e1000_data, E1000_EERD); + while ((eerd & eerd_done) == 0) { + usleep(1); + eerd = E1000_REG_READ(e1000_data, E1000_EERD); + } + + fibril_mutex_unlock(&e1000_data->eeprom_lock); + + return (uint16_t)(eerd >> EERD_DATA_OFFSET); +} + +/** Get MAC address of the E1000 adapter + * + * @param device The E10000 device + * @param address The place to store the address + * @param max_len Maximal addresss length to store + * @return EOK if succeed, negative error code otherwise + */ +static int e1000_get_address(e1000_t *e1000_data, nic_address_t *address) +{ + fibril_mutex_lock(&e1000_data->rx_lock); + + uint8_t *mac0_dest = (uint8_t *)address->address; + uint8_t *mac1_dest = (uint8_t *)address->address + 1; + uint8_t *mac2_dest = (uint8_t *)address->address + 2; + uint8_t *mac3_dest = (uint8_t *)address->address + 3; + uint8_t *mac4_dest = (uint8_t *)address->address + 4; + uint8_t *mac5_dest = (uint8_t *)address->address + 5; + + uint32_t rah = E1000_REG_READ(e1000_data, E1000_RAH_ARRAY(0)); + uint32_t ral = E1000_REG_READ(e1000_data, E1000_RAL_ARRAY(0)); + + *mac0_dest = (uint8_t) ral; + *mac1_dest = (uint8_t) (ral >> 8); + *mac2_dest = (uint8_t) (ral >> 16); + *mac3_dest = (uint8_t) (ral >> 24); + *mac4_dest = (uint8_t) rah; + *mac5_dest = (uint8_t) (rah >> 8); + + fibril_mutex_unlock(&e1000_data->rx_lock); + + return EOK; +}; + +/** Set card MAC address + * + * @param device The E1000 device + * @param address The place to store the address + * @param max_len Maximal addresss length to store + * @return EOK if succeed, negative error code otherwise + */ +static int e1000_set_addr(ddf_fun_t *dev, const nic_address_t *addr) +{ + nic_t *nic_data = NIC_DATA_DEV(dev); + e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data); + fibril_mutex_lock(&e1000_data->rx_lock); + fibril_mutex_lock(&e1000_data->tx_lock); + + int rc = nic_report_address(nic_data, addr); + if (rc == EOK) { + e1000_write_receive_address(e1000_data, 0, addr, false); + } + + fibril_mutex_unlock(&e1000_data->tx_lock); + fibril_mutex_unlock(&e1000_data->rx_lock); + + return rc; +} + +static void e1000_eeprom_get_address(e1000_t *e1000_data, + nic_address_t *address) +{ + uint16_t *mac0_dest = (uint16_t *)address->address; + uint16_t *mac2_dest = (uint16_t *)(address->address + 2); + uint16_t *mac4_dest = (uint16_t *)(address->address + 4); + + *mac0_dest = e1000_eeprom_read(e1000_data, 0); + *mac2_dest = e1000_eeprom_read(e1000_data, 1); + *mac4_dest = e1000_eeprom_read(e1000_data, 2); +} + +/** Send packet with the hardware + * + * @param nic_data The nic driver data structure + * @param packet The packet to send + * + * @return EOK if succeed, error code in the case of error + */ +static void e1000_write_packet(nic_t *nic_data, packet_t *packet) +{ + assert(nic_data); + + e1000_t *e1000_data = DRIVER_DATA_NIC(nic_data); + fibril_mutex_lock(&e1000_data->tx_lock); + + uint32_t tdt = E1000_REG_READ(e1000_data, E1000_TDT); + e1000_tx_descriptor_t * tx_descriptor_addr = (e1000_tx_descriptor_t *) + (e1000_data->tx_ring.virtual + tdt * sizeof(e1000_tx_descriptor_t)); + + bool descriptor_available = false; + //Descriptor never used + if (tx_descriptor_addr->length == 0) { + descriptor_available = true; + } + //Descriptor done + if (tx_descriptor_addr->status & TXDESCRIPTOR_STATUS_DD) { + descriptor_available = true; + packet_t * old_packet = *(e1000_data->tx_ring_packets + tdt); + if (old_packet) { + nic_dma_unlock_packet(old_packet); + nic_release_packet(nic_data, old_packet); + } + } + if (! descriptor_available) { + nlog_error("Packet %d lost no space in tx ring", packet->packet_id); + fibril_mutex_unlock(&e1000_data->tx_lock); + return; + } + + size_t packet_size = packet_get_data_length(packet); + + void * phys_addr; + phys_addr = nic_dma_lock_packet(packet); + if (!phys_addr) { + fibril_mutex_unlock(&e1000_data->tx_lock); + return; + } + + *(e1000_data->tx_ring_packets + tdt) = packet; + + tx_descriptor_addr->phys_addr = + PTR_TO_U64(phys_addr + packet->data_start); + tx_descriptor_addr->length = packet_size; + tx_descriptor_addr->command = + TXDESCRIPTOR_COMMAND_RS | // report status to STATUS.DD (descr. done) + TXDESCRIPTOR_COMMAND_IFCS | // add ethernet CRC + TXDESCRIPTOR_COMMAND_EOP; // end of packet + tx_descriptor_addr->checksum_offset = 0; + tx_descriptor_addr->status = 0; + if (e1000_data->vlan_tag_add) { + tx_descriptor_addr->special = e1000_data->vlan_tag; + tx_descriptor_addr->command |= TXDESCRIPTOR_COMMAND_VLE; + } else { + tx_descriptor_addr->special = 0; + } + tx_descriptor_addr->checksum_start_field = 0; + + ++tdt; + if (tdt == E1000_TX_PACKETS_COUNT ) { + tdt = 0; + } + + E1000_REG_WRITE(e1000_data, E1000_TDT, tdt); + + + fibril_mutex_unlock(&e1000_data->tx_lock); + +}; + +/** Initialize the driver + */ +static void e1000_driver_init() +{ + int rc = dma_allocator_init(); + if (rc != EOK) { + nlog_error("Unable to initialize DMA allocator"); + } +} + +/** Main function of E1000 driver + * + * Just initialize the driver structures and + * put it into the device drivers interface + */ +int main(void) +{ + int rc = nic_driver_init(NAME); + if (rc != EOK) { + return rc; + } + + nlog_set_min_severity(DEBUG); + nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops, &e1000_nic_iface); + + e1000_driver_init(); + nlog_info("HelenOS E1000 driver started"); + return ddf_driver_main(&e1000_driver); +} Index: uspace/drv/nic/e1k/e1k.h =================================================================== --- uspace/drv/nic/e1k/e1k.h (revision bf848717e8d508127f8be22655d603fdd89fe773) +++ uspace/drv/nic/e1k/e1k.h (revision bf848717e8d508127f8be22655d603fdd89fe773) @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2011 Zdenek Bouska + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @file e1000_defs.h + * + * Registers, bit positions and masks definition of the E1000 network family + * cards + */ + +#ifndef E1000_DEFS_H_INCLUDED_ +#define E1000_DEFS_H_INCLUDED_ + +/** Ethernet CRC size after packet received in rx_descriptor */ +#define E1000_CRC_SIZE 4 + +/** Receive descriptior */ +typedef struct e1000_rx_descriptor { + /** Buffer Address - physical */ + uint64_t phys_addr; + /** Length is per segment */ + uint16_t length; + /** Checksum - not all types, on some reseved */ + uint16_t checksum; + /** Status field */ + uint8_t status; + /** Errors field */ + uint8_t errors; + /** Special Field - not all types, on some reseved */ + uint16_t special; +} e1000_rx_descriptor_t; + +/** Legacy transmit descriptior */ +typedef struct e1000_tx_descriptor { + /** Buffer Address - physical */ + uint64_t phys_addr; + /** Length is per segment */ + uint16_t length; + /** Checksum Offset */ + uint8_t checksum_offset; + /** Command field */ + uint8_t command; + /** Status field, upper bits are reserved */ + uint8_t status; + /** Checksum Start Field */ + uint8_t checksum_start_field; + /** Special Field */ + uint16_t special; +} e1000_tx_descriptor_t; + +/** VLAN tag bits */ +enum e1000_vlantag { + VLANTAG_CFI = (1 << 12), /**< Canonical Form Indicator */ +}; + +/** transmit descriptor COMMAND field bits */ +enum e1000_txdescriptor_command { + TXDESCRIPTOR_COMMAND_VLE = (1 << 6), /**< VLAN Packet Enable */ + TXDESCRIPTOR_COMMAND_RS = (1 << 3), /**< Report Status */ + TXDESCRIPTOR_COMMAND_IFCS = (1 << 1), /**< Insert FCS */ + TXDESCRIPTOR_COMMAND_EOP = (1 << 0) /**< End Of Packet */ +}; + +/** transmit descriptor STATUS field bits */ +enum e1000_txdescriptor_status { + TXDESCRIPTOR_STATUS_DD = (1 << 0) /**< Descriptor Done */ +}; + +#define VET_VALUE 0x8100 + +/** e1000 Registers */ +enum e1000_registers { + E1000_CTRL = 0x0, /**< Device Control Register */ + E1000_STATUS = 0x8, /**< Device Status Register */ + E1000_EERD = 0x14, /**< EEPROM Read Register */ + E1000_TCTL = 0x400, /**< Transmit Control Register */ + E1000_TIPG = 0x410, /**< Transmit IPG Register */ + E1000_TDBAL = 0x3800, /**< Transmit Descriptor Base Address Low */ + E1000_TDBAH = 0x3804, /**< Transmit Descriptor Base Address High */ + E1000_TDLEN = 0x3808, /**< Transmit Descriptor Length */ + E1000_TDH = 0x3810, /**< Transmit Descriptor Head */ + E1000_TDT = 0x3818, /**< Transmit Descriptor Tail */ + E1000_RCTL = 0x100, /**< Receive Control Register */ + E1000_RDBAL = 0x2800, /**< Receive Descriptor Base Address Low */ + E1000_RDBAH = 0x2804, /**< Receive Descriptor Base Address High */ + E1000_RDLEN = 0x2808, /**< Receive Descriptor Length */ + E1000_RDH = 0x2810, /**< Receive Descriptor Head */ + E1000_RDT = 0x2818, /**< Receive Descriptor Tail */ + E1000_RAL = 0x5400, /**< Receive Address Low */ + E1000_RAH = 0x5404, /**< Receive Address High */ + E1000_VFTA = 0x5600, /**< VLAN Filter Table Array */ + E1000_VET = 0x38, /**< VLAN Ether Type */ + E1000_FCAL = 0x28, /**< Flow Control Address Low */ + E1000_FCAH = 0x2C, /**< Flow Control Address High */ + E1000_FCTTV = 0x170, /**< Flow Control Transmit Timer Value */ + E1000_FCT = 0x30, /**< Flow Control Type */ + E1000_ICR = 0xC0, /**< Interrupt Cause Read Register */ + E1000_ITR = 0xC4, /**< Interrupt Throttling Register */ + E1000_IMS = 0xD0, /**< Interrupt Mask Set/Read Register */ + E1000_IMC = 0xD8 /**< Interrupt Mask Clear Register */ +}; +#define E1000_RAL_ARRAY(n) (E1000_RAL + ((n) * 8)) +#define E1000_RAH_ARRAY(n) (E1000_RAH + ((n) * 8)) +#define E1000_VFTA_ARRAY(n) (E1000_VFTA + (0x4 * (n))) + +/** EEPROM Read Register fields */ +enum e1000_eerd { + EERD_START = (1 << 0), /**< Start Read */ + EERD_DONE = (1 << 4), /**< Read Done */ + EERD_DONE_82541XX_82547GI_EI = (1 << 1), /**< Read Done for + * 82541xx and 82547GI/EI + */ + EERD_ADDRESS_OFFSET = 8, /**< Read Address offset */ + EERD_ADDRESS_OFFSET_82541XX_82547GI_EI = 2, /**< Read Address offset + * 82541xx and 82547GI/EI + */ + EERD_DATA_OFFSET = 16 /**< Read Data */ +}; + +/** Device Control Register fields */ +enum e1000_ctrl { + CTRL_FD = (1 << 0), /**< Full-Duplex */ + CTRL_LRST = (1 << 3), /**< Link Reset */ + CTRL_ASDE = (1 << 5), /*< Auto-Speed Detection Enable */ + CTRL_SLU = (1 << 6), /**< Set Link Up */ + CTRL_ILOS = (1 << 7), /**< Invert Loss-of-Signal */ + + CTRL_SPEED_SHIFT = 8, /**< Speed selection shift */ + CTRL_SPEED_SIZE = 2, /**< Speed selection size */ + CTRL_SPEED_ALL = ((1 << CTRL_SPEED_SIZE) - 1), /**< Speed selection all + * bit set value + */ + CTRL_SPEED_MASK = CTRL_SPEED_ALL << CTRL_SPEED_SHIFT, /**< Speed selection + * shift + */ + CTRL_SPEED_10 = 0, /**< Speed selection 10 Mb/s value */ + CTRL_SPEED_100 = 1, /**< Speed selection 10 Mb/s value */ + CTRL_SPEED_1000 = 2, /**< Speed selection 10 Mb/s value */ + + CTRL_FRCSPD = (1 << 11), /**< Force Speed */ + CTRL_FRCDPLX = (1 << 12), /**< Force Duplex */ + CTRL_RST = (1 << 26), /**< Device Reset */ + CTRL_VME = (1 << 30), /**< VLAN Mode Enable */ + CTRL_PHY_RST = (1 << 31) /**< PHY Reset */ +}; + +/** Device Status Register fields */ +enum e1000_status { + STATUS_FD = (1 << 0), /**< Link Full Duplex configuration Indication */ + STATUS_LU = (1 << 1), /**< Link Up Indication */ + + STATUS_SPEED_SHIFT = 6, /**< Link speed setting shift */ + STATUS_SPEED_SIZE = 2, /**< Link speed setting size */ + STATUS_SPEED_ALL = ((1 << STATUS_SPEED_SIZE) - 1), /**< Link speed setting + * all bits set + */ + STATUS_SPEED_10 = 0, /**< Link speed setting 10 Mb/s value */ + STATUS_SPEED_100 = 1, /**< Link speed setting 100 Mb/s value */ + STATUS_SPEED_1000A = 2, /**< Link speed setting 1000 Mb/s value variant A */ + STATUS_SPEED_1000B = 3, /**< Link speed setting 1000 Mb/s value variant B */ +}; + +/** Transmit IPG Register fields + * IPG = Inter Packet Gap + */ +enum e1000_tipg { + TIPG_IPGT_SHIFT = 0, /**< IPG Transmit Time shift */ + TIPG_IPGR1_SHIFT = 10, /**< IPG Receive Time 1 */ + TIPG_IPGR2_SHIFT = 20 /**< IPG Receive Time 2 */ +}; + +/** Transmit Control Register fields */ +enum e1000_tctl { + TCTL_EN = (1 << 1), /**< Transmit Enable */ + TCTL_PSP = (1 << 3), /**< Pad Short Packets */ + TCTL_CT_SHIFT = 4, /**< Collision Threshold shift */ + TCTL_COLD_SHIFT = 12 /**< Collision Distance shift */ +}; + +/** ICR register fields */ +enum e1000_icr { + ICR_TXDW = (1 << 0), /**< Transmit Descriptor Written Back */ + ICR_RXT0 = (1 << 7) /**< Receiver Timer Interrupt */ +}; + +/** RAH register fields */ +enum e1000_rah { + RAH_AV = (1 << 31) /**< Address Valid */ +}; + +/** RCTL register fields */ +enum e1000_rctl { + RCTL_EN = (1 << 1), /**< Receiver Enable */ + RCTL_SBP = (1 << 2), /**< Store Bad Packets */ + RCTL_UPE = (1 << 3), /**< Unicast Promiscuous Enabled */ + RCTL_MPE = (1 << 4), /**< Multicast Promiscuous Enabled */ + RCTL_BAM = (1 << 15), /**< Broadcast Accept Mode */ + RCTL_VFE = (1 << 18) /**< VLAN Filter Enable */ +}; + +#endif Index: uspace/drv/nic/e1k/e1k.ma =================================================================== --- uspace/drv/nic/e1k/e1k.ma (revision bf848717e8d508127f8be22655d603fdd89fe773) +++ uspace/drv/nic/e1k/e1k.ma (revision bf848717e8d508127f8be22655d603fdd89fe773) @@ -0,0 +1,26 @@ +10 pci/ven=8086&dev=100e +10 pci/ven=8086&dev=100f +10 pci/ven=8086&dev=1010 +10 pci/ven=8086&dev=1011 +10 pci/ven=8086&dev=1012 +10 pci/ven=8086&dev=1013 +10 pci/ven=8086&dev=1015 +10 pci/ven=8086&dev=1016 +10 pci/ven=8086&dev=1017 +10 pci/ven=8086&dev=1018 +10 pci/ven=8086&dev=1019 +10 pci/ven=8086&dev=101a +10 pci/ven=8086&dev=101d +10 pci/ven=8086&dev=1026 +10 pci/ven=8086&dev=1027 +10 pci/ven=8086&dev=1028 +10 pci/ven=8086&dev=1076 +10 pci/ven=8086&dev=1077 +10 pci/ven=8086&dev=1078 +10 pci/ven=8086&dev=1079 +10 pci/ven=8086&dev=107a +10 pci/ven=8086&dev=107b +10 pci/ven=8086&dev=107c +10 pci/ven=8086&dev=1107 +10 pci/ven=8086&dev=1112 +10 pci/ven=8086&dev=10b9 Index: uspace/drv/nic/rtl8139/Makefile =================================================================== --- uspace/drv/nic/rtl8139/Makefile (revision bf848717e8d508127f8be22655d603fdd89fe773) +++ uspace/drv/nic/rtl8139/Makefile (revision bf848717e8d508127f8be22655d603fdd89fe773) @@ -0,0 +1,39 @@ +# +# Copyright (c) 2011 Radim Vansa +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +USPACE_PREFIX = ../../.. +LIBS = $(LIBDRV_PREFIX)/libdrv.a $(LIBNET_PREFIX)/libnet.a $(LIBNIC_PREFIX)/libnic.a +EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include -I$(LIBNET_PREFIX)/include -I$(LIBNIC_PREFIX)/include +BINARY = rtl8139 + +SOURCES = \ + driver.c \ + general.c \ + defs.c + +include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/nic/rtl8139/defs.c =================================================================== --- uspace/drv/nic/rtl8139/defs.c (revision bf848717e8d508127f8be22655d603fdd89fe773) +++ uspace/drv/nic/rtl8139/defs.c (revision bf848717e8d508127f8be22655d603fdd89fe773) @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2011 Jiri Michalec + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "rtl8139_defs.h" + +const char* model_names[RTL8139_VER_COUNT] = { + "RTL8139", + "RTL8139A", + "RTL8139A_G", + "RTL8139B", + "RTL8130", + "RTL8139C", + "RTL8100", + "RTL8139C+", + "RTL8139D", + "RTL8101" +}; + +#define HWVER(b1, b2, b3, b4, b5, b6, b7) ((b1 << 6) | (b2 << 5) | (b3 << 4) \ + | (b4 << 3) | (b5 << 2) | (b6 << 1) | (b7)) + +const struct rtl8139_hwver_map rtl8139_versions[RTL8139_VER_COUNT + 1] = { + { HWVER(1,1,0,0,0,0,0), RTL8139 }, + { HWVER(1,1,1,0,0,0,0), RTL8139A }, + { HWVER(1,1,1,0,0,1,0), RTL8139A_G }, + { HWVER(1,1,1,1,0,0,0), RTL8139B }, + { HWVER(1,1,1,1,1,0,0), RTL8130 }, + { HWVER(1,1,1,0,1,0,0), RTL8139C }, + { HWVER(1,1,1,1,0,1,0), RTL8100 }, + { HWVER(1,1,1,0,1,0,1), RTL8139D }, + { HWVER(1,1,1,0,1,1,0), RTL8139Cp }, + { HWVER(1,1,1,0,1,1,1), RTL8101 }, + /* End value */ + { 0, RTL8139_VER_COUNT} +}; + Index: uspace/drv/nic/rtl8139/defs.h =================================================================== --- uspace/drv/nic/rtl8139/defs.h (revision bf848717e8d508127f8be22655d603fdd89fe773) +++ uspace/drv/nic/rtl8139/defs.h (revision bf848717e8d508127f8be22655d603fdd89fe773) @@ -0,0 +1,509 @@ +/* + * Copyright (c) 2011 Jiri Michalec + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @file rtl8139_defs.h + * + * Registers, bit positions and masks definition of the RTL8139 network family + * cards + */ + +#ifndef RTL8139_DEFS_H_INCLUDED_ +#define RTL8139_DEFS_H_INCLUDED_ +#include +#include + + +/** The size of RTL8139 registers address space */ +#define RTL8139_IO_SIZE 256 + +/** The maximal transmitted packet length in bytes allowed according to RTL8139 + * documentation (see SIZE part of TSD documentation) + */ +#define RTL8139_PACKET_MAX_LENGTH 1792 + + +/** HW version + * + * as can be detected from HWVERID part of TCR + * (Transmit Configuration Register) + */ +enum rtl8139_version_id { + RTL8139 = 0, /**< RTL8139 */ + RTL8139A, /**< RTL8139A */ + RTL8139A_G, /**< RTL8139A-G */ + RTL8139B, /**< RTL8139B */ + RTL8130, /**< RTL8130 */ + RTL8139C, /**< RTL8139C */ + RTL8100, /**< RTL8100 */ + RTL8139Cp, /**< RTL8139C+ */ + RTL8139D, /**< RTL8139D */ + RTL8100B = RTL8139D, /**< RTL8100B and RTL8139D, the same HWVERID in TCR */ + RTL8101, /**< RTL8101 */ + RTL8139_VER_COUNT /**< Count of known RTL versions, the last value */ +}; + +extern const char* model_names[RTL8139_VER_COUNT]; + +/** Registers of RTL8139 family card offsets from the memory address base */ +enum rtl8139_registers { + IDR0 = 0x00, /**< First MAC address bit, 6 1b registres sequence */ + MAC0 = IDR0, /**< Alias for IDR0 */ + + // 0x6 - 0x7 reserved + + MAR0 = 0x08, /**< Multicast mask registers 8 1b registers sequence */ + + TSD0 = 0x10, /**< Transmit status of descriptor 0 */ + TSD1 = 0x14, /**< Transmit status of descriptor 1 */ + TSD2 = 0x18, /**< Transmit status of descriptor 2 */ + TSD3 = 0x1C, /**< Transmit status of descriptor 3 */ + + TSAD0 = 0x20, /**< Physical address of the 1st transmitter buffer, 4b */ + TSAD1 = 0x24, /**< Physical address of the 2nd transmitter buffer, 4b */ + TSAD2 = 0x28, /**< Physical address of the 3rd transmitter buffer, 4b */ + TSAD3 = 0x3C, /**< Physical address of the 4th transmitter buffer, 4b */ + + RBSTART = 0x30, /**< Receive (Rx) buffer start address, 4b */ + ERBCR = 0x34, /**< Early receive (Rx) byte count register, 2b */ + ERSR = 0x36, /**< Early receive (Rx) status register, 1b */ + + CR = 0x37, /**< Command register, 1b */ + CAPR = 0x38, /**< Current address of packet read, 2b */ + CBA = 0x3a, /**< Current buffer address, 2b */ + + IMR = 0x3c, /**< Interrupt mask register, 2b */ + ISR = 0x3e, /**< Interrupt status register, 2b */ + + TCR = 0x40, /**< Transmit (Tx) configuration register, 4b */ + RCR = 0x44, /**< Receive (Rx) configuration register, 4b */ + + TCTR = 0x48, /**< Timer count register */ + MPC = 0x4c, /**< Missed packet count */ + + CR9346 = 0x50, /**< 93C46 command register (locking of registers) */ + + CONFIG0 = 0x51, /**< Configuration register 0, 1b */ + CONFIG1 = 0x52, /**< Configuration register 1, 1b */ + + // 0x53 reserved + + TIMERINT = 0x54, /**< Timer interrupt register, 4b */ + MSR = 0x58, /**< Media status register, 1b */ + + CONFIG3 = 0x59, /**< Configuration register 3, 1b */ + CONFIG4 = 0x5a, /**< Configuration register 4, 1b */ + + // 0x5b reserved + + MULINT = 0x5c, /**< Multiple interrupt select, 2b */ + RERID = 0x5e, /**< PCI revision ID = 0x10, 1b */ + + // 0x5f reserved + + TSALLD = 0x60, /**< Transmit status of all descriptors, 2b */ + + BMCR = 0x62, /**< Basic mode control register */ + BMSR = 0x64, /**< Basic mode status register */ + + ANAR = 0x66, /**< Auto-negotiation advertisement register */ + ANLPAR = 0x68, /**< Auto-negotiation link partner register */ + ANER = 0x6a, /**< Auto-negotiation expansion register */ + DIS = 0x6c, /**< Disconnect counter */ + FCSC = 0x6e, /**< False carrier sense counter */ + NWAYTR = 0x70, /**< n-way test register */ + REC = 0x72, /**< RX_ER counter */ + CSCR = 0x74, /**< CS configuration register */ + + // 0x76 - 0x77 reserved + + PHY1_PARM = 0x78, /**< PHY parameter 1 */ + TW_PARM = 0x7c, /**< Twister parameter */ + PHY2_PARM = 0x80, /**< PHY parameter 2 */ + + // 0x81 reserved + + TDOKLA = 0x82, /**< Low Address of a Tx Descriptor with Tx DMA Ok */ + CRC0 = 0x84, /**< Power Management CRC register0 for wakeup frame 0 */ + WAKEUP0 = 0x8c, /**< Power Management wakeup frame 0 */ + LSBCRC0 = 0xcc, /**< Least significant masked byte of WF0 */ + FLASH = 0xd4, /**< Flash memory read/write register */ + + CONFIG5 = 0xd8, /**< Configuration register 5 */ + + TPPOL = 0xd9, /**< Transmit priority polling register */ + + // 0xda - 0xdf reserved + + CPCR = 0xe0, /**< C+ mode command register */ + + // 0xe2 - 0xe3 reserved + + RDSAR = 0xe4, /**< Receive Descriptor Start Address Register */ + ETTHR = 0xec, /**< Early transmit threshold register */ + + // 0xed - 0xef reserved + + FER = 0xf0, /**< Function event register */ + FEMR = 0xf4, /**< Function event mask register */ + FPSR = 0xf8, /**< Function present state register */ + FFER = 0xfc, /**< Function force event register */ + MIIR = 0xfc /**< MII register */ +}; + +/** Mask of valid bits in MPC value */ +#define MPC_VMASK UINT32_C(0xFFFFFF); + +/** Command register bits */ +enum rtl8139_cr { + CR_BUFE = (1 << 0), /**< Buffer empty bit - read only */ + CR_TE = (1 << 2), /**< Transmitter enable bit */ + CR_RE = (1 << 3), /**< Receiver enable bit */ + CR_RST = (1 << 4) /**< Reset - set to 1 to force software reset */ +}; + +/** Config1 register bits */ +enum rtl8139_config1 { + CONFIG1_LEDS_SHIFT = 6, /**< Shift of CONFIG1_LEDS bits */ + CONFIG1_LEDS_SIZE = 2, /**< Size of CONFIG1_LEDS bits */ + + CONFIG1_DVRLOAD = (1 << 5), /**< Driver load */ + CONFIG1_LWACT = (1 << 4), /**< LWAKE active mode */ + CONFIG1_MEMMAP = (1 << 3), /**< Memory mapping */ + CONFIG1_IOMAP = (1 << 2), /**< I/O space mapping */ + CONFIG1_VPD = (1 << 1), /**< Set to enable Vital Product Data */ + CONFIG1_PMEn = (1 << 0) /**< Power management enabled */ +}; + +/** Mask of 9346CR register for lock configuration registers */ +#define RTL8139_REGS_LOCKED 0 +/** Mask of 9346CR register for unlock configuration registers */ +#define RTL8139_REGS_UNLOCKED 0xC0 + +/** Put rtl8139 to normal mode. + * + * Writing to Config0-4 and part of BMCR registers is not allowed + */ +static inline void rtl8139_regs_lock(void *io_base) +{ + pio_write_8(io_base + CR9346, RTL8139_REGS_LOCKED); +} +/** Allow to change Config0-4 and BMCR register */ +static inline void rtl8139_regs_unlock(void *io_base) +{ + pio_write_8((io_base) + CR9346, RTL8139_REGS_UNLOCKED); +} + +/** Force soft reset of the chip. After it: + * receiver and transmitter are disabled + * transmitter FIFO is cleared + * transmitter buffer is set to TSDA0 + * receiver buffer is empty + * + * The reset bit in command register must be set to 1, the value of the + * the register is 1 during reset operation + * + * @param base_port The base address of the port mappings + */ +#define rtl8139_hw_reset(base_port)\ + {\ + pio_write_8(base_port + CR, CR_RST);\ + while((pio_read_8(base_port + CR) & CR_RST) != 0);\ + } + +/** Interrupt_masks + * + * The masks are the same for both IMR and ISR + */ +enum rtl8139_interrupts { + INT_SERR = (1 << 15), /**< System error interrupt */ + INT_TIME_OUT = (1 << 14), /**< Time out interrupt */ + INT_LENGTH_CHANGE = (1 << 13), /**< Cable length change interrupt */ + + /* bits 7 - 12 reserved */ + + INT_FIFOOVW = (1 << 6), /**< Receiver FIFO overflow interrupt */ + INT_PUN = (1 << 5), /**< Packet Underrun/Link Change Interrupt */ + INT_RXOVW = (1 << 4), /**< Receiver buffer overflow */ + INT_TER = (1 << 3), /**< Transmit error interrupt */ + INT_TOK = (1 << 2), /**< Transmit OK interrupt */ + INT_RER = (1 << 1), /**< Receive error interrupt */ + INT_ROK = (1 << 0) /**< Receive OK interrupt */ +}; + +/** Transmit status descriptor registers bits */ +enum rtl8139_tsd { + TSD_CRS = (1 << 31), /**< Carrier Sense Lost */ + TSD_TABT = (1 << 30), /**< Transmit Abort */ + TSD_OWC = (1 << 29), /**< Out of Window Collision */ + TSD_CDH = (1 << 28), /**< CD Heart Beat */ + TSD_NCC_SHIFT = 24, /**< Collision Count - bit shift */ + TSD_NCC_SIZE = 4, /**< Collision Count - bit size */ + TSD_NCC_MASK = (1 << 4)-1, /**< Collision Count - bit size */ + TSD_ERTXTH_SHIFT = 16, /**< Early Tx Threshold - bit shift */ + TSD_ERTXTH_SIZE = 6, /**< Early Tx Treshold - bit size */ + TSD_TOK = (1 << 15), /**< Transmit OK */ + TSD_TUN = (1 << 14), /**< Transmit FIFO Underrun */ + TSD_OWN = (1 << 13), /**< OWN */ + TSD_SIZE_SHIFT = 0, /**< Size - bit shift */ + TSD_SIZE_SIZE = 13, /**< Size - bit size */ + TSD_SIZE_MASK = 0x1fff /**< Size - bit mask */ +}; + +/** Receiver control register values */ +enum rtl8139_rcr { + RCR_ERTH_SHIFT = 24, /**< Early Rx treshold part shift */ + RCR_ERTH_SIZE = 4, /**< Early Rx treshold part size */ + + RCR_MulERINT = 1 << 17, /**< Multiple early interrupt select */ + + /** Minimal error packet length (1 = 8B, 0 = 64B). If AER/AR is set, RER8 + * is "Don't care" + */ + RCR_RER8 = 1 << 16, + + RCR_RXFTH_SHIFT = 13, /**< Rx FIFO treshold part shitf */ + RCR_RXFTH_SIZE = 3, /**< Rx FIFO treshold part size */ + + RCR_RBLEN_SHIFT = 11, /**< Rx buffer length part shift */ + RCR_RBLEN_SIZE = 2, /**< Rx buffer length part size */ + + RCR_RBLEN_8k = 0x00 << RCR_RBLEN_SHIFT, /**< 8K + 16 byte rx buffer */ + RCR_RBLEN_16k = 0x01 << RCR_RBLEN_SHIFT, /**< 16K + 16 byte rx buffer */ + RCR_RBLEN_32k = 0x02 << RCR_RBLEN_SHIFT, /**< 32K + 16 byte rx buffer */ + RCR_RBLEN_64k = 0x03 << RCR_RBLEN_SHIFT, /**< 64K + 16 byte rx buffer */ + + RCR_MXDMA_SHIFT = 8, /**< Max DMA Burst Size part shift */ + RCR_MXDMA_SIZE = 3, /**< Max DMA Burst Size part size */ + + RCR_WRAP = 1 << 7, /**< Rx buffer wrapped */ + RCR_ACCEPT_ERROR = 1 << 5, /**< Accept error packet */ + RCR_ACCEPT_RUNT = 1 << 4, /**< Accept Runt (8-64 bytes) packets */ + RCR_ACCEPT_BROADCAST = 1 << 3, /**< Accept broadcast */ + RCR_ACCEPT_MULTICAST = 1 << 2, /**< Accept multicast */ + RCR_ACCEPT_PHYS_MATCH = 1 << 1, /**< Accept device MAC address match */ + RCR_ACCEPT_ALL_PHYS = 1 << 0, /**< Accept all packets with + * phys. desticnation + */ + RCR_ACCEPT_MASK = (1 << 6) - 1 /**< Mask of accept part */ +}; + + +/** CSCR register bits */ +enum rtl8139_cscr { + CS_Testfun = (1 << 15), + CS_LD = (1 << 9), /**< Low TPI link disable signal */ + CS_HEART_BEAT = (1 << 8), /**< Heart beat enable; 10Mbit mode only */ + CS_JABBER_ENABLE = (1 << 7), /**< Enable jabber function */ + CS_F_LINK100 = (1 << 6), + CS_F_CONNECT = (1 << 5), + CS_CON_STATUS = (1 << 3), /**< connection status: + * 1 = valid, 0 = disconnected + */ + CS_CON_STATUS_EN = (1 << 2), /**< LED1 pin connection status indication */ + CS_PASS_SCR = (1 << 0) /**< Bypass Scramble */ +}; + +/** MSR register bits */ +enum rtl8139_msr { + MSR_TXFCE = (1 << 7), /**< Transmitter flow control enable */ + MSR_RXFCE = (1 << 6), /**< Receiver flow control enable */ + + MSR_AUX_PRESENT = (1 << 4), /**< Aux. Power present Status */ + MSR_SPEED10 = (1 << 3), /**< 10MBit mode sign (1 = 10Mb, 0 = 100Mb) */ + MSR_LINKB = (1 << 2), /**< Link Bad (fail) */ + MSR_TXPF = (1 << 1), /**< Transmitter pause flag */ + MSR_RXPF = (1 << 0) /**< Receiver pause flag */ +}; + +/** BMCR register bits (basic mode control register) */ +enum rtl8139_bmcr { + BMCR_Reset = (1 << 15), /**< Software reset */ + BMCR_Spd_100 = (1 << 13), /**< 100 MBit mode set, 10 MBit otherwise */ + BMCR_AN_ENABLE = (1 << 12), /**< Autonegotion enable */ + + /* 10,11 reserved*/ + + BMCR_AN_RESTART = (1 << 9), /**< Restart autonegotion */ + BMCR_DUPLEX = (1 << 8) /**< Duplex mode: 1=full duplex */ + + /* 0-7 reserved */ +}; + +/** Auto-negotiation advertisement register */ +enum rtl8139_anar { + ANAR_NEXT_PAGE = (1 << 15), /**< Next page bit, 0 - primary capability + * 1 - protocol specific + */ + ANAR_ACK = (1 << 14), /**< Capability reception acknowledge */ + ANAR_REMOTE_FAULT = (1 << 13), /**< Remote fault detection capability */ + ANAR_PAUSE = (1 << 10), /**< Symetric pause packet capability */ + ANAR_100T4 = (1 << 9), /**< T4, not supported by the device */ + ANAR_100TX_FD = (1 << 8), /**< 100BASE_TX full duplex */ + ANAR_100TX_HD = (1 << 7), /**< 100BASE_TX half duplex */ + ANAR_10_FD = (1 << 6), /**< 10BASE_T full duplex */ + ANAR_10_HD = (1 << 5), /**< 10BASE_T half duplex */ + ANAR_SELECTOR = 0x1 /**< Selector, + * CSMA/CD (0x1) supported only + */ +}; + +/** Autonegotiation expansion register bits */ +enum rtl8139_aner { + ANER_MFL = (1 << 4), /**< Multiple link fault occured */ + ANER_LP_NP_ABLE = (1 << 3), /**< Link parent supports next page */ + ANER_NP_ABLE = (1 << 2), /**< Local node is able to send next pages */ + ANER_PAGE_RX = (1 << 1), /** New page received, cleared on LPAR read */ + ANER_LP_NW_ABLE = (1 << 0) /**< Link partner autonegotiation support */ +}; + +enum rtl8139_config5 { + CONFIG5_BROADCAST_WAKEUP = (1 << 6), /**< Broadcast wakeup frame enable */ + CONFIG5_MULTICAST_WAKEUP = (1 << 5), /**< Multicast wakeup frame enable */ + CONFIG5_UNICAST_WAKEUP = (1 << 4), /**< Unicast wakeup frame enable */ + + /** Descending/ascending grow of Rx/Tx FIFO (to test FIFO SRAM only) */ + CONFIG5_FIFO_ADDR_PTR = (1 << 3), + /** Powersave if cable is disconnected */ + CONFIG5_LINK_DOWN_POWERSAVE = (1 << 2), + + CONFIG5_LAN_WAKE = (1 << 1), /**< LANWake signal enabled */ + CONFIG5_PME_STATUS = (1 << 0) /**< PMEn change: 0 = SW, 1 = SW+PCI */ +}; + +enum rtl8139_config3 { + CONFIG3_GNT_SELECT = (1 << 7), /**< Gnt select */ + CONFIG3_PARM_EN = (1 << 6), /**< Parameter enabled (100MBit mode) */ + CONFIG3_MAGIC = (1 << 5), /**< WoL Magic packet enable */ + CONFIG3_LINK_UP = (1 << 4), /**< Wakeup if link is reestablished */ + CONFIG3_CLKRUN_EN = (1 << 2), /**< CLKRUN enabled */ /* TODO: check what does it mean */ + CONFIG3_FBTBEN = (1 << 0) /**< Fast back to back enabled */ +}; + +enum rtl8139_config4 { + CONFIG4_RxFIFOAutoClr = (1 << 7), /**< Automatic RxFIFO owerflow clear */ + CONFIG4_AnaOff = (1 << 6), /**< Analog poweroff */ + CONFIG4_LongWF = (1 << 5), /**< Long wakeup frame + * (2xCRC8 + 3xCRC16) + */ + CONFIG4_LWPME = (1 << 4), /**< LWAKE and PMEB assertion */ + CONFIG4_LWPTN = (1 << 2), /**< LWake pattern */ + CONFIG4_PBWakeup = (1 << 0) /**< Preboot wakeup */ +}; + +/** Maximal runt packet size + 1 */ +#define RTL8139_RUNT_MAX_SIZE 64 + +/** Bits in packet header */ +enum rtl8139_packet_header { + RSR_MAR = (1 << 15), /**< Multicast received */ + RSR_PAM = (1 << 14), /**< Physical address match */ + RSR_BAR = (1 << 13), /**< Broadcast match */ + + RSR_ISE = (1 << 5), /**< Invalid symbol error, 100BASE-TX only */ + RSR_RUNT = (1 << 4), /**< Runt packet (< RTL8139_RUNT_MAX_SIZE bytes) */ + + RSR_LONG = (1 << 3), /**< Long packet (size > 4k bytes) */ + RSR_CRC = (1 << 2), /**< CRC error */ + RSR_FAE = (1 << 1), /**< Frame alignment error */ + RSR_ROK = (1 << 0) /**< Good packet received */ +}; + +enum rtl8139_tcr_bits { + HWVERID_A_SHIFT = 26, /**< HW version id, part A shift */ + HWVERID_A_SIZE = 5, /**< HW version id, part A bit size */ + HWVERID_A_MASK = (1 << 5) - 1, /**< HW version id, part A mask */ + + IFG_SHIFT = 24, /**< The interframe gap time setting shift */ + IFG_SIZE = 2, /**< The interframe gap time setting bit size */ + + HWVERID_B_SHIFT = 22, /**< HW version id, part B shift */ + HWVERID_B_SIZE = 2, /**< HW version id, part B bit size */ + HWVERID_B_MASK = (1 << 2) - 1, /**< HW version id, part B mask */ + + LOOPBACK_SHIFT = 17, /**< Loopback mode shift */ + LOOPBACK_SIZE = 2, /**< Loopback mode size + * 00 = normal, 11 = loopback + */ + + APPEND_CRC = 1 << 16, /**< Append CRC at the end of a packet */ + + MXTxDMA_SHIFT = 8, /**< Max. DMA Burst per TxDMA shift, burst = 16^value */ + MXTxDMA_SIZE = 3, /**< Max. DMA Burst per TxDMA bit size */ + + TX_RETRY_COUNT_SHIFT = 4, /**< Retries before aborting shift */ + TX_RETRY_COUNT_SIZE = 4, /**< Retries before aborting size */ + + CLEAR_ABORT = 1 << 0 /**< Retransmit aborted packet at the last + * transmitted descriptor + */ +}; + +#define RTL8139_HWVERID_A(tcr) (((tcr) >> HWVERID_A_SHIFT) & HWVERID_A_MASK) +#define RTL8139_HWVERID_B(tcr) (((tcr) >> HWVERID_B_SHIFT) & HWVERID_B_MASK) +#define RTL8139_HWVERID(tcr) ((RTL8139_HWVERID_A(tcr) << HWVERID_B_SIZE) | \ + RTL8139_HWVERID_B(tcr)) + +/** Mapping of HW version -> version ID */ +struct rtl8139_hwver_map { + uint32_t hwverid; /**< HW version value in the register */ + enum rtl8139_version_id ver_id; /**< appropriate version id */ +}; + +/** Mapping of HW version -> version ID */ +extern const struct rtl8139_hwver_map rtl8139_versions[RTL8139_VER_COUNT + 1]; + +/** Size in the packet header while copying from RxFIFO to Rx buffer */ +#define RTL8139_EARLY_SIZE UINT16_C(0xfff0) +/** The only supported pause packet time value */ +#define RTL8139_PAUSE_VAL UINT16_C(0xFFFF) + +/** Size of the packet header in front of the received frame */ +#define RTL_PACKET_HEADER_SIZE 4 + +/** 8k buffer */ +#define RTL8139_RXFLAGS_SIZE_8 0 +/** 16k buffer */ +#define RTL8139_RXFLAGS_SIZE_16 1 +/** 32k buffer */ +#define RTL8139_RXFLAGS_SIZE_32 2 +/** 64k buffer */ +#define RTL8139_RXFLAGS_SIZE_64 3 + +/** Get the buffer initial size without 16B padding + * Size is (8 + 2^flags) kB (^ in mean power) + * + * @param flags The flags for Rx buffer size, 0-3 + */ +#define RTL8139_RXSIZE(flags) (1 << (13 + (flags))) + +/** Padding of the receiver buffer */ +#define RTL8139_RXBUF_PAD 16 +/** Size needed for buffer allocation */ +#define RTL8139_RXBUF_LENGTH(flags) (RTL8139_RXSIZE(flags) + RTL8139_RXBUF_PAD) + +#endif Index: uspace/drv/nic/rtl8139/driver.c =================================================================== --- uspace/drv/nic/rtl8139/driver.c (revision bf848717e8d508127f8be22655d603fdd89fe773) +++ uspace/drv/nic/rtl8139/driver.c (revision bf848717e8d508127f8be22655d603fdd89fe773) @@ -0,0 +1,2173 @@ +/* + * Copyright (c) 2011 Jiri Michalec + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include + +#include "rtl8139_defs.h" +#include "rtl8139_driver.h" +#include "rtl8139_general.h" + +/** Global mutex for work with shared irq structure */ +FIBRIL_MUTEX_INITIALIZE(irq_reg_lock); +/** Lock interrupt structure mutex */ +#define RTL8139_IRQ_STRUCT_LOCK() fibril_mutex_lock(&irq_reg_lock) +/** Unlock interrupt structure mutex */ +#define RTL8139_IRQ_STRUCT_UNLOCK() fibril_mutex_unlock(&irq_reg_lock) + +/** PCI clock frequency in kHz */ +#define RTL8139_PCI_FREQ_KHZ 33000 + +#define RTL8139_AUTONEG_CAPS (ETH_AUTONEG_10BASE_T_HALF \ + | ETH_AUTONEG_10BASE_T_FULL | ETH_AUTONEG_100BASE_TX_HALF \ + | ETH_AUTONEG_100BASE_TX_FULL | ETH_AUTONEG_PAUSE_SYMETRIC) + +/** Lock transmitter and receiver data + * This function shall be called whenever both transmitter and receiver locking + * to force safe lock ordering (deadlock prevention) + * + * @param rtl8139 RTL8139 private data + */ +inline static void rtl8139_lock_all(rtl8139_t *rtl8139) +{ + assert(rtl8139); + fibril_mutex_lock(&rtl8139->tx_lock); + fibril_mutex_lock(&rtl8139->rx_lock); +} + +/** Unlock transmitter and receiver data + * + * @param rtl8139 RTL8139 private data + */ +inline static void rtl8139_unlock_all(rtl8139_t *rtl8139) +{ + assert(rtl8139); + fibril_mutex_unlock(&rtl8139->rx_lock); + fibril_mutex_unlock(&rtl8139->tx_lock); +} + +#ifndef RXBUF_SIZE_FLAGS + /** Flags for receiver buffer - 16kB default */ + #define RXBUF_SIZE_FLAGS RTL8139_RXFLAGS_SIZE_16 +#endif + +#if (RXBUF_SIZE_FLAGS > RTL8139_RXFLAGS_SIZE_64) || (RXBUF_SIZE_FLAGS < 0) + #error Bad receiver buffer flags size flags +#endif + +/** Size of the receiver buffer + * + * Incrementing flags by one twices the buffer size + * the lowest size is 8*1024 (flags = 0) + */ +#define RxBUF_SIZE RTL8139_RXSIZE(RXBUF_SIZE_FLAGS) + +/** Total size of the receiver buffer to allocate */ +#define RxBUF_TOT_LENGTH RTL8139_RXBUF_LENGTH(RXBUF_SIZE_FLAGS) + + +/** Default interrupt mask */ +#define RTL_DEFAULT_INTERRUPTS UINT16_C(0xFFFF) + +/** Obtain the value of the register part + * The bit operations will be done + * The _SHIFT and _MASK for the register part must exists as macros + * or variables + */ +#define REG_GET_VAL(value, reg_part)\ + (((value) >> reg_part##_SHIFT) & reg_part##_MASK) + + +/** Disable interrupts on controller + * + * @param rtl8139 The card private structure + */ +inline static void rtl8139_hw_int_disable(rtl8139_t *rtl8139) +{ + pio_write_16(rtl8139->io_port + IMR, 0x0); +} +/** Enable interrupts on controller + * + * @param rtl8139 The card private structure + */ +inline static void rtl8139_hw_int_enable(rtl8139_t *rtl8139) +{ + pio_write_16(rtl8139->io_port + IMR, rtl8139->int_mask); +} + +/** Check on the controller if the receiving buffer is empty + * + * @param rtl8139 The controller data + * + * @return Nonzero if empty, zero otherwise + */ +inline static int rtl8139_hw_buffer_empty(rtl8139_t *rtl8139) +{ + return pio_read_16(rtl8139->io_port + CR) & CR_BUFE; +} + +/** Update the mask of accepted packets in the RCR register according to + * rcr_accept_mode value in rtl8139_t + * + * @param rtl8139 The rtl8139 private data + */ +static void rtl8139_hw_update_rcr(rtl8139_t *rtl8139) +{ + uint32_t rcr = rtl8139->rcr_data.rcr_base | rtl8139->rcr_data.ucast_mask + | rtl8139->rcr_data.mcast_mask | rtl8139->rcr_data.bcast_mask + | rtl8139->rcr_data.defect_mask | + (RXBUF_SIZE_FLAGS << RCR_RBLEN_SHIFT); + + nlog_debug("Rewriting rcr: %x -> %x", pio_read_32(rtl8139->io_port + RCR), + rcr); + + pio_write_32(rtl8139->io_port + RCR, rcr); +} + +/** Fill the mask of accepted multicast packets in the card registers + * + * @param rtl8139 The rtl8139 private data + * @param mask The mask to set + */ +inline static void rtl8139_hw_set_mcast_mask(rtl8139_t *rtl8139, + uint64_t mask) +{ + pio_write_32(rtl8139->io_port + MAR0, (uint32_t) mask); + pio_write_32(rtl8139->io_port + MAR0 + sizeof(uint32_t), + (uint32_t)(mask >> 32)); + return; +} + +#include + +/** Set PmEn (Power management enable) bit value + * + * @param rtl8139 rtl8139 card data + * @param bit_val If bit_val is zero pmen is set to 0, otherwise pmen is set to 1 + */ +inline static void rtl8139_hw_pmen_set(rtl8139_t *rtl8139, uint8_t bit_val) +{ + uint8_t config1 = pio_read_8(rtl8139->io_port + CONFIG1); + uint8_t config1_new; + if (bit_val) + config1_new = config1 | CONFIG1_PMEn; + else + config1_new = config1 & ~(uint8_t)(CONFIG1_PMEn); + + if (config1_new == config1) + return; + + rtl8139_regs_unlock(rtl8139->io_port); + pio_write_8(rtl8139->io_port + CONFIG1, config1_new); + rtl8139_regs_lock(rtl8139->io_port); + + if (bit_val) { + async_sess_t *pci_sess = + nic_get_ddf_dev(rtl8139->nic_data)->parent_sess; + uint8_t pmen; + pci_config_space_read_8(pci_sess, 0x55, &pmen); + pci_config_space_write_8(pci_sess, 0x55, pmen | 1 | (1 << 7)); + } else { + async_sess_t *pci_sess = + nic_get_ddf_dev(rtl8139->nic_data)->parent_sess; + uint8_t pmen; + pci_config_space_read_8(pci_sess, 0x55, &pmen); + pci_config_space_write_8(pci_sess, 0x55, pmen & ~(1 | (1 << 7))); + } +} + +/** Get MAC address of the RTL8139 adapter + * + * @param rtl8139 The RTL8139 device + * @param address The place to store the address + * + * @return EOK if succeed, negative error code otherwise + */ +inline static void rtl8139_hw_get_addr(rtl8139_t *rtl8139, + nic_address_t *addr) +{ + assert(rtl8139); + assert(addr); + + uint32_t *mac0_dest = (uint32_t *)addr->address; + uint16_t *mac4_dest = (uint16_t *)(addr->address + 4); + + /* Read MAC address from the i/o (4byte + 2byte reads) */ + *mac0_dest = pio_read_32(rtl8139->io_port + MAC0); + *mac4_dest = pio_read_16(rtl8139->io_port + MAC0 + 4); +}; + +/** Set MAC address to the device + * + * @param rtl8139 Controller private structure + * @param addr The address to set + */ +static void rtl8139_hw_set_addr(rtl8139_t *rtl8139, const nic_address_t *addr) +{ + assert(rtl8139); + assert(addr); + + const uint32_t *val1 = (const uint32_t*)addr->address; + const uint16_t *val2 = (const uint16_t*)(addr->address + sizeof(uint32_t)); + + rtl8139_regs_unlock(rtl8139->io_port); + pio_write_32(rtl8139->io_port + MAC0, *val1); + pio_write_32(rtl8139->io_port + MAC0 + 4, *val2); + rtl8139_regs_lock(rtl8139->io_port); +} + +/** Provide OR in the 8bit register (set selected bits to 1) + * + * @param rtl8139 The rtl8139 structure + * @param reg_offset Register offset in the device IO space + * @param bits_add The value to or + */ +inline static void rtl8139_hw_reg_add_8(rtl8139_t * rtl8139, size_t reg_offset, + uint8_t bits_add) +{ + uint8_t value = pio_read_8(rtl8139->io_port + reg_offset); + value |= bits_add; + pio_write_8(rtl8139->io_port + reg_offset, value); +} + +/** Provide OR in the 32bit register (set selected bits to 1) + * + * @param rtl8139 The rtl8139 structure + * @param reg_offset Register offset in the device IO space + * @param bits_add The value to or + */ +inline static void rtl8139_hw_reg_add_32(rtl8139_t * rtl8139, size_t reg_offset, + uint32_t bits_add) +{ + uint32_t value = pio_read_32(rtl8139->io_port + reg_offset); + value |= bits_add; + pio_write_32(rtl8139->io_port + reg_offset, value); +} + +/** Unset selected bits in 8bit register + * + * @param rtl8139 The rtl8139 structure + * @param reg_offset Register offset in the device IO space + * @param bits_add The mask of bits to remove + */ +inline static void rtl8139_hw_reg_rem_8(rtl8139_t * rtl8139, size_t reg_offset, + uint8_t bits_add) +{ + uint8_t value = pio_read_8(rtl8139->io_port + reg_offset); + value &= ~bits_add; + pio_write_8(rtl8139->io_port + reg_offset, value); +} + +/** Unset selected bits in 32bit register + * + * @param rtl8139 The rtl8139 structure + * @param reg_offset Register offset in the device IO space + * @param bits_add The mask of bits to remove + */ +inline static void rtl8139_hw_reg_rem_32(rtl8139_t * rtl8139, size_t reg_offset, + uint32_t bits_add) +{ + uint32_t value = pio_read_32(rtl8139->io_port + reg_offset); + value &= ~bits_add; + pio_write_32(rtl8139->io_port + reg_offset, value); +} + + +static int rtl8139_set_addr(ddf_fun_t *fun, const nic_address_t *); +static int rtl8139_get_device_info(ddf_fun_t *fun, nic_device_info_t *info); +static int rtl8139_get_cable_state(ddf_fun_t *fun, nic_cable_state_t *state); +static int rtl8139_get_operation_mode(ddf_fun_t *fun, int *speed, + nic_channel_mode_t *duplex, nic_role_t *role); +static int rtl8139_set_operation_mode(ddf_fun_t *fun, int speed, + nic_channel_mode_t duplex, nic_role_t); + +static int rtl8139_pause_get(ddf_fun_t*, nic_result_t*, nic_result_t*, + uint16_t *); +static int rtl8139_pause_set(ddf_fun_t*, int, int, uint16_t); + +static int rtl8139_autoneg_enable(ddf_fun_t *fun, uint32_t advertisement); +static int rtl8139_autoneg_disable(ddf_fun_t *fun); +static int rtl8139_autoneg_probe(ddf_fun_t *fun, uint32_t *our_advertisement, + uint32_t *their_advertisement, nic_result_t *result, + nic_result_t *their_result); +static int rtl8139_autoneg_restart(ddf_fun_t *fun); + +static int rtl8139_defective_get_mode(ddf_fun_t *fun, uint32_t *mode); +static int rtl8139_defective_set_mode(ddf_fun_t *fun, uint32_t mode); + +static int rtl8139_wol_virtue_add(nic_t *nic_data, + const nic_wol_virtue_t *virtue); +static void rtl8139_wol_virtue_rem(nic_t *nic_data, + const nic_wol_virtue_t *virtue); + +static int rtl8139_poll_mode_change(nic_t *nic_data, nic_poll_mode_t mode, + const struct timeval *period); +static void rtl8139_poll(nic_t *nic_data); + +/** Network interface options for RTL8139 card driver */ +static nic_iface_t rtl8139_nic_iface = { + .set_address = &rtl8139_set_addr, + .get_device_info = &rtl8139_get_device_info, + .get_cable_state = &rtl8139_get_cable_state, + .get_operation_mode = &rtl8139_get_operation_mode, + .set_operation_mode = &rtl8139_set_operation_mode, + + .get_pause = &rtl8139_pause_get, + .set_pause = &rtl8139_pause_set, + + .autoneg_enable = &rtl8139_autoneg_enable, + .autoneg_disable = &rtl8139_autoneg_disable, + .autoneg_probe = &rtl8139_autoneg_probe, + .autoneg_restart = &rtl8139_autoneg_restart, + + .defective_get_mode = &rtl8139_defective_get_mode, + .defective_set_mode = &rtl8139_defective_set_mode, +}; + +/** Basic device operations for RTL8139 driver */ +static ddf_dev_ops_t rtl8139_dev_ops; + +static int rtl8139_add_device(ddf_dev_t *dev); + +/** Basic driver operations for RTL8139 driver */ +static driver_ops_t rtl8139_driver_ops = { + .add_device = &rtl8139_add_device, +}; + +/** Driver structure for RTL8139 driver */ +static driver_t rtl8139_driver = { + .name = NAME, + .driver_ops = &rtl8139_driver_ops +}; + +/* The default implementation callbacks */ +static int rtl8139_on_activated(nic_t *nic_data); +static int rtl8139_on_stopped(nic_t *nic_data); +static void rtl8139_write_packet(nic_t *nic_data, packet_t *packet); + +/** Check if the transmit buffer is busy */ +#define rtl8139_tbuf_busy(tsd) ((pio_read_32(tsd) & TSD_OWN) == 0) + +/** Send packet with the hardware + * + * note: the main_lock is locked when framework calls this function + * + * @param nic_data The nic driver data structure + * @param packet The packet to send + * + * @return EOK if succeed, error code in the case of error + */ +static void rtl8139_write_packet(nic_t *nic_data, packet_t *packet) +{ + assert(nic_data); + + rtl8139_t *rtl8139 = nic_get_specific(nic_data); + assert(rtl8139); + nlog_debug("Sending packet"); + + /* Get the packet data and check if it can be send */ + size_t packet_length = packet_get_data_length(packet); + void *packet_data = packet_get_data(packet); + + assert(packet_data); + + if ((packet_length > RTL8139_PACKET_MAX_LENGTH) || !packet_data) { + nlog_error("Write packet length error: data %p, length %z", + packet_data, packet_length); + nic_report_send_error(rtl8139->nic_data, NIC_SEC_OTHER, 1); + goto err_size; + } + + assert((packet_length & TSD_SIZE_MASK) == packet_length); + + /* Lock transmitter structure for obtaining next buffer */ + fibril_mutex_lock(&rtl8139->tx_lock); + + /* Check if there is free buffer */ + if (rtl8139->tx_next - TX_BUFF_COUNT == rtl8139->tx_used) { + nic_set_tx_busy(nic_data, 1); + fibril_mutex_unlock(&rtl8139->tx_lock); + nic_report_send_error(nic_data, NIC_SEC_BUFFER_FULL, 1); + goto err_busy_no_inc; + } + + /* Get buffer id to use and set next buffer to use */ + size_t tx_curr = rtl8139->tx_next++ % TX_BUFF_COUNT; + + fibril_mutex_unlock(&rtl8139->tx_lock); + + /* Get address of the buffer descriptor and packet data */ + void *tsd = rtl8139->io_port + TSD0 + tx_curr * 4; + void *buf_addr = rtl8139->tx_buff[tx_curr]; + + /* Wait until the buffer is free */ + assert(!rtl8139_tbuf_busy(tsd)); + + /* Write packet data to the buffer, set the size to TSD and clear OWN bit */ + memcpy(buf_addr, packet_data, packet_length); + + /* Set size of the data to send */ + uint32_t tsd_value = pio_read_32(tsd); + tsd_value = rtl8139_tsd_set_size(tsd_value, packet_length); + pio_write_32(tsd, tsd_value); + + /* barrier for HW to really see the current buffer data */ + write_barrier(); + + tsd_value &= ~(uint32_t)TSD_OWN; + pio_write_32(tsd, tsd_value); + nic_release_packet(nic_data, packet); + return; + +err_busy_no_inc: +err_size: + nic_release_packet(nic_data, packet); + return; +}; + + +/** Reset the controller + * + * @param io_base The address of the i/o port mapping start + */ +inline static void rtl8139_hw_soft_reset(void *io_base) +{ + pio_write_8(io_base + CR, CR_RST); + memory_barrier(); + while(pio_read_8(io_base + CR) & CR_RST) { + usleep(1); + read_barrier(); + } +} + +/** Provide soft reset of the controller + * + * The caller must lock tx_lock and rx_lock before calling this function + * + */ +static void rtl8139_soft_reset(rtl8139_t *rtl8139) +{ + assert(rtl8139); + + rtl8139_hw_soft_reset(rtl8139->io_port); + nic_t *nic_data = rtl8139->nic_data; + + /* Write MAC address to the card */ + nic_address_t addr; + nic_query_address(nic_data, &addr); + rtl8139_hw_set_addr(rtl8139, &addr); + + /* Recover accept modes back */ + rtl8139_hw_set_mcast_mask(rtl8139, nic_query_mcast_hash(nic_data)); + rtl8139_hw_update_rcr(rtl8139); + + rtl8139->tx_used = 0; + rtl8139->tx_next = 0; + nic_set_tx_busy(rtl8139->nic_data, 0); +} + +/** Create packet structure from the buffer data + * + * @param nic_data NIC driver data + * @param rx_buffer The receiver buffer + * @param rx_size The buffer size + * @param packet_start The offset where packet data start + * @param packet_size The size of the packet data + * + * @return The packet list node (not connected) + */ +static nic_frame_t *rtl8139_read_packet(nic_t *nic_data, + void *rx_buffer, size_t rx_size, size_t packet_start, size_t packet_size) +{ + nic_frame_t *frame = nic_alloc_frame(nic_data, packet_size); + if (! frame) { + nlog_error("Can not allocate frame for received packet."); + return NULL; + } + + void *packet_data = packet_suffix(frame->packet, packet_size); + if (!packet_data) { + nlog_error("Can not get the packet suffix."); + nic_release_frame(nic_data, frame); + return NULL; + } + + void *ret = rtl8139_memcpy_wrapped(packet_data, rx_buffer, packet_start, + RxBUF_SIZE, packet_size); + if (ret == NULL) { + nic_release_frame(nic_data, frame); + return NULL; + } + return frame; +} + +/* Reset receiver + * + * Use in the case of receiver error (lost in the rx_buff) + * + * @param rtl8139 controller private data + */ +static void rtl8139_rx_reset(rtl8139_t *rtl8139) +{ + /* Disable receiver, update offset and enable receiver again */ + uint8_t cr = pio_read_8(rtl8139->io_port + CR); + rtl8139_regs_unlock(rtl8139); + + pio_write_8(rtl8139->io_port + CR, cr & ~(uint8_t)CR_RE); + + write_barrier(); + pio_write_32(rtl8139->io_port + CAPR, 0); + pio_write_32(rtl8139->io_port + RBSTART, + PTR2U32(rtl8139->rx_buff.physical)); + + write_barrier(); + + rtl8139_hw_update_rcr(rtl8139); + pio_write_8(rtl8139->io_port + CR, cr); + rtl8139_regs_lock(rtl8139); + + nic_report_receive_error(rtl8139->nic_data, NIC_REC_OTHER, 1); +} + +/** Receive all packets in queue + * + * @param nic_data The controller data + * @return The linked list of packet_list_t nodes, each containing one packet + */ +static nic_frame_list_t *rtl8139_packet_receive(nic_t *nic_data) +{ + rtl8139_t *rtl8139 = nic_get_specific(nic_data); + if (rtl8139_hw_buffer_empty(rtl8139)) + return NULL; + + nic_frame_list_t *frames = nic_alloc_frame_list(); + if (!frames) + nlog_error("Can not allocate frame list for received packets."); + + void *rx_buffer = rtl8139->rx_buff.virtual; + + /* where to start reading */ + uint16_t rx_offset = pio_read_16(rtl8139->io_port + CAPR) + 16; + /* unread bytes count */ + uint16_t bytes_received = pio_read_16(rtl8139->io_port + CBA); + uint16_t max_read; + uint16_t cur_read = 0; + + /* get values to the <0, buffer size) */ + bytes_received %= RxBUF_SIZE; + rx_offset %= RxBUF_SIZE; + + /* count how many bytes to read maximaly */ + if (bytes_received < rx_offset) + max_read = bytes_received + (RxBUF_SIZE - rx_offset); + else + max_read = bytes_received - rx_offset; + + memory_barrier(); + while (!rtl8139_hw_buffer_empty(rtl8139)) { + void *rx_ptr = rx_buffer + rx_offset % RxBUF_SIZE; + uint32_t packet_header = uint32_t_le2host( *((uint32_t*)rx_ptr) ); + uint16_t size = packet_header >> 16; + uint16_t packet_size = size - RTL8139_CRC_SIZE; + /* received packet flags in packet header */ + uint16_t rcs = (uint16_t) packet_header; + + if (size == RTL8139_EARLY_SIZE) { + /* The packet copying is still in progress, break receiving */ + nlog_debug("Early threshold reached, not completely coppied"); + break; + } + + /* Check if the header is valid, otherwise we are lost in the buffer */ + if (size == 0 || size > RTL8139_PACKET_MAX_LENGTH) { + nlog_error("Receiver error -> receiver reset (size: %4"PRIu16", " + "header 0x%4"PRIx16". Offset: %zu)", size, packet_header, + rx_offset); + goto rx_err; + } + if (size < RTL8139_RUNT_MAX_SIZE && !(rcs & RSR_RUNT)) { + nlog_error("Receiver error -> receiver reset (%"PRIx16")", size); + goto rx_err; + } + + cur_read += size + RTL_PACKET_HEADER_SIZE; + if (cur_read > max_read) + break; + + if (frames) { + nic_frame_t *frame = rtl8139_read_packet(nic_data, rx_buffer, + RxBUF_SIZE, rx_offset + RTL_PACKET_HEADER_SIZE, packet_size); + + if (frame) + nic_frame_list_append(frames, frame); + } + + /* Update offset */ + rx_offset = ALIGN_UP(rx_offset + size + RTL_PACKET_HEADER_SIZE, 4); + + /* Write lesser value to prevent overflow into unread packet + * (the recomendation from the RealTech rtl8139 programming guide) + */ + uint16_t capr_val = rx_offset - 16; + pio_write_16(rtl8139->io_port + CAPR, capr_val); + + /* Ensure no CR read optimalization during next empty buffer test */ + memory_barrier(); + } + return frames; +rx_err: + rtl8139_rx_reset(rtl8139); + return frames; +}; + + + +/** Commands to deal with interrupt + * + * Read ISR, check if tere is any interrupt pending. + * If so, reset it and accept the interrupt. + * The .addr of the first and third command must + * be filled to the ISR port address + */ +irq_cmd_t rtl8139_irq_commands[] = { + { + /* Get the interrupt status */ + .cmd = CMD_PIO_READ_16, + .addr = NULL, + .dstarg = 2 + }, + { + .cmd = CMD_PREDICATE, + .value = 3, + .srcarg = 2 + }, + { + /* Mark interrupts as solved */ + .cmd = CMD_PIO_WRITE_16, + .addr = NULL, + .value = 0xFFFF + }, + { + /* Disable interrupts until interrupt routine is finished */ + .cmd = CMD_PIO_WRITE_16, + .addr = NULL, + .value = 0x0000 + }, + { + .cmd = CMD_ACCEPT + } +}; + +/** Interrupt code definition */ +irq_code_t rtl8139_irq_code = { + .cmdcount = sizeof(rtl8139_irq_commands)/sizeof(irq_cmd_t), + .cmds = rtl8139_irq_commands +}; + +/** Deal with transmitter interrupt + * + * @param nic_data Nic driver data + */ +static void rtl8139_tx_interrupt(nic_t *nic_data) +{ + rtl8139_t *rtl8139 = nic_get_specific(nic_data); + + fibril_mutex_lock(&rtl8139->tx_lock); + + size_t tx_next = rtl8139->tx_next; + size_t tx_used = rtl8139->tx_used; + while (tx_used != tx_next) { + size_t desc_to_check = tx_used % TX_BUFF_COUNT; + void * tsd_to_check = rtl8139->io_port + TSD0 + + desc_to_check * sizeof(uint32_t); + uint32_t tsd_value = pio_read_32(tsd_to_check); + + /* If sending is still in the progress */ + if ((tsd_value & TSD_OWN) == 0) + break; + + tx_used++; + + /* If the packet was sent */ + if (tsd_value & TSD_TOK) { + size_t size = REG_GET_VAL(tsd_value, TSD_SIZE); + nic_report_send_ok(nic_data, 1, size); + } else if (tsd_value & TSD_CRS) { + nic_report_send_error(nic_data, NIC_SEC_CARRIER_LOST, 1); + } else if (tsd_value & TSD_OWC) { + nic_report_send_error(nic_data, NIC_SEC_WINDOW_ERROR, 1); + } else if (tsd_value & TSD_TABT) { + nic_report_send_error(nic_data, NIC_SEC_ABORTED, 1); + } else if (tsd_value & TSD_CDH) { + nic_report_send_error(nic_data, NIC_SEC_HEARTBEAT, 1); + } + + unsigned collisions = REG_GET_VAL(tsd_value, TSD_NCC); + if (collisions > 0) { + nic_report_collisions(nic_data, collisions); + } + + if (tsd_value & TSD_TUN) { + nic_report_send_error(nic_data, NIC_SEC_FIFO_OVERRUN, 1); + } + } + if (rtl8139->tx_used != tx_used) { + rtl8139->tx_used = tx_used; + nic_set_tx_busy(nic_data, 0); + } + fibril_mutex_unlock(&rtl8139->tx_lock); +} + +/** Receive all packets from the buffer + * + * @param rtl8139 driver private data + */ +static void rtl8139_receive_packets(nic_t *nic_data) +{ + assert(nic_data); + + rtl8139_t *rtl8139 = nic_get_specific(nic_data); + assert(rtl8139); + + fibril_mutex_lock(&rtl8139->rx_lock); + nic_frame_list_t *frames = rtl8139_packet_receive(nic_data); + fibril_mutex_unlock(&rtl8139->rx_lock); + + if (frames) + nic_received_frame_list(nic_data, frames); +} + + +/** Deal with poll interrupt + * + * @param nic_data Nic driver data + */ +static int rtl8139_poll_interrupt(nic_t *nic_data) +{ + assert(nic_data); + + rtl8139_t *rtl8139 = nic_get_specific(nic_data); + assert(rtl8139); + + uint32_t timer_val; + int receive = rtl8139_timer_act_step(&rtl8139->poll_timer, &timer_val); + + assert(timer_val); + pio_write_32(rtl8139->io_port + TIMERINT, timer_val); + pio_write_32(rtl8139->io_port + TCTR, 0x0); + nlog_debug("rtl8139 timer: %"PRIu32"\treceive: %d", timer_val, receive); + return receive; +} + + +/** Poll device according to isr status + * + * The isr value must be obtained and cleared by the caller. The reason + * of this function separate is to allow polling from both interrupt + * (which clears controller ISR before the handler runs) and the polling + * callbacks. + * + * @param nic_data Driver data + * @param isr Interrupt status register value + */ +static void rtl8139_interrupt_impl(nic_t *nic_data, uint16_t isr) +{ + assert(nic_data); + + nic_poll_mode_t poll_mode = nic_query_poll_mode(nic_data, 0); + + /* Process only when should in the polling mode */ + if (poll_mode == NIC_POLL_PERIODIC) { + int receive = 0; + if (isr & INT_TIME_OUT) { + receive = rtl8139_poll_interrupt(nic_data); + } + if (! receive) + return; + } + + /* Check transmittion interrupts first to allow transmit next packets + * sooner + */ + if (isr & (INT_TOK | INT_TER)) { + rtl8139_tx_interrupt(nic_data); + } + if (isr & INT_ROK) { + rtl8139_receive_packets(nic_data); + } + if (isr & (INT_RER | INT_RXOVW | INT_FIFOOVW)) { + if (isr & INT_RER) { + //TODO: is this only the general error, or any particular? + } + if (isr & (INT_FIFOOVW)) { + nic_report_receive_error(nic_data, NIC_REC_FIFO_OVERRUN, 1); + } else if (isr & (INT_RXOVW)) { + rtl8139_t *rtl8139 = nic_get_specific(nic_data); + assert(rtl8139); + + uint32_t miss = pio_read_32(rtl8139->io_port + MPC) & MPC_VMASK; + pio_write_32(rtl8139->io_port + MPC, 0); + nic_report_receive_error(nic_data, NIC_REC_BUFFER_OVERFLOW, miss); + } + } +} + +/** Handle device interrupt + * + * @param dev The rtl8139 device + * @param iid The IPC call id + * @param icall The IPC call structure + */ +static void rtl8139_interrupt_handler(ddf_dev_t *dev, ipc_callid_t iid, + ipc_call_t *icall) +{ + assert(dev); + assert(icall); + + uint16_t isr = (uint16_t) IPC_GET_ARG2(*icall); + nic_t *nic_data = nic_get_from_ddf_dev(dev); + rtl8139_t *rtl8139 = nic_get_specific(nic_data); + + rtl8139_interrupt_impl(nic_data, isr); + + /* Turn the interrupts on again */ + rtl8139_hw_int_enable(rtl8139); +}; + +/** Register interrupt handler for the card in the system + * + * Note: the global irq_reg_mutex is locked because of work with global + * structure. + * + * @param nic_data The driver data + * + * @return EOK if the handler was registered, negative error code otherwise + */ +inline static int rtl8139_register_int_handler(nic_t *nic_data) +{ + rtl8139_t *rtl8139 = nic_get_specific(nic_data); + + /* Lock the mutex in whole driver while working with global structure */ + RTL8139_IRQ_STRUCT_LOCK(); + + rtl8139_irq_code.cmds[0].addr = rtl8139->io_port + ISR; + rtl8139_irq_code.cmds[2].addr = rtl8139->io_port + ISR; + rtl8139_irq_code.cmds[3].addr = rtl8139->io_port + IMR; + int rc = register_interrupt_handler(nic_get_ddf_dev(nic_data), + rtl8139->irq, rtl8139_interrupt_handler, &rtl8139_irq_code); + + RTL8139_IRQ_STRUCT_UNLOCK(); + + return rc; +} + +/** Start the controller + * + * The caller must lock tx_lock and rx_lock before calling this function + * + * @param rtl8139 The card private data + */ +inline static void rtl8139_card_up(rtl8139_t *rtl8139) +{ + void *io_base = rtl8139->io_port; + size_t i; + + /* Wake up the device */ + pio_write_8(io_base + CONFIG1, 0x00); + /* Reset the device */ + rtl8139_soft_reset(rtl8139); + + /* Write transmittion buffer addresses */ + for(i = 0; i < TX_BUFF_COUNT; ++i) { + uint32_t addr = PTR2U32(rtl8139->tx_buff_mem.physical + i*TX_BUFF_SIZE); + pio_write_32(io_base + TSAD0 + 4*i, addr); + } + rtl8139->tx_next = 0; + rtl8139->tx_used = 0; + nic_set_tx_busy(rtl8139->nic_data, 0); + + pio_write_32(io_base + RBSTART, PTR2U32(rtl8139->rx_buff.physical)); + + /* Enable transmitter and receiver */ + uint8_t cr_value = pio_read_8(io_base + CR); + pio_write_8(io_base + CR, cr_value | CR_TE | CR_RE); + rtl8139_hw_update_rcr(rtl8139); +} + +/** Activate the device to receive and transmit packets + * + * @param nic_data The nic driver data + * + * @return EOK if activated successfully, error code otherwise + */ +static int rtl8139_on_activated(nic_t *nic_data) +{ + assert(nic_data); + nlog_info("Activating device"); + + rtl8139_t *rtl8139 = nic_get_specific(nic_data); + assert(rtl8139); + + rtl8139_lock_all(rtl8139); + rtl8139_card_up(rtl8139); + rtl8139_unlock_all(rtl8139); + + rtl8139->int_mask = RTL_DEFAULT_INTERRUPTS; + rtl8139_hw_int_enable(rtl8139); + nic_enable_interrupt(nic_data, rtl8139->irq); + + nlog_debug("Device activated, interrupt %d registered", rtl8139->irq); + return EOK; +} + +/** Callback for NIC_STATE_STOPPED change + * + * @param nic_data The nic driver data + * + * @return EOK if succeed, error code otherwise + */ +static int rtl8139_on_stopped(nic_t *nic_data) +{ + assert(nic_data); + + rtl8139_t *rtl8139 = nic_get_specific(nic_data); + assert(rtl8139); + + rtl8139->rcr_data.ucast_mask = RTL8139_RCR_UCAST_DEFAULT; + rtl8139->rcr_data.mcast_mask = RTL8139_RCR_MCAST_DEFAULT; + rtl8139->rcr_data.bcast_mask = RTL8139_RCR_BCAST_DEFAULT; + rtl8139->rcr_data.defect_mask = RTL8139_RCR_DEFECT_DEFAULT; + + /* Reset the card to the initial state (interrupts, Tx and Rx disabled) */ + rtl8139_lock_all(rtl8139); + rtl8139_soft_reset(rtl8139); + rtl8139_unlock_all(rtl8139); + return EOK; +} + + +static int rtl8139_unicast_set(nic_t *nic_data, nic_unicast_mode_t mode, + const nic_address_t *, size_t); +static int rtl8139_multicast_set(nic_t *nic_data, nic_multicast_mode_t mode, + const nic_address_t *addr, size_t addr_count); +static int rtl8139_broadcast_set(nic_t *nic_data, nic_broadcast_mode_t mode); + + +/** Create driver data structure + * + * @return Intialized device data structure or NULL + */ +static rtl8139_t *rtl8139_create_dev_data(ddf_dev_t *dev) +{ + assert(dev); + assert(!nic_get_from_ddf_dev(dev)); + + nic_t *nic_data = nic_create_and_bind(dev); + if (!nic_data) + return NULL; + + rtl8139_t *rtl8139 = malloc(sizeof(rtl8139_t)); + if (!rtl8139) { + nic_unbind_and_destroy(dev); + return NULL; + } + + bzero(rtl8139, sizeof(rtl8139_t)); + + rtl8139->nic_data = nic_data; + nic_set_specific(nic_data, rtl8139); + nic_set_write_packet_handler(nic_data, rtl8139_write_packet); + nic_set_state_change_handlers(nic_data, + rtl8139_on_activated, NULL, rtl8139_on_stopped); + nic_set_filtering_change_handlers(nic_data, + rtl8139_unicast_set, rtl8139_multicast_set, rtl8139_broadcast_set, + NULL, NULL); + nic_set_wol_virtue_change_handlers(nic_data, + rtl8139_wol_virtue_add, rtl8139_wol_virtue_rem); + nic_set_poll_handlers(nic_data, rtl8139_poll_mode_change, rtl8139_poll); + + + fibril_mutex_initialize(&rtl8139->rx_lock); + fibril_mutex_initialize(&rtl8139->tx_lock); + + nic_set_wol_max_caps(nic_data, NIC_WV_BROADCAST, 1); + nic_set_wol_max_caps(nic_data, NIC_WV_LINK_CHANGE, 1); + nic_set_wol_max_caps(nic_data, NIC_WV_MAGIC_PACKET, 1); + + return rtl8139; +} + +/** Clean up the rtl8139 device structure. + * + * @param dev The device structure. + */ +static void rtl8139_dev_cleanup(ddf_dev_t *dev) +{ + assert(dev); + + if (dev->driver_data) + nic_unbind_and_destroy(dev); + + if (dev->parent_sess != NULL) { + async_hangup(dev->parent_sess); + dev->parent_sess = NULL; + } +} + +/** Fill the irq and io_addr part of device data structure + * + * The hw_resources must be obtained before calling this function + * + * @param dev The device structure + * @param hw_resources Devices hardware resources + * + * @return EOK if succeed, negative error code otherwise + */ +static int rtl8139_fill_resource_info(ddf_dev_t *dev, const hw_res_list_parsed_t + *hw_resources) +{ + assert(dev); + assert(hw_resources); + + rtl8139_t *rtl8139 = nic_get_specific(nic_get_from_ddf_dev(dev)); + assert(rtl8139); + + if (hw_resources->irqs.count != 1) { + nlog_error("%s device: unexpected irq count", dev->name); + return EINVAL; + }; + if (hw_resources->io_ranges.count != 1) { + nlog_error("%s device: unexpected io ranges count", dev->name); + return EINVAL; + } + + rtl8139->irq = hw_resources->irqs.irqs[0]; + nlog_debug("%s device: irq 0x%x assigned", dev->name, rtl8139->irq); + + rtl8139->io_addr = IOADDR_TO_PTR(hw_resources->io_ranges.ranges[0].address); + if (hw_resources->io_ranges.ranges[0].size < RTL8139_IO_SIZE) { + nlog_error("i/o range assigned to the device " + "%s is too small.", dev->name); + return EINVAL; + } + nlog_debug("%s device: i/o addr %p assigned.", dev->name, rtl8139->io_addr); + + return EOK; +} + +/** Obtain information about hardware resources of the device + * + * The device must be connected to the parent + * + * @param dev The device structure + * + * @return EOK if succeed, negative error code otherwise + */ +static int rtl8139_get_resource_info(ddf_dev_t *dev) +{ + assert(dev); + + nic_t *nic_data = nic_get_from_ddf_dev(dev); + assert(nic_data); + + hw_res_list_parsed_t hw_res_parsed; + hw_res_list_parsed_init(&hw_res_parsed); + + /* Get hw resources form parent driver */ + int rc = nic_get_resources(nic_data, &hw_res_parsed); + if (rc != EOK) + return rc; + + /* Fill resources information to the device */ + int ret = rtl8139_fill_resource_info(dev, &hw_res_parsed); + hw_res_list_parsed_clean(&hw_res_parsed); + + return ret; +} + + +/** Allocate buffers using DMA framework + * + * The buffers structures in the device specific data is filled + * + * @param data The device specific structure to fill + * + * @return EOK in the case of success, error code otherwise + */ +static int rtl8139_buffers_create(rtl8139_t *rtl8139) +{ + assert(rtl8139); + size_t i = 0; + int rc; + + nlog_debug("Creating buffers"); + + rtl8139->tx_buff_mem.size = TX_PAGES; + rtl8139->tx_buff_mem.mapping_flags = AS_AREA_WRITE; + rc = dma_allocate_anonymous(&rtl8139->tx_buff_mem, DMA_32_BITS); + if (rc != EOK) { + nlog_error("Can not allocate transmitter buffers."); + goto err_tx_alloc; + } + + for(i = 0; i < TX_BUFF_COUNT; ++i) + rtl8139->tx_buff[i] = rtl8139->tx_buff_mem.virtual + i * TX_BUFF_SIZE; + + nlog_debug("The transmittion buffers allocated"); + + /* Use the first buffer for next transmittion */ + rtl8139->tx_next = 0; + rtl8139->tx_used = 0; + + /* Allocate buffer for receiver */ + size_t rx_pages = ALIGN_UP(RxBUF_TOT_LENGTH, PAGE_SIZE) / PAGE_SIZE; + nlog_debug("Allocating receiver buffer of the size %zd pages", rx_pages); + + rtl8139->rx_buff.size = rx_pages; + rtl8139->rx_buff.mapping_flags = AS_AREA_READ; + rc = dma_allocate_anonymous(&rtl8139->rx_buff, DMA_32_BITS); + if( rc != EOK ) { + nlog_error("Can not allocate receiver buffer."); + goto err_rx_alloc; + } + nlog_debug("The buffers created"); + + return EOK; + +err_rx_alloc: + dma_free(&rtl8139->tx_buff_mem); +err_tx_alloc: + return rc; +} + +/** Initialize the rtl8139 device structure + * + * @param dev The device information + * + * @return EOK if succeed, negative error code otherwise + */ +static int rtl8139_device_initialize(ddf_dev_t *dev) +{ + nlog_debug("rtl8139_dev_initialize %s", dev->name); + + int ret = EOK; + + nlog_debug("rtl8139: creating device data"); + + /* Allocate driver data for the device. */ + rtl8139_t *rtl8139 = rtl8139_create_dev_data(dev); + if (rtl8139 == NULL) { + nlog_error("Not enough memory for initializing %s.", dev->name); + return ENOMEM; + } + + nlog_debug("rtl8139: dev_data created"); + + /* Obtain and fill hardware resources info and connect to parent */ + ret = rtl8139_get_resource_info(dev); + if (ret != EOK) { + nlog_error("Can not obatin hw resources information"); + goto failed; + } + + nlog_debug("rtl8139: resource_info obtained"); + + /* Allocate DMA buffers */ + ret = rtl8139_buffers_create(rtl8139); + if (ret != EOK) + goto failed; + + /* Set default packet acceptance */ + rtl8139->rcr_data.ucast_mask = RTL8139_RCR_UCAST_DEFAULT; + rtl8139->rcr_data.mcast_mask = RTL8139_RCR_MCAST_DEFAULT; + rtl8139->rcr_data.bcast_mask = RTL8139_RCR_BCAST_DEFAULT; + rtl8139->rcr_data.defect_mask = RTL8139_RCR_DEFECT_DEFAULT; + /* Set receiver early treshold to 8/16 of packet length */ + rtl8139->rcr_data.rcr_base = (0x8 << RCR_ERTH_SHIFT); + + nlog_debug("The device is initialized"); + return ret; + +failed: + nlog_error("The device initialization failed"); + rtl8139_dev_cleanup(dev); + return ret; +} + +/** Enable the i/o ports of the device. + * + * @param dev The RTL8139 device. + * + * @return EOK if successed, negative error code otherwise + */ +static int rtl8139_pio_enable(ddf_dev_t *dev) +{ + nlog_debug(NAME ": rtl8139_pio_enable %s", dev->name); + + rtl8139_t *rtl8139 = nic_get_specific(nic_get_from_ddf_dev(dev)); + + /* Gain control over port's registers. */ + if (pio_enable(rtl8139->io_addr, RTL8139_IO_SIZE, &rtl8139->io_port)) { + nlog_error("Cannot gain the port %lx for device %s.", rtl8139->io_addr, + dev->name); + return EADDRNOTAVAIL; + } + + return EOK; +} + +/** Initialize the driver private data according to the + * device registers + * + * @param rtl8139 rtl8139 private data + */ +static void rtl8139_data_init(rtl8139_t *rtl8139) +{ + assert(rtl8139); + + /* Check the version id */ + uint32_t tcr = pio_read_32(rtl8139->io_port + TCR); + uint32_t hwverid = RTL8139_HWVERID(tcr); + size_t i = 0; + rtl8139->hw_version = RTL8139_VER_COUNT; + for (i = 0; i < RTL8139_VER_COUNT; ++i) { + if (rtl8139_versions[i].hwverid == 0) + break; + + if (rtl8139_versions[i].hwverid == hwverid) { + rtl8139->hw_version = rtl8139_versions[i].ver_id; + nlog_info("HW version found: index %zu, ver_id %d (%s)", i, + rtl8139_versions[i].ver_id, model_names[rtl8139->hw_version]); + } + } +} + +/** The add_device callback of RTL8139 callback + * + * Probe and initialize the newly added device. + * + * @param dev The RTL8139 device. + * + * @return EOK if added successfully, negative error code otherwise + */ +int rtl8139_add_device(ddf_dev_t *dev) +{ + assert(dev); + nlog_info("RTL8139_add_device %s (handle = %d)", dev->name, dev->handle); + + /* Init device structure for rtl8139 */ + int rc = rtl8139_device_initialize(dev); + if (rc != EOK) + return rc; + + /* Map I/O ports */ + rc = rtl8139_pio_enable(dev); + if (rc != EOK) + goto err_destroy; + + nic_t *nic_data = nic_get_from_ddf_dev(dev); + rtl8139_t *rtl8139 = nic_get_specific(nic_data); + + nic_address_t addr; + rtl8139_hw_get_addr(rtl8139, &addr); + rc = nic_report_address(nic_data, &addr); + if (rc != EOK) + goto err_pio; + + /* Initialize the driver private structure */ + rtl8139_data_init(rtl8139); + + /* Register interrupt handler */ + rc = rtl8139_register_int_handler(nic_data); + if (rc != EOK) + goto err_pio; + + rc = nic_connect_to_services(nic_data); + if (rc != EOK) { + nlog_error("Failed to connect to services", rc); + goto err_irq; + } + + rc = nic_register_as_ddf_fun(nic_data, &rtl8139_dev_ops); + if (rc != EOK) { + nlog_error("Failed to register as DDF function - error %d", rc); + goto err_irq; + } + + nlog_info("The %s device has been successfully initialized.", + dev->name); + + return EOK; + +err_irq: + unregister_interrupt_handler(dev, rtl8139->irq); +err_pio: + // rtl8139_pio_disable(dev); + /* TODO: find out if the pio_disable is needed */ +err_destroy: + rtl8139_dev_cleanup(dev); + return rc; +}; + +/** Set card MAC address + * + * @param device The RTL8139 device + * @param address The place to store the address + * @param max_len Maximal addresss length to store + * + * @return EOK if succeed, negative error code otherwise + */ +static int rtl8139_set_addr(ddf_fun_t *fun, const nic_address_t *addr) +{ + assert(fun); + assert(addr); + + nic_t *nic_data =nic_get_from_ddf_fun((fun)); + rtl8139_t *rtl8139 = nic_get_specific(nic_data); + assert(rtl8139); + + rtl8139_lock_all(rtl8139); + + int rc = nic_report_address(nic_data, addr); + if ( rc != EOK) { + rtl8139_unlock_all(rtl8139); + return rc; + } + + rtl8139_hw_set_addr(rtl8139, addr); + + rtl8139_unlock_all(rtl8139); + return EOK; +} + +/** Get the device information + * + * @param dev The NIC device + * @param info The information to fill + * + * @return EOK + */ +static int rtl8139_get_device_info(ddf_fun_t *fun, nic_device_info_t *info) +{ + assert(fun); + assert(info); + + nic_t *nic_data = nic_get_from_ddf_fun(fun); + assert(nic_data); + rtl8139_t *rtl8139 = nic_get_specific(nic_data); + assert(rtl8139); + + /* TODO: fill the information more completely */ + info->vendor_id = 0x10ec; + str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH, "Realtek"); + + if (rtl8139->hw_version < RTL8139_VER_COUNT) { + str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH, + model_names[rtl8139->hw_version]); + } else { + str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH, "RTL8139"); + } + + info->ethernet_support[ETH_10M] = ETH_10BASE_T; + info->ethernet_support[ETH_100M] = ETH_100BASE_TX; + + info->autoneg_support = RTL8139_AUTONEG_CAPS; + return EOK; +} + +/** Check the cable state + * + * @param[in] dev The device + * @param[out] state The state to fill + * + * @return EOK + */ +static int rtl8139_get_cable_state(ddf_fun_t *fun, nic_cable_state_t *state) +{ + assert(fun); + assert(state); + + rtl8139_t *rtl8139 = nic_get_specific(nic_get_from_ddf_fun(fun)); + assert(rtl8139); + + if (pio_read_16(rtl8139->io_port + CSCR) & CS_CON_STATUS) { + *state = NIC_CS_PLUGGED; + } else { + *state = NIC_CS_UNPLUGGED; + } + + return EOK; +} + +/** Get operation mode of the device + */ +static int rtl8139_get_operation_mode(ddf_fun_t *fun, int *speed, + nic_channel_mode_t *duplex, nic_role_t *role) +{ + assert(fun); + assert(speed); + assert(duplex); + assert(role); + + rtl8139_t *rtl8139 = nic_get_specific(nic_get_from_ddf_fun(fun)); + assert(rtl8139); + + uint16_t bmcr_val = pio_read_16(rtl8139->io_port + BMCR); + uint8_t msr_val = pio_read_8(rtl8139->io_port + MSR); + + if (bmcr_val & BMCR_DUPLEX) { + *duplex = NIC_CM_FULL_DUPLEX; + } else { + *duplex = NIC_CM_HALF_DUPLEX; + } + + if (msr_val & MSR_SPEED10) { + *speed = 10; + } else { + *speed = 100; + } + + *role = NIC_ROLE_UNKNOWN; + return EOK; +} + +/** Value validity */ +enum access_mode { + /** Value is invalid now */ + VALUE_INVALID = 0, + /** Read-only */ + VALUE_RO, + /** Read-write */ + VALUE_RW +}; + +/** Check if pause packet operations are valid in current situation + * + * @param rtl8139 RTL8139 private structure + * + * @return VALUE_INVALID if the value has no sense in current moment + * @return VALUE_RO if the state is read-only in current moment + * @return VALUE_RW if the state can be modified + */ +static int rtl8139_pause_is_valid(rtl8139_t *rtl8139) +{ + assert(rtl8139); + + uint16_t bmcr = pio_read_16(rtl8139->io_port + BMCR); + if ((bmcr & (BMCR_AN_ENABLE | BMCR_DUPLEX)) == 0) + return VALUE_INVALID; + + if (bmcr & BMCR_AN_ENABLE) { + uint16_t anar_lp = pio_read_16(rtl8139->io_port + ANLPAR); + if (anar_lp & ANAR_PAUSE) + return VALUE_RO; + } + + return VALUE_RW; +} + +/** Get current pause packet configuration + * + * Values are filled with NIC_RESULT_NOT_AVAILABLE if the value has no sense in + * the moment (half-duplex). + * + * @param[in] fun The DDF structure of the RTL8139 + * @param[out] we_send Sign if local constroller sends pause packets + * @param[out] we_receive Sign if local constroller receives pause packets + * @param[out] time Time filled in pause packets. 0xFFFF in rtl8139 + * + * @return EOK if succeed + */ +static int rtl8139_pause_get(ddf_fun_t *fun, nic_result_t *we_send, + nic_result_t *we_receive, uint16_t *time) +{ + assert(fun); + assert(we_send); + assert(we_receive); + + rtl8139_t *rtl8139 = nic_get_specific(nic_get_from_ddf_fun(fun)); + assert(rtl8139); + + if (rtl8139_pause_is_valid(rtl8139) == VALUE_INVALID) { + *we_send = NIC_RESULT_NOT_AVAILABLE; + *we_receive = NIC_RESULT_NOT_AVAILABLE; + *time = 0; + return EOK; + } + + uint8_t msr = pio_read_8(rtl8139->io_port + MSR); + + *we_send = (msr & MSR_TXFCE) ? NIC_RESULT_ENABLED : NIC_RESULT_DISABLED; + *we_receive = (msr & MSR_RXFCE) ? NIC_RESULT_ENABLED : NIC_RESULT_DISABLED; + *time = RTL8139_PAUSE_VAL; + + return EOK; +}; + +/** Set current pause packet configuration + * + * @param fun The DDF structure of the RTL8139 + * @param allow_send Sign if local constroller sends pause packets + * @param allow_receive Sign if local constroller receives pause packets + * @param time Time to use, ignored (not supported by device) + * + * @return EOK if succeed, INVAL if the pause packet has no sence + */ +static int rtl8139_pause_set(ddf_fun_t *fun, int allow_send, int allow_receive, + uint16_t time) +{ + assert(fun); + + rtl8139_t *rtl8139 = nic_get_specific(nic_get_from_ddf_fun(fun)); + assert(rtl8139); + + if (rtl8139_pause_is_valid(rtl8139) != VALUE_RW) + return EINVAL; + + uint8_t msr = pio_read_8(rtl8139->io_port + MSR); + msr &= ~(uint8_t)(MSR_TXFCE | MSR_RXFCE); + + if (allow_receive) + msr |= MSR_RXFCE; + if (allow_send) + msr |= MSR_TXFCE; + + pio_write_8(rtl8139->io_port + MSR, msr); + + if (allow_send && time > 0) { + nlog_warning("Time setting is not supported in set_pause method."); + } + return EOK; +}; + +/** Set operation mode of the device + * + */ +static int rtl8139_set_operation_mode(ddf_fun_t *fun, int speed, + nic_channel_mode_t duplex, nic_role_t role) +{ + assert(fun); + + rtl8139_t *rtl8139 = nic_get_specific(nic_get_from_ddf_fun(fun)); + assert(rtl8139); + + if (speed != 10 && speed != 100) + return EINVAL; + if (duplex != NIC_CM_HALF_DUPLEX && duplex != NIC_CM_FULL_DUPLEX) + return EINVAL; + + uint16_t bmcr_val = pio_read_16(rtl8139->io_port + BMCR); + + /* Set autonegotion disabled */ + bmcr_val &= ~(uint16_t)BMCR_AN_ENABLE; + + if (duplex == NIC_CM_FULL_DUPLEX) { + bmcr_val |= BMCR_DUPLEX; + } else { + bmcr_val &= ~((uint16_t)BMCR_DUPLEX); + } + + if (speed == 100) { + bmcr_val |= BMCR_Spd_100; + } else { + bmcr_val &= ~((uint16_t)BMCR_Spd_100); + } + + rtl8139_regs_unlock(rtl8139->io_port); + pio_write_16(rtl8139->io_port + BMCR, bmcr_val); + rtl8139_regs_lock(rtl8139->io_port); + return EOK; +} + +/** Enable autonegoation with specific advertisement + * + * @param dev The device to update + * @param advertisement The advertisement to set + * + * @returns EINVAL if the advertisement mode is not supproted + * @returns EOK if advertisement mode set successfully + */ +static int rtl8139_autoneg_enable(ddf_fun_t *fun, uint32_t advertisement) +{ + assert(fun); + + rtl8139_t *rtl8139 = nic_get_specific(nic_get_from_ddf_fun(fun)); + assert(rtl8139); + + if (advertisement == 0) { + advertisement = RTL8139_AUTONEG_CAPS; + } + + if ((advertisement | RTL8139_AUTONEG_CAPS) != RTL8139_AUTONEG_CAPS) + return EINVAL; /* some unsuported mode is requested */ + + assert(advertisement != 0); + + /* Set the autonegotiation advertisement */ + uint16_t anar = ANAR_SELECTOR; /* default selector */ + if (advertisement & ETH_AUTONEG_10BASE_T_FULL) + anar |= ANAR_10_FD; + if (advertisement & ETH_AUTONEG_10BASE_T_HALF) + anar |= ANAR_10_HD; + if (advertisement & ETH_AUTONEG_100BASE_TX_FULL) + anar |= ANAR_100TX_FD; + if (advertisement & ETH_AUTONEG_100BASE_TX_HALF) + anar |= ANAR_100TX_HD; + if (advertisement & ETH_AUTONEG_PAUSE_SYMETRIC) + anar |= ANAR_PAUSE; + + uint16_t bmcr_val = pio_read_16(rtl8139->io_port + BMCR); + bmcr_val |= BMCR_AN_ENABLE; + + pio_write_16(rtl8139->io_port + ANAR, anar); + + rtl8139_regs_unlock(rtl8139->io_port); + pio_write_16(rtl8139->io_port + BMCR, bmcr_val); + rtl8139_regs_lock(rtl8139->io_port); + return EOK; +} + +/** Disable advertisement functionality + * + * @param dev The device to update + * + * @returns EOK + */ +static int rtl8139_autoneg_disable(ddf_fun_t *fun) +{ + assert(fun); + + rtl8139_t *rtl8139 = nic_get_specific(nic_get_from_ddf_fun(fun)); + assert(rtl8139); + + uint16_t bmcr_val = pio_read_16(rtl8139->io_port + BMCR); + + bmcr_val &= ~((uint16_t)BMCR_AN_ENABLE); + + rtl8139_regs_unlock(rtl8139->io_port); + pio_write_16(rtl8139->io_port + BMCR, bmcr_val); + rtl8139_regs_lock(rtl8139->io_port); + + return EOK; +} + +/** Obtain the advertisement NIC framework value from the ANAR/ANLPAR register + * value + * + * @param[in] anar The ANAR register value + * @param[out] advertisement The advertisement result + */ +static void rtl8139_get_anar_state(uint16_t anar, uint32_t *advertisement) +{ + *advertisement = 0; + if (anar & ANAR_10_HD) + *advertisement |= ETH_AUTONEG_10BASE_T_HALF; + if (anar & ANAR_10_FD) + *advertisement |= ETH_AUTONEG_10BASE_T_FULL; + if (anar & ANAR_100TX_HD) + *advertisement |= ETH_AUTONEG_100BASE_TX_HALF; + if (anar & ANAR_100TX_FD) + *advertisement |= ETH_AUTONEG_100BASE_TX_FULL; + if (anar & ANAR_100T4) + *advertisement |= ETH_AUTONEG_100BASE_T4_HALF; + if (anar & ANAR_PAUSE) + *advertisement |= ETH_AUTONEG_PAUSE_SYMETRIC; +} + +/** Check the autonegotion state + * + * @param[in] dev The device to check + * @param[out] advertisement The device advertisement + * @param[out] their_adv The partners advertisement + * @param[out] result The autonegotion state + * @param[out] their_result The link partner autonegotion status + * + * @returns EOK + */ +static int rtl8139_autoneg_probe(ddf_fun_t *fun, uint32_t *advertisement, + uint32_t *their_adv, nic_result_t *result, nic_result_t *their_result) +{ + assert(fun); + + rtl8139_t *rtl8139 = nic_get_specific(nic_get_from_ddf_fun(fun)); + assert(rtl8139); + + uint16_t bmcr = pio_read_16(rtl8139->io_port + BMCR); + uint16_t anar = pio_read_16(rtl8139->io_port + ANAR); + uint16_t anar_lp = pio_read_16(rtl8139->io_port + ANLPAR); + uint16_t aner = pio_read_16(rtl8139->io_port + ANER); + + if (bmcr & BMCR_AN_ENABLE) { + *result = NIC_RESULT_ENABLED; + } else { + *result = NIC_RESULT_DISABLED; + } + + if (aner & ANER_LP_NW_ABLE) { + *their_result = NIC_RESULT_ENABLED; + } else { + *their_result = NIC_RESULT_DISABLED; + } + + rtl8139_get_anar_state(anar, advertisement); + rtl8139_get_anar_state(anar_lp, their_adv); + + return EOK; +} + +/** Restart autonegotiation process + * + * @param dev The device to update + * + * @returns EOK + */ +static int rtl8139_autoneg_restart(ddf_fun_t *fun) +{ + assert(fun); + + rtl8139_t *rtl8139 = nic_get_specific(nic_get_from_ddf_fun(fun)); + assert(rtl8139); + + uint16_t bmcr = pio_read_16(rtl8139->io_port + BMCR); + bmcr |= BMCR_AN_RESTART; + bmcr |= BMCR_AN_ENABLE; + + rtl8139_regs_unlock(rtl8139); + pio_write_16(rtl8139->io_port + BMCR, bmcr); + rtl8139_regs_lock(rtl8139); + + return EOK; +} + +/** Notify NIC framework about HW filtering state when promisc mode was disabled + * + * @param nic_data The NIC data + * @param mcast_mode Current multicast mode + * @param was_promisc Sign if the promiscuous mode was active before disabling + */ +inline static void rtl8139_rcx_promics_rem(nic_t *nic_data, + nic_multicast_mode_t mcast_mode, uint8_t was_promisc) +{ + assert(nic_data); + + if (was_promisc != 0) { + if (mcast_mode == NIC_MULTICAST_LIST) + nic_report_hw_filtering(nic_data, 1, 0, -1); + else + nic_report_hw_filtering(nic_data, 1, 1, -1); + } else { + nic_report_hw_filtering(nic_data, 1, -1, -1); + } +} + +/** Set unicast packets acceptance mode + * + * @param nic_data The nic device to update + * @param mode The mode to set + * @param addr Ignored, no HW support, just use unicast promisc + * @param addr_cnt Ignored, no HW support + * + * @returns EOK + */ +static int rtl8139_unicast_set(nic_t *nic_data, nic_unicast_mode_t mode, + const nic_address_t *addr, size_t addr_cnt) +{ + assert(nic_data); + + rtl8139_t *rtl8139 = nic_get_specific(nic_data); + assert(rtl8139); + + uint8_t was_promisc = rtl8139->rcr_data.ucast_mask & RCR_ACCEPT_ALL_PHYS; + + nic_multicast_mode_t mcast_mode; + nic_query_multicast(nic_data, &mcast_mode, 0, NULL, NULL); + + switch (mode) { + case NIC_UNICAST_BLOCKED: + rtl8139->rcr_data.ucast_mask = 0; + rtl8139_rcx_promics_rem(nic_data, mcast_mode, was_promisc); + break; + case NIC_UNICAST_DEFAULT: + rtl8139->rcr_data.ucast_mask = RCR_ACCEPT_PHYS_MATCH; + rtl8139_rcx_promics_rem(nic_data, mcast_mode, was_promisc); + break; + case NIC_UNICAST_LIST: + rtl8139->rcr_data.ucast_mask = RCR_ACCEPT_PHYS_MATCH + | RCR_ACCEPT_ALL_PHYS; + + if (mcast_mode == NIC_MULTICAST_PROMISC) + nic_report_hw_filtering(nic_data, 0, 1, -1); + else + nic_report_hw_filtering(nic_data, 0, 0, -1); + break; + case NIC_UNICAST_PROMISC: + rtl8139->rcr_data.ucast_mask = RCR_ACCEPT_PHYS_MATCH + | RCR_ACCEPT_ALL_PHYS; + + if (mcast_mode == NIC_MULTICAST_PROMISC) + nic_report_hw_filtering(nic_data, 1, 1, -1); + else + nic_report_hw_filtering(nic_data, 1, 0, -1); + break; + default: + return ENOTSUP; + } + fibril_mutex_lock(&rtl8139->rx_lock); + rtl8139_hw_update_rcr(rtl8139); + fibril_mutex_unlock(&rtl8139->rx_lock); + return EOK; +} + +/** Set multicast packets acceptance mode + * + * @param nic_data The nic device to update + * @param mode The mode to set + * @param addr Addresses to accept + * @param addr_cnt Addresses count + * + * @returns EOK + */ +static int rtl8139_multicast_set(nic_t *nic_data, nic_multicast_mode_t mode, + const nic_address_t *addr, size_t addr_count) +{ + assert(nic_data); + assert(addr_count == 0 || addr); + + rtl8139_t *rtl8139 = nic_get_specific(nic_data); + assert(rtl8139); + + switch (mode) { + case NIC_MULTICAST_BLOCKED: + rtl8139->rcr_data.mcast_mask = 0; + if ((rtl8139->rcr_data.ucast_mask & RCR_ACCEPT_ALL_PHYS) != 0) + nic_report_hw_filtering(nic_data, -1, 0, -1); + else + nic_report_hw_filtering(nic_data, -1, 1, -1); + break; + case NIC_MULTICAST_LIST: + rtl8139_hw_set_mcast_mask(rtl8139, nic_mcast_hash(addr, addr_count)); + rtl8139->rcr_data.mcast_mask = RCR_ACCEPT_MULTICAST; + nic_report_hw_filtering(nic_data, -1, 0, -1); + break; + case NIC_MULTICAST_PROMISC: + rtl8139_hw_set_mcast_mask(rtl8139, RTL8139_MCAST_MASK_PROMISC); + rtl8139->rcr_data.mcast_mask = RCR_ACCEPT_MULTICAST; + nic_report_hw_filtering(nic_data, -1, 1, -1); + break; + default: + return ENOTSUP; + } + fibril_mutex_lock(&rtl8139->rx_lock); + rtl8139_hw_update_rcr(rtl8139); + fibril_mutex_unlock(&rtl8139->rx_lock); + return EOK; +} + +/** Set broadcast packets acceptance mode + * + * @param nic_data The nic device to update + * @param mode The mode to set + * + * @returns EOK + */ +static int rtl8139_broadcast_set(nic_t *nic_data, nic_broadcast_mode_t mode) +{ + assert(nic_data); + + rtl8139_t *rtl8139 = nic_get_specific(nic_data); + assert(rtl8139); + + switch (mode) { + case NIC_BROADCAST_BLOCKED: + rtl8139->rcr_data.bcast_mask = 0; + break; + case NIC_BROADCAST_ACCEPTED: + rtl8139->rcr_data.bcast_mask = RCR_ACCEPT_BROADCAST; + break; + default: + return ENOTSUP; + } + fibril_mutex_lock(&rtl8139->rx_lock); + rtl8139_hw_update_rcr(rtl8139); + fibril_mutex_unlock(&rtl8139->rx_lock); + return EOK; +} + +/** Get state of acceptance of weird packets + * + * @param[in] device The device to check + * @param[out] mode The current mode + */ +static int rtl8139_defective_get_mode(ddf_fun_t *fun, uint32_t *mode) +{ + assert(fun); + assert(mode); + + rtl8139_t *rtl8139 = nic_get_specific(nic_get_from_ddf_fun(fun)); + assert(rtl8139); + + *mode = 0; + if (rtl8139->rcr_data.defect_mask & RCR_ACCEPT_ERROR) + *mode |= NIC_DEFECTIVE_BAD_CRC; + if (rtl8139->rcr_data.defect_mask & RCR_ACCEPT_RUNT) + *mode |= NIC_DEFECTIVE_SHORT; + + return EOK; +}; + +/** Set acceptance of weird packets + * + * @param device The device to update + * @param mode The mode to set + * + * @returns ENOTSUP if the mode is not supported + * @returns EOK of mode was set + */ +static int rtl8139_defective_set_mode(ddf_fun_t *fun, uint32_t mode) +{ + assert(fun); + + rtl8139_t *rtl8139 = nic_get_specific(nic_get_from_ddf_fun(fun)); + assert(rtl8139); + + if ((mode & (NIC_DEFECTIVE_SHORT | NIC_DEFECTIVE_BAD_CRC)) != mode) + return ENOTSUP; + + rtl8139->rcr_data.defect_mask = 0; + if (mode & NIC_DEFECTIVE_SHORT) + rtl8139->rcr_data.defect_mask |= RCR_ACCEPT_RUNT; + if (mode & NIC_DEFECTIVE_BAD_CRC) + rtl8139->rcr_data.defect_mask |= RCR_ACCEPT_ERROR; + + fibril_mutex_lock(&rtl8139->rx_lock); + rtl8139_hw_update_rcr(rtl8139); + fibril_mutex_unlock(&rtl8139->rx_lock); + return EOK; +}; + + +/** Turn Wakeup On Lan method on + * + * @param nic_data The NIC to update + * @param virtue The method to turn on + * + * @returns EINVAL if the method is not supported + * @returns EOK if succeed + * @returns ELIMIT if no more methods of this kind can be enabled + */ +static int rtl8139_wol_virtue_add(nic_t *nic_data, + const nic_wol_virtue_t *virtue) +{ + assert(nic_data); + assert(virtue); + + rtl8139_t *rtl8139 = nic_get_specific(nic_data); + assert(rtl8139); + + switch(virtue->type) { + case NIC_WV_BROADCAST: + rtl8139_hw_reg_add_8(rtl8139, CONFIG5, CONFIG5_BROADCAST_WAKEUP); + break; + case NIC_WV_LINK_CHANGE: + rtl8139_regs_unlock(rtl8139->io_port); + rtl8139_hw_reg_add_8(rtl8139, CONFIG3, CONFIG3_LINK_UP); + rtl8139_regs_lock(rtl8139->io_port); + break; + case NIC_WV_MAGIC_PACKET: + if (virtue->data) + return EINVAL; + rtl8139_regs_unlock(rtl8139->io_port); + rtl8139_hw_reg_add_8(rtl8139, CONFIG3, CONFIG3_MAGIC); + rtl8139_regs_lock(rtl8139->io_port); + break; + default: + return EINVAL; + }; + if(rtl8139->pm.active++ == 0) + rtl8139_hw_pmen_set(rtl8139, 1); + return EOK; +} + +/** Turn Wakeup On Lan method off + * + * @param nic_data The NIC to update + * @param virtue The method to turn off + */ +static void rtl8139_wol_virtue_rem(nic_t *nic_data, + const nic_wol_virtue_t *virtue) +{ + assert(nic_data); + assert(virtue); + + rtl8139_t *rtl8139 = nic_get_specific(nic_data); + assert(rtl8139); + + switch(virtue->type) { + case NIC_WV_BROADCAST: + rtl8139_hw_reg_rem_8(rtl8139, CONFIG5, CONFIG5_BROADCAST_WAKEUP); + break; + case NIC_WV_LINK_CHANGE: + rtl8139_regs_unlock(rtl8139->io_port); + rtl8139_hw_reg_rem_8(rtl8139, CONFIG3, CONFIG3_LINK_UP); + rtl8139_regs_lock(rtl8139->io_port); + break; + case NIC_WV_MAGIC_PACKET: + rtl8139_regs_unlock(rtl8139->io_port); + rtl8139_hw_reg_rem_8(rtl8139, CONFIG3, CONFIG3_MAGIC); + rtl8139_regs_lock(rtl8139->io_port); + break; + default: + return; + }; + rtl8139->pm.active--; + if (rtl8139->pm.active == 0) + rtl8139_hw_pmen_set(rtl8139, 0); +} + + +/** Set polling mode + * + * @param device The device to set + * @param mode The mode to set + * @param period The period for NIC_POLL_PERIODIC + * + * @returns EOK if succeed + * @returns ENOTSUP if the mode is not supported + */ +static int rtl8139_poll_mode_change(nic_t *nic_data, nic_poll_mode_t mode, + const struct timeval *period) +{ + assert(nic_data); + int rc = EOK; + + rtl8139_t *rtl8139 = nic_get_specific(nic_data); + assert(rtl8139); + + fibril_mutex_lock(&rtl8139->rx_lock); + + switch(mode) { + case NIC_POLL_IMMEDIATE: + rtl8139->int_mask = RTL_DEFAULT_INTERRUPTS; + break; + case NIC_POLL_ON_DEMAND: + rtl8139->int_mask = 0; + break; + case NIC_POLL_PERIODIC: + assert(period); + + rtl8139_timer_act_t new_timer; + rc = rtl8139_timer_act_init(&new_timer, RTL8139_PCI_FREQ_KHZ, period); + if (rc != EOK) + break; + + /* Disable timer interrupts while working with timer-related data */ + rtl8139->int_mask = 0; + rtl8139_hw_int_enable(rtl8139); + + rtl8139->poll_timer = new_timer; + rtl8139->int_mask = INT_TIME_OUT; + + /* Force timer interrupt start be writing nonzero value to timer + * interrutp register (should be small to prevent big delay) + * Read TCTR to reset timer counter + * Change values to simulate the last interrupt from the period. + */ + pio_write_32(rtl8139->io_port + TIMERINT, 10); + pio_write_32(rtl8139->io_port + TCTR, 0); + + nlog_debug("Periodic mode. Interrupt mask %"PRIx16", poll.full_skips %" + PRIu32", last timer %"PRIu32".", rtl8139->int_mask, + rtl8139->poll_timer.full_skips, rtl8139->poll_timer.last_val); + break; + default: + rc = ENOTSUP; + break; + } + + rtl8139_hw_int_enable(rtl8139); + + fibril_mutex_unlock(&rtl8139->rx_lock); + + return rc; +} + +/** Force receiving all packets in the receive buffer + * + * @param device The device to receive + */ +static void rtl8139_poll(nic_t *nic_data) +{ + assert(nic_data); + + rtl8139_t *rtl8139 = nic_get_specific(nic_data); + assert(rtl8139); + + uint16_t isr = pio_read_16(rtl8139->io_port + ISR); + pio_write_16(rtl8139->io_port + ISR, 0); + + rtl8139_interrupt_impl(nic_data, isr); +} + + +/** Main function of RTL8139 driver + * + * Just initialize the driver structures and + * put it into the device drivers interface + */ +int main(void) +{ + int rc = nic_driver_init(NAME); + if (rc != EOK) + return rc; + nic_driver_implement( + &rtl8139_driver_ops, &rtl8139_dev_ops, &rtl8139_nic_iface); + + nlog_set_min_severity(DEBUG); + nlog_info("HelenOS RTL8139 driver started"); + return ddf_driver_main(&rtl8139_driver); +} Index: uspace/drv/nic/rtl8139/driver.h =================================================================== --- uspace/drv/nic/rtl8139/driver.h (revision bf848717e8d508127f8be22655d603fdd89fe773) +++ uspace/drv/nic/rtl8139/driver.h (revision bf848717e8d508127f8be22655d603fdd89fe773) @@ -0,0 +1,238 @@ +/* + * Copyright (c) 2011 Jiri Michalec + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RTL8139_DRIVER_H_ +#define RTL8139_DRIVER_H_ + +#include "rtl8139_defs.h" +#include "rtl8139_general.h" +#include +#include +#include + +/** The driver name */ +#define NAME "rtl8139" +/** Transmittion buffers count */ +#define TX_BUFF_COUNT 4 +/** Size of buffer for one packet + * - 2kB + */ +#define TX_BUFF_SIZE (2 * 1024) +/** Count of pages to allocate for TxBuffers */ +#define TX_PAGES 2 + +/** Size of the CRC after the received frame in the receiver buffer */ +#define RTL8139_CRC_SIZE 4 + +/** The default mode of accepting unicast packets */ +#define RTL8139_RCR_UCAST_DEFAULT RCR_ACCEPT_PHYS_MATCH +/** The default mode of accepting multicast packets */ +#define RTL8139_RCR_MCAST_DEFAULT 0 +/** The default mode of accepting broadcast packets */ +#define RTL8139_RCR_BCAST_DEFAULT RCR_ACCEPT_BROADCAST +/** The default mode of accepting defect packets */ +#define RTL8139_RCR_DEFECT_DEFAULT 0 + +/** Mask for accepting all multicast */ +#define RTL8139_MCAST_MASK_PROMISC UINT64_MAX + +/** Data */ +struct rtl8139_rcr_data { + /** Configuration part of RCR */ + uint32_t rcr_base; + /** Mask of unicast */ + uint8_t ucast_mask; + /** Mask of multicast */ + uint8_t mcast_mask; + /** Mask of broadcast */ + uint8_t bcast_mask; + /** Mask of defective */ + uint8_t defect_mask; +}; + +/** Power management related data */ +typedef struct rtl8139_pm { + /** Count of used activities which needs PMEn bit set */ + int active; +} rtl8139_pm_t; + +/** RTL8139 device data */ +typedef struct rtl8139_data { + /** I/O address of the device */ + void *io_addr; + /** Mapped I/O port */ + void *io_port; + /** The irq assigned */ + int irq; + + /** Mask of the turned interupts (IMR value) */ + uint16_t int_mask; + + /** The memory allocated for the transmittion buffers + * Each buffer takes 2kB + */ + dma_mem_t tx_buff_mem; + /** Virtual adresses of the Tx buffers */ + void *tx_buff[TX_BUFF_COUNT]; + + /** The nubmer of the next buffer to use, index = tx_next % TX_BUFF_COUNT */ + size_t tx_next; + /** The number of the first used buffer in the row + * + * tx_used is in the interval tx_next - TX_BUFF_COUNT and tx_next: + * tx_next - TX_BUFF_COUNT: there is no useable Tx descriptor + * tx_next: all Tx descriptors are can be used + */ + size_t tx_used; + + /** Buffer for receiving packets */ + dma_mem_t rx_buff; + + /** Receiver control register data */ + struct rtl8139_rcr_data rcr_data; + + /** Power management information */ + rtl8139_pm_t pm; + + /** Lock for receiver */ + fibril_mutex_t rx_lock; + /** Lock for transmitter */ + fibril_mutex_t tx_lock; + + /** Polling mode information */ + rtl8139_timer_act_t poll_timer; + + /** Backward pointer to nic_data */ + nic_t *nic_data; + + /** Version of RT8139 controller */ + enum rtl8139_version_id hw_version; +} rtl8139_t; + + +/* ***** Pointers casting - for both amd64 and ia32 ***** */ + +/** Cast pointer to uint32_t + * + * @param ptr The pointer to cast + * @return The uint32_t pointer representation. The low 32 bit is taken + * in the case of the 64 bit pointers + */ +#define PTR2U32(ptr) ((uint32_t)((size_t)(ptr))) + +/** Check if the pointer can be cast to uint32_t without the data lost + * + * @param ptr The pointer to check + * @return The true value if the pointer can be cast, false if not + */ +#define PTR_IS_32(ptr) ((size_t)PTR2U32(ptr) == (size_t)(ptr)) + +/** Cast the ioaddr part to the void* + * + * @param ioaddr The ioaddr value + */ +#define IOADDR_TO_PTR(ioaddr) ((void*)((size_t)(ioaddr))) + + + +/* ***** Bit operation macros ***** */ + +/** Set the bits specified by the given bit mask to the different values + * + * The bit from the src is used if the corresponding bit in the mask is 0, + * the bit from the value is used if the corresponding bit in the mask is 1 + * + * @param src The original value + * @param value The new bit value + * @param mask The mask to specify modified bits + * @param type The values type + * + * @return New value + */ +#define bit_set_part_g( src, value, mask, type ) \ + ((type)(((src) & ~((type)(mask))) | ((value) & (type)(mask)))) + +/** Set the bits specified by the given bit mask to the different values + * + * The version of the uint32_t + * + * @see bit_set_part_g + */ + +#define bit_set_part_32(src, value, mask) bit_set_part_g(src, value, mask, uint32_t) +/** Set the bits specified by the given bit mask to the different values + * + * The version of the uint16_t + * + * @see bit_set_part_g + */ + +#define bit_set_part_16(src, value, mask) bit_set_part_g(src, value, mask, uint16_t) + +/** Set the bits specified by the given bit mask to the different values + * + * The version of the uint8_t + * + * @see bit_set_part_g + */ +#define bit_set_part_8(src, value, mask) bit_set_part_g(src, value, mask, uint8_t) + +/** Clear specified bits in the value + * + * @param src Original value + * @param clear_mask Bits to clear mask + * @param type The values type + */ +#define bit_clear_g(src, clear_mask, type) ((type)((src) & ~((type)(clear_mask)))) + +/** Clear specified bits in the value, 32bit version + * + * @see bit_clear_g + */ +#define bit_clear_32(src, clear_mask) bit_clear_g(src, clear_mask, uint32_t) +/** Clear specified bits in the value, 16bit version + * + * @see bit_clear_g + */ +#define bit_clear_16(src, clear_mask) bit_clear_g(src, clear_mask, uint16_t) +/** Clear specified bits in the value, 8bit version + * + * @see bit_clear_g + */ +#define bit_clear_8(src, clear_mask) bit_clear_g(src, clear_mask, uint8_t) + +/** Obtain value of the TSD register with size part modified + * + * @param tsd_value Old value of the TSD + * @param size The size to set + */ +#define rtl8139_tsd_set_size(tsd_value, size) \ + bit_set_part_32(tsd_value, (size) << TSD_SIZE_SHIFT, TSD_SIZE_MASK << TSD_SIZE_SHIFT) + + +#endif Index: uspace/drv/nic/rtl8139/general.c =================================================================== --- uspace/drv/nic/rtl8139/general.c (revision bf848717e8d508127f8be22655d603fdd89fe773) +++ uspace/drv/nic/rtl8139/general.c (revision bf848717e8d508127f8be22655d603fdd89fe773) @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2011 Jiri Michalec + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @file + * + * General functions and structures used in rtl8139 driver + */ + +#include "rtl8139_general.h" + +#include +#include +#include +#include + +/** Copy block of the memory from wrapped source buffer. + * + * Start on the specific offset in the source buffer and * copy data_size bytes + * - continue from the buffer start after getting the end + * + * @param dest The destination memory + * @param src_begin The begin of the source buffer + * @param src_offset The offset in the source buffer to start copy + * @param src_size The source buffer size + * @param data_size The amount of data to copy + * + * @return NULL if the error occures, dest if succeed + */ +void* rtl8139_memcpy_wrapped(void *dest, const void *src, size_t src_offset, + size_t src_size, size_t data_size) +{ + src_offset %= src_size; + if (data_size > src_size) + return NULL; + + size_t to_src_end = src_size - src_offset; + if (data_size <= to_src_end) { + return memcpy(dest, src + src_offset, data_size); + } + + size_t rem_size = data_size - to_src_end; + + /* First copy the end part of the data (from the source begining), + * then copy the begining + */ + memcpy(dest + to_src_end, src, rem_size); + return memcpy(dest, src + src_offset, to_src_end); +} + +/** Initialize the timer register structures + * + * The structure will be initialized to the state that the first call of + * rtl8139_timer_act_step function will be the period expiration + * + * @param ta The timer structure + * @param timer_freq The timer frequency in kHz + * @param time The requested time + * + * @return EOK if succeed, negative error code otherwise + */ +int rtl8139_timer_act_init(rtl8139_timer_act_t * ta, uint32_t timer_freq, + const struct timeval *time) +{ + if (!ta || timer_freq == 0 || !time) + return EINVAL; + memset(ta, 0, sizeof(rtl8139_timer_act_t)); + + uint32_t tics_per_ms = timer_freq; + uint32_t seconds_in_reg = UINT32_MAX / (tics_per_ms * 1000); + ta->full_val = seconds_in_reg * tics_per_ms * 1000; + + struct timeval remains = *time; + ta->full_skips = remains.tv_sec / seconds_in_reg; + remains.tv_sec = remains.tv_sec % seconds_in_reg; + + if (remains.tv_usec > RTL8139_USEC_IN_SEC) { + remains.tv_sec += remains.tv_usec / RTL8139_USEC_IN_SEC; + remains.tv_usec = remains.tv_usec % RTL8139_USEC_IN_SEC; + + /* it can be increased above seconds_in_reg again */ + ta->full_skips += remains.tv_sec / seconds_in_reg; + remains.tv_sec = remains.tv_sec % seconds_in_reg; + } + + ta->last_val = remains.tv_sec * 1000 + remains.tv_usec / 1000; + ta->last_val *= tics_per_ms; + + /* Force inital setting in the next step */ + ta->full_skips_remains = 0; + ta->last_run = 1; + return EOK; +}; + + +/** Make one step timer step + * + * @param ta Timer structure + * @param new_reg[out] Register value to set + * + * @return Nonzero if whole period expired, zero if part of period expired + */ +int rtl8139_timer_act_step(rtl8139_timer_act_t * ta, uint32_t *new_reg) +{ + uint32_t next_val = 0; + int expired = 0; + + if (ta->last_run || (ta->last_val == 0 && ta->full_skips_remains == 0)) { + ta->full_skips_remains = ta->full_skips; + ta->last_run = 0; + expired = 1; + } + + if (ta->full_skips_remains > 0) { + next_val = ta->full_val; + ta->full_skips_remains--; + } else { + next_val = ta->last_val; + ta->last_run = 1; + } + + if (new_reg) + *new_reg = next_val; + + return expired; +}; + Index: uspace/drv/nic/rtl8139/general.h =================================================================== --- uspace/drv/nic/rtl8139/general.h (revision bf848717e8d508127f8be22655d603fdd89fe773) +++ uspace/drv/nic/rtl8139/general.h (revision bf848717e8d508127f8be22655d603fdd89fe773) @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2011 Jiri Michalec + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @file + * + * General functions and structures used in rtl8139 driver + */ + +#ifndef RTL8139_GENERAL_H_ +#define RTL8139_GENERAL_H_ + +#include + +extern void* rtl8139_memcpy_wrapped(void *dest, const void *src_buf, + size_t src_offset, size_t src_size, size_t data_size); + + +/** Structure for HW timer control */ +typedef struct rtl8139_timer_act { + /** Register value set in the last timer period */ + uint32_t last_val; + /** Register value set in the common timer period */ + uint32_t full_val; + + /** Amount of full register periods in timer period */ + size_t full_skips; + /** Remaining full register periods to the next period end */ + size_t full_skips_remains; + /** Mark if there is a last run */ + int last_run; +} rtl8139_timer_act_t; + +/** Count of microseconds in second */ +#define RTL8139_USEC_IN_SEC 1000000 + +extern int rtl8139_timer_act_init(rtl8139_timer_act_t *ta, uint32_t timer_freq, + const struct timeval *time); +extern int rtl8139_timer_act_step(rtl8139_timer_act_t *ta, uint32_t *new_reg); + + +#endif Index: uspace/drv/nic/rtl8139/rtl8139.ma =================================================================== --- uspace/drv/nic/rtl8139/rtl8139.ma (revision bf848717e8d508127f8be22655d603fdd89fe773) +++ uspace/drv/nic/rtl8139/rtl8139.ma (revision bf848717e8d508127f8be22655d603fdd89fe773) @@ -0,0 +1,1 @@ +10 pci/ven=10ec&dev=8139