Index: uspace/drv/nic/ne2k/Makefile =================================================================== --- uspace/drv/nic/ne2k/Makefile (revision bd83012835a346d3b98fb0fa4aac917aa404a734) +++ uspace/drv/nic/ne2k/Makefile (revision bd83012835a346d3b98fb0fa4aac917aa404a734) @@ -0,0 +1,38 @@ +# +# Copyright (c) 2011 Radim Vansa +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +USPACE_PREFIX = ../../.. +LIBS = $(LIBDRV_PREFIX)/libdrv.a $(LIBNET_PREFIX)/libnet.a $(LIBNIC_PREFIX)/libnic.a +EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include -I$(LIBNET_PREFIX)/include -I$(LIBNIC_PREFIX)/include +BINARY = ne2k + +SOURCES = \ + dp8390.c \ + ne2k.c + +include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/nic/ne2k/dp8390.c =================================================================== --- uspace/drv/nic/ne2k/dp8390.c (revision bd83012835a346d3b98fb0fa4aac917aa404a734) +++ uspace/drv/nic/ne2k/dp8390.c (revision bd83012835a346d3b98fb0fa4aac917aa404a734) @@ -0,0 +1,677 @@ +/* + * Copyright (c) 2009 Lukas Mejdrech + * Copyright (c) 2011 Martin Decky + * Copyright (c) 2011 Radim Vansa + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This code is based upon the NE2000 driver for MINIX, + * distributed according to a BSD-style license. + * + * Copyright (c) 1987, 1997, 2006 Vrije Universiteit + * Copyright (c) 1992, 1994 Philip Homburg + * Copyright (c) 1996 G. Falzoni + * + */ + +/** + * @addtogroup drv_ne2k + * @{ + */ + +/** + * @file + * @brief NE2000 driver core + * + * NE2000 (based on DP8390) network interface core implementation. + * Only the basic NE2000 PIO (ISA) interface is supported, remote + * DMA is completely absent from this code for simplicity. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include "dp8390.h" + +/** Page size */ +#define DP_PAGE 256 + +/** 6 * DP_PAGE >= 1514 bytes */ +#define SQ_PAGES 6 + +/** Type definition of the receive header + * + */ +typedef struct { + /** Copy of RSR */ + uint8_t status; + + /** Pointer to next packet */ + uint8_t next; + + /** Receive Byte Count Low */ + uint8_t rbcl; + + /** Receive Byte Count High */ + uint8_t rbch; +} recv_header_t; + +/** Read a memory block word by word. + * + * @param[in] port Source address. + * @param[out] buf Destination buffer. + * @param[in] size Memory block size in bytes. + * + */ +static void pio_read_buf_16(void *port, void *buf, size_t size) +{ + size_t i; + + for (i = 0; (i << 1) < size; i++) + *((uint16_t *) buf + i) = pio_read_16((ioport16_t *) (port)); +} + +/** Write a memory block word by word. + * + * @param[in] port Destination address. + * @param[in] buf Source buffer. + * @param[in] size Memory block size in bytes. + * + */ +static void pio_write_buf_16(void *port, void *buf, size_t size) +{ + size_t i; + + for (i = 0; (i << 1) < size; i++) + pio_write_16((ioport16_t *) port, *((uint16_t *) buf + i)); +} + +static void ne2k_download(ne2k_t *ne2k, void *buf, size_t addr, size_t size) +{ + size_t esize = size & ~1; + + pio_write_8(ne2k->port + DP_RBCR0, esize & 0xff); + pio_write_8(ne2k->port + DP_RBCR1, (esize >> 8) & 0xff); + pio_write_8(ne2k->port + DP_RSAR0, addr & 0xff); + pio_write_8(ne2k->port + DP_RSAR1, (addr >> 8) & 0xff); + pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA); + + if (esize != 0) { + pio_read_buf_16(ne2k->data_port, buf, esize); + size -= esize; + buf += esize; + } + + if (size) { + assert(size == 1); + + uint16_t word = pio_read_16(ne2k->data_port); + memcpy(buf, &word, 1); + } +} + +static void ne2k_upload(ne2k_t *ne2k, void *buf, size_t addr, size_t size) +{ + size_t esize = size & ~1; + + pio_write_8(ne2k->port + DP_RBCR0, esize & 0xff); + pio_write_8(ne2k->port + DP_RBCR1, (esize >> 8) & 0xff); + pio_write_8(ne2k->port + DP_RSAR0, addr & 0xff); + pio_write_8(ne2k->port + DP_RSAR1, (addr >> 8) & 0xff); + pio_write_8(ne2k->port + DP_CR, CR_DM_RW | CR_PS_P0 | CR_STA); + + if (esize != 0) { + pio_write_buf_16(ne2k->data_port, buf, esize); + size -= esize; + buf += esize; + } + + if (size) { + assert(size == 1); + + uint16_t word = 0; + + memcpy(&word, buf, 1); + pio_write_16(ne2k->data_port, word); + } +} + +static void ne2k_init(ne2k_t *ne2k) +{ + unsigned int i; + + /* Reset the ethernet card */ + uint8_t val = pio_read_8(ne2k->port + NE2K_RESET); + usleep(2000); + pio_write_8(ne2k->port + NE2K_RESET, val); + usleep(2000); + + /* Reset the DP8390 */ + pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT); + for (i = 0; i < NE2K_RETRY; i++) { + if (pio_read_8(ne2k->port + DP_ISR) != 0) + break; + } +} + +/** Probe and initialize the network interface. + * + * @param[in,out] ne2k Network interface structure. + * @param[in] port Device address. + * @param[in] irq Device interrupt vector. + * + * @return EOK on success. + * @return EXDEV if the network interface was not recognized. + * + */ +int ne2k_probe(ne2k_t *ne2k) +{ + unsigned int i; + + ne2k_init(ne2k); + + /* Check if the DP8390 is really there */ + uint8_t val = pio_read_8(ne2k->port + DP_CR); + if ((val & (CR_STP | CR_DM_ABORT)) != (CR_STP | CR_DM_ABORT)) + return EXDEV; + + /* Disable the receiver and init TCR and DCR */ + pio_write_8(ne2k->port + DP_RCR, RCR_MON); + pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL); + pio_write_8(ne2k->port + DP_DCR, DCR_WORDWIDE | DCR_8BYTES | DCR_BMS); + + /* Setup a transfer to get the MAC address */ + pio_write_8(ne2k->port + DP_RBCR0, ETH_ADDR << 1); + pio_write_8(ne2k->port + DP_RBCR1, 0); + pio_write_8(ne2k->port + DP_RSAR0, 0); + pio_write_8(ne2k->port + DP_RSAR1, 0); + pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA); + + for (i = 0; i < ETH_ADDR; i++) + ne2k->mac.address[i] = pio_read_16(ne2k->data_port); + + return EOK; +} + +void ne2k_set_physical_address(ne2k_t *ne2k, const nic_address_t *address) +{ + memcpy(&ne2k->mac, address, sizeof(nic_address_t)); + + pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STP); + + pio_write_8(ne2k->port + DP_RBCR0, ETH_ADDR << 1); + pio_write_8(ne2k->port + DP_RBCR1, 0); + pio_write_8(ne2k->port + DP_RSAR0, 0); + pio_write_8(ne2k->port + DP_RSAR1, 0); + pio_write_8(ne2k->port + DP_CR, CR_DM_RW | CR_PS_P0 | CR_STA); + + size_t i; + for (i = 0; i < ETH_ADDR; i++) + pio_write_16(ne2k->data_port, ne2k->mac.address[i]); + + //pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STA); +} + +/** Start the network interface. + * + * @param[in,out] ne2k Network interface structure. + * + * @return EOK on success. + * @return EXDEV if the network interface is disabled. + * + */ +int ne2k_up(ne2k_t *ne2k) +{ + if (!ne2k->probed) + return EXDEV; + + ne2k_init(ne2k); + + /* + * Setup send queue. Use the first + * SQ_PAGES of NE2000 memory for the send + * buffer. + */ + ne2k->sq.dirty = false; + ne2k->sq.page = NE2K_START / DP_PAGE; + fibril_mutex_initialize(&ne2k->sq_mutex); + fibril_condvar_initialize(&ne2k->sq_cv); + + /* + * Setup receive ring buffer. Use all the rest + * of the NE2000 memory (except the first SQ_PAGES + * reserved for the send buffer) for the receive + * ring buffer. + */ + ne2k->start_page = ne2k->sq.page + SQ_PAGES; + ne2k->stop_page = ne2k->sq.page + NE2K_SIZE / DP_PAGE; + + /* + * Initialization of the DP8390 following the mandatory procedure + * in reference manual ("DP8390D/NS32490D NIC Network Interface + * Controller", National Semiconductor, July 1995, Page 29). + */ + + /* Step 1: */ + pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_STP | CR_DM_ABORT); + + /* Step 2: */ + pio_write_8(ne2k->port + DP_DCR, DCR_WORDWIDE | DCR_8BYTES | DCR_BMS); + + /* Step 3: */ + pio_write_8(ne2k->port + DP_RBCR0, 0); + pio_write_8(ne2k->port + DP_RBCR1, 0); + + /* Step 4: */ + pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration); + + /* Step 5: */ + pio_write_8(ne2k->port + DP_TCR, TCR_INTERNAL); + + /* Step 6: */ + pio_write_8(ne2k->port + DP_BNRY, ne2k->start_page); + pio_write_8(ne2k->port + DP_PSTART, ne2k->start_page); + pio_write_8(ne2k->port + DP_PSTOP, ne2k->stop_page); + + /* Step 7: */ + pio_write_8(ne2k->port + DP_ISR, 0xff); + + /* Step 8: */ + pio_write_8(ne2k->port + DP_IMR, + IMR_PRXE | IMR_PTXE | IMR_RXEE | IMR_TXEE | IMR_OVWE | IMR_CNTE); + + /* Step 9: */ + pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_DM_ABORT | CR_STP); + + pio_write_8(ne2k->port + DP_PAR0, ne2k->mac.address[0]); + pio_write_8(ne2k->port + DP_PAR1, ne2k->mac.address[1]); + pio_write_8(ne2k->port + DP_PAR2, ne2k->mac.address[2]); + pio_write_8(ne2k->port + DP_PAR3, ne2k->mac.address[3]); + pio_write_8(ne2k->port + DP_PAR4, ne2k->mac.address[4]); + pio_write_8(ne2k->port + DP_PAR5, ne2k->mac.address[5]); + + pio_write_8(ne2k->port + DP_MAR0, 0); + pio_write_8(ne2k->port + DP_MAR1, 0); + pio_write_8(ne2k->port + DP_MAR2, 0); + pio_write_8(ne2k->port + DP_MAR3, 0); + pio_write_8(ne2k->port + DP_MAR4, 0); + pio_write_8(ne2k->port + DP_MAR5, 0); + pio_write_8(ne2k->port + DP_MAR6, 0); + pio_write_8(ne2k->port + DP_MAR7, 0); + + pio_write_8(ne2k->port + DP_CURR, ne2k->start_page + 1); + + /* Step 10: */ + pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STA); + + /* Step 11: */ + pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL); + + /* Reset counters by reading */ + pio_read_8(ne2k->port + DP_CNTR0); + pio_read_8(ne2k->port + DP_CNTR1); + pio_read_8(ne2k->port + DP_CNTR2); + + /* Finish the initialization */ + ne2k->up = true; + return EOK; +} + +/** Stop the network interface. + * + * @param[in,out] ne2k Network interface structure. + * + */ +void ne2k_down(ne2k_t *ne2k) +{ + if ((ne2k->probed) && (ne2k->up)) { + pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT); + ne2k_init(ne2k); + ne2k->up = false; + } +} + +static void ne2k_reset(ne2k_t *ne2k) +{ + unsigned int i; + + fibril_mutex_lock(&ne2k->sq_mutex); + + /* Stop the chip */ + pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT); + pio_write_8(ne2k->port + DP_RBCR0, 0); + pio_write_8(ne2k->port + DP_RBCR1, 0); + + for (i = 0; i < NE2K_RETRY; i++) { + if ((pio_read_8(ne2k->port + DP_ISR) & ISR_RST) != 0) + break; + } + + pio_write_8(ne2k->port + DP_TCR, TCR_1EXTERNAL | TCR_OFST); + pio_write_8(ne2k->port + DP_CR, CR_STA | CR_DM_ABORT); + pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL); + + /* Acknowledge the ISR_RDC (remote DMA) interrupt */ + for (i = 0; i < NE2K_RETRY; i++) { + if ((pio_read_8(ne2k->port + DP_ISR) & ISR_RDC) != 0) + break; + } + + uint8_t val = pio_read_8(ne2k->port + DP_ISR); + pio_write_8(ne2k->port + DP_ISR, val & ~ISR_RDC); + + /* + * Reset the transmit ring. If we were transmitting a frame, + * we pretend that the packet is processed. Higher layers will + * retransmit if the packet wasn't actually sent. + */ + ne2k->sq.dirty = false; + + fibril_mutex_unlock(&ne2k->sq_mutex); +} + +/** Send a frame. + * + * @param[in,out] ne2k Network interface structure. + * @param[in] packet Frame to be sent. + * + */ +void ne2k_send(nic_t *nic_data, packet_t *packet) +{ + ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data); + + assert(ne2k->probed); + assert(ne2k->up); + + fibril_mutex_lock(&ne2k->sq_mutex); + + while (ne2k->sq.dirty) { + fibril_condvar_wait(&ne2k->sq_cv, &ne2k->sq_mutex); + } + void *buf = packet_get_data(packet); + size_t size = packet_get_data_length(packet); + + if ((size < ETH_MIN_PACK_SIZE) || (size > ETH_MAX_PACK_SIZE_TAGGED)) { + fibril_mutex_unlock(&ne2k->sq_mutex); + return; + } + + /* Upload the frame to the ethernet card */ + ne2k_upload(ne2k, buf, ne2k->sq.page * DP_PAGE, size); + ne2k->sq.dirty = true; + ne2k->sq.size = size; + + /* Initialize the transfer */ + pio_write_8(ne2k->port + DP_TPSR, ne2k->sq.page); + pio_write_8(ne2k->port + DP_TBCR0, size & 0xff); + pio_write_8(ne2k->port + DP_TBCR1, (size >> 8) & 0xff); + pio_write_8(ne2k->port + DP_CR, CR_TXP | CR_STA); + fibril_mutex_unlock(&ne2k->sq_mutex); + + /* Relase packet */ + nic_release_packet(nic_data, packet); +} + +static nic_frame_t *ne2k_receive_frame(nic_t *nic_data, uint8_t page, + size_t length) +{ + ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data); + + nic_frame_t *frame = nic_alloc_frame(nic_data, length); + if (frame == NULL) + return NULL; + + void *buf = packet_suffix(frame->packet, length); + bzero(buf, length); + uint8_t last = page + length / DP_PAGE; + + if (last >= ne2k->stop_page) { + size_t left = (ne2k->stop_page - page) * DP_PAGE + - sizeof(recv_header_t); + ne2k_download(ne2k, buf, page * DP_PAGE + sizeof(recv_header_t), + left); + ne2k_download(ne2k, buf + left, ne2k->start_page * DP_PAGE, + length - left); + } else { + ne2k_download(ne2k, buf, page * DP_PAGE + sizeof(recv_header_t), + length); + } + return frame; +} + +static void ne2k_receive(nic_t *nic_data) +{ + ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data); + /* + * Allocate memory for the list of received frames. + * If the allocation fails here we still receive the + * frames from the network, but they will be lost. + */ + nic_frame_list_t *frames = nic_alloc_frame_list(); + size_t frames_count = 0; + + /* We may block sending in this loop - after so many received frames there + * must be some interrupt pending (for the frames not yet downloaded) and + * we will continue in its handler. */ + while (frames_count < 16) { + //TODO: isn't some locking necessary here? + uint8_t boundary = pio_read_8(ne2k->port + DP_BNRY) + 1; + + if (boundary == ne2k->stop_page) + boundary = ne2k->start_page; + + pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_STA); + uint8_t current = pio_read_8(ne2k->port + DP_CURR); + pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_STA); + if (current == boundary) + /* No more frames to process */ + break; + + recv_header_t header; + size_t size = sizeof(header); + size_t offset = boundary * DP_PAGE; + + /* Get the frame header */ + pio_write_8(ne2k->port + DP_RBCR0, size & 0xff); + pio_write_8(ne2k->port + DP_RBCR1, (size >> 8) & 0xff); + pio_write_8(ne2k->port + DP_RSAR0, offset & 0xff); + pio_write_8(ne2k->port + DP_RSAR1, (offset >> 8) & 0xff); + pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA); + + pio_read_buf_16(ne2k->data_port, (void *) &header, size); + + size_t length = + (((size_t) header.rbcl) | (((size_t) header.rbch) << 8)) - size; + uint8_t next = header.next; + + if ((length < ETH_MIN_PACK_SIZE) + || (length > ETH_MAX_PACK_SIZE_TAGGED)) { + next = current; + } else if ((header.next < ne2k->start_page) + || (header.next > ne2k->stop_page)) { + next = current; + } else if (header.status & RSR_FO) { + /* + * This is very serious, so we issue a warning and + * reset the buffers. + */ + ne2k->overruns++; + next = current; + } else if ((header.status & RSR_PRX) && (ne2k->up)) { + if (frames != NULL) { + nic_frame_t *frame = + ne2k_receive_frame(nic_data, boundary, length); + if (frame != NULL) { + nic_frame_list_append(frames, frame); + frames_count++; + } else { + break; + } + } else + break; + } + + /* + * Update the boundary pointer + * to the value of the page + * prior to the next packet to + * be processed. + */ + if (next == ne2k->start_page) + next = ne2k->stop_page - 1; + else + next--; + pio_write_8(ne2k->port + DP_BNRY, next); + } + nic_received_frame_list(nic_data, frames); +} + +void ne2k_interrupt(nic_t *nic_data, uint8_t isr, uint8_t tsr) +{ + ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data); + + if (isr & (ISR_PTX | ISR_TXE)) { + if (tsr & TSR_COL) { + nic_report_collisions(nic_data, + pio_read_8(ne2k->port + DP_NCR) & 15); + } + + if (tsr & TSR_PTX) { + // TODO: fix number of sent bytes (but how?) + nic_report_send_ok(nic_data, 1, 0); + } else if (tsr & TSR_ABT) { + nic_report_send_error(nic_data, NIC_SEC_ABORTED, 1); + } else if (tsr & TSR_CRS) { + nic_report_send_error(nic_data, NIC_SEC_CARRIER_LOST, 1); + } else if (tsr & TSR_FU) { + ne2k->underruns++; + // if (ne2k->underruns < NE2K_ERL) { + // } + } else if (tsr & TSR_CDH) { + nic_report_send_error(nic_data, NIC_SEC_HEARTBEAT, 1); + // if (nic_data->stats.send_heartbeat_errors < NE2K_ERL) { + // } + } else if (tsr & TSR_OWC) { + nic_report_send_error(nic_data, NIC_SEC_WINDOW_ERROR, 1); + } + + fibril_mutex_lock(&ne2k->sq_mutex); + if (ne2k->sq.dirty) { + /* Prepare the buffer for next packet */ + ne2k->sq.dirty = false; + ne2k->sq.size = 0; + + /* Signal a next frame to be sent */ + fibril_condvar_broadcast(&ne2k->sq_cv); + } else { + ne2k->misses++; + // if (ne2k->misses < NE2K_ERL) { + // } + } + fibril_mutex_unlock(&ne2k->sq_mutex); + } + + if (isr & ISR_CNT) { + unsigned int errors; + for (errors = pio_read_8(ne2k->port + DP_CNTR0); errors > 0; --errors) + nic_report_receive_error(nic_data, NIC_REC_CRC, 1); + for (errors = pio_read_8(ne2k->port + DP_CNTR1); errors > 0; --errors) + nic_report_receive_error(nic_data, NIC_REC_FRAME_ALIGNMENT, 1); + for (errors = pio_read_8(ne2k->port + DP_CNTR2); errors > 0; --errors) + nic_report_receive_error(nic_data, NIC_REC_MISSED, 1); + } + if (isr & ISR_PRX) { + ne2k_receive(nic_data); + } + if (isr & ISR_RST) { + /* + * The chip is stopped, and all arrived + * frames are delivered. + */ + ne2k_reset(ne2k); + } + + /* Unmask interrupts to be processed in the next round */ + pio_write_8(ne2k->port + DP_IMR, + IMR_PRXE | IMR_PTXE | IMR_RXEE | IMR_TXEE | IMR_OVWE | IMR_CNTE); +} + +void ne2k_set_accept_bcast(ne2k_t *ne2k, int accept) +{ + if (accept) + ne2k->receive_configuration |= RCR_AB; + else + ne2k->receive_configuration &= ~RCR_AB; + + pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration); +} + +void ne2k_set_accept_mcast(ne2k_t *ne2k, int accept) +{ + if (accept) + ne2k->receive_configuration |= RCR_AM; + else + ne2k->receive_configuration &= ~RCR_AM; + + pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration); +} + +void ne2k_set_promisc_phys(ne2k_t *ne2k, int promisc) +{ + if (promisc) + ne2k->receive_configuration |= RCR_PRO; + else + ne2k->receive_configuration &= ~RCR_PRO; + + pio_write_8(ne2k->port + DP_RCR, ne2k->receive_configuration); +} + +void ne2k_set_mcast_hash(ne2k_t *ne2k, uint64_t hash) +{ + /* Select Page 1 and stop all transfers */ + pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_DM_ABORT | CR_STP); + + pio_write_8(ne2k->port + DP_MAR0, (uint8_t) hash); + pio_write_8(ne2k->port + DP_MAR1, (uint8_t) (hash >> 8)); + pio_write_8(ne2k->port + DP_MAR2, (uint8_t) (hash >> 16)); + pio_write_8(ne2k->port + DP_MAR3, (uint8_t) (hash >> 24)); + pio_write_8(ne2k->port + DP_MAR4, (uint8_t) (hash >> 32)); + pio_write_8(ne2k->port + DP_MAR5, (uint8_t) (hash >> 40)); + pio_write_8(ne2k->port + DP_MAR6, (uint8_t) (hash >> 48)); + pio_write_8(ne2k->port + DP_MAR7, (uint8_t) (hash >> 56)); + + /* Select Page 0 and resume transfers */ + pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STA); +} + +/** @} + */ Index: uspace/drv/nic/ne2k/dp8390.h =================================================================== --- uspace/drv/nic/ne2k/dp8390.h (revision bd83012835a346d3b98fb0fa4aac917aa404a734) +++ uspace/drv/nic/ne2k/dp8390.h (revision bd83012835a346d3b98fb0fa4aac917aa404a734) @@ -0,0 +1,277 @@ +/* + * Copyright (c) 2009 Lukas Mejdrech + * Copyright (c) 2011 Martin Decky + * Copyright (c) 2011 Radim Vansa + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This code is based upon the NE2000 driver for MINIX, + * distributed according to a BSD-style license. + * + * Copyright (c) 1987, 1997, 2006 Vrije Universiteit + * Copyright (c) 1992, 1994 Philip Homburg + * Copyright (c) 1996 G. Falzoni + * + */ + +/** @addtogroup drv_ne2k + * @{ + */ + +/** @file + * DP8390 network interface definitions. + */ + +#ifndef __NET_NETIF_DP8390_H__ +#define __NET_NETIF_DP8390_H__ + +#include +#include +#include + +/** Input/output size */ +#define NE2K_IO_SIZE 0x0020 + +/* NE2000 implementation. */ + +/** NE2000 Data Register */ +#define NE2K_DATA 0x0010 + +/** NE2000 Reset register */ +#define NE2K_RESET 0x001f + +/** NE2000 data start */ +#define NE2K_START 0x4000 + +/** NE2000 data size */ +#define NE2K_SIZE 0x4000 + +/** NE2000 retry count */ +#define NE2K_RETRY 0x1000 + +/** NE2000 error messages rate limiting */ +#define NE2K_ERL 10 + +/** Minimum Ethernet packet size in bytes */ +#define ETH_MIN_PACK_SIZE 60 + +/** Maximum Ethernet packet size in bytes */ +#define ETH_MAX_PACK_SIZE_TAGGED 1518 + +/* National Semiconductor DP8390 Network Interface Controller. */ + +/** Page 0, for reading */ +#define DP_CR 0x00 /**< Command Register */ +#define DP_CLDA0 0x01 /**< Current Local DMA Address 0 */ +#define DP_CLDA1 0x02 /**< Current Local DMA Address 1 */ +#define DP_BNRY 0x03 /**< Boundary Pointer */ +#define DP_TSR 0x04 /**< Transmit Status Register */ +#define DP_NCR 0x05 /**< Number of Collisions Register */ +#define DP_FIFO 0x06 /**< FIFO */ +#define DP_ISR 0x07 /**< Interrupt Status Register */ +#define DP_CRDA0 0x08 /**< Current Remote DMA Address 0 */ +#define DP_CRDA1 0x09 /**< Current Remote DMA Address 1 */ +#define DP_RSR 0x0c /**< Receive Status Register */ +#define DP_CNTR0 0x0d /**< Tally Counter 0 */ +#define DP_CNTR1 0x0e /**< Tally Counter 1 */ +#define DP_CNTR2 0x0f /**< Tally Counter 2 */ + +/** Page 0, for writing */ +#define DP_PSTART 0x01 /**< Page Start Register*/ +#define DP_PSTOP 0x02 /**< Page Stop Register */ +#define DP_TPSR 0x04 /**< Transmit Page Start Register */ +#define DP_TBCR0 0x05 /**< Transmit Byte Count Register 0 */ +#define DP_TBCR1 0x06 /**< Transmit Byte Count Register 1 */ +#define DP_RSAR0 0x08 /**< Remote Start Address Register 0 */ +#define DP_RSAR1 0x09 /**< Remote Start Address Register 1 */ +#define DP_RBCR0 0x0a /**< Remote Byte Count Register 0 */ +#define DP_RBCR1 0x0b /**< Remote Byte Count Register 1 */ +#define DP_RCR 0x0c /**< Receive Configuration Register */ +#define DP_TCR 0x0d /**< Transmit Configuration Register */ +#define DP_DCR 0x0e /**< Data Configuration Register */ +#define DP_IMR 0x0f /**< Interrupt Mask Register */ + +/** Page 1, read/write */ +#define DP_PAR0 0x01 /**< Physical Address Register 0 */ +#define DP_PAR1 0x02 /**< Physical Address Register 1 */ +#define DP_PAR2 0x03 /**< Physical Address Register 2 */ +#define DP_PAR3 0x04 /**< Physical Address Register 3 */ +#define DP_PAR4 0x05 /**< Physical Address Register 4 */ +#define DP_PAR5 0x06 /**< Physical Address Register 5 */ +#define DP_CURR 0x07 /**< Current Page Register */ +#define DP_MAR0 0x08 /**< Multicast Address Register 0 */ +#define DP_MAR1 0x09 /**< Multicast Address Register 1 */ +#define DP_MAR2 0x0a /**< Multicast Address Register 2 */ +#define DP_MAR3 0x0b /**< Multicast Address Register 3 */ +#define DP_MAR4 0x0c /**< Multicast Address Register 4 */ +#define DP_MAR5 0x0d /**< Multicast Address Register 5 */ +#define DP_MAR6 0x0e /**< Multicast Address Register 6 */ +#define DP_MAR7 0x0f /**< Multicast Address Register 7 */ + +/* Bits in Command Register */ +#define CR_STP 0x01 /**< Stop (software reset) */ +#define CR_STA 0x02 /**< Start (activate NIC) */ +#define CR_TXP 0x04 /**< Transmit Packet */ +#define CR_DMA 0x38 /**< Mask for DMA control */ +#define CR_DM_NOP 0x00 /**< DMA: No Operation */ +#define CR_DM_RR 0x08 /**< DMA: Remote Read */ +#define CR_DM_RW 0x10 /**< DMA: Remote Write */ +#define CR_DM_SP 0x18 /**< DMA: Send Packet */ +#define CR_DM_ABORT 0x20 /**< DMA: Abort Remote DMA Operation */ +#define CR_PS 0xc0 /**< Mask for Page Select */ +#define CR_PS_P0 0x00 /**< Register Page 0 */ +#define CR_PS_P1 0x40 /**< Register Page 1 */ +#define CR_PS_P2 0x80 /**< Register Page 2 */ +#define CR_PS_T1 0xc0 /**< Test Mode Register Map */ + +/* Bits in Interrupt State Register */ +#define ISR_PRX 0x01 /**< Packet Received with no errors */ +#define ISR_PTX 0x02 /**< Packet Transmitted with no errors */ +#define ISR_RXE 0x04 /**< Receive Error */ +#define ISR_TXE 0x08 /**< Transmit Error */ +#define ISR_OVW 0x10 /**< Overwrite Warning */ +#define ISR_CNT 0x20 /**< Counter Overflow */ +#define ISR_RDC 0x40 /**< Remote DMA Complete */ +#define ISR_RST 0x80 /**< Reset Status */ + +/* Bits in Interrupt Mask Register */ +#define IMR_PRXE 0x01 /**< Packet Received Interrupt Enable */ +#define IMR_PTXE 0x02 /**< Packet Transmitted Interrupt Enable */ +#define IMR_RXEE 0x04 /**< Receive Error Interrupt Enable */ +#define IMR_TXEE 0x08 /**< Transmit Error Interrupt Enable */ +#define IMR_OVWE 0x10 /**< Overwrite Warning Interrupt Enable */ +#define IMR_CNTE 0x20 /**< Counter Overflow Interrupt Enable */ +#define IMR_RDCE 0x40 /**< DMA Complete Interrupt Enable */ + +/* Bits in Data Configuration Register */ +#define DCR_WTS 0x01 /**< Word Transfer Select */ +#define DCR_BYTEWIDE 0x00 /**< WTS: byte wide transfers */ +#define DCR_WORDWIDE 0x01 /**< WTS: word wide transfers */ +#define DCR_BOS 0x02 /**< Byte Order Select */ +#define DCR_LTLENDIAN 0x00 /**< BOS: Little Endian */ +#define DCR_BIGENDIAN 0x02 /**< BOS: Big Endian */ +#define DCR_LAS 0x04 /**< Long Address Select */ +#define DCR_BMS 0x08 /**< Burst Mode Select */ +#define DCR_AR 0x10 /**< Autoinitialize Remote */ +#define DCR_FTS 0x60 /**< Fifo Threshold Select */ +#define DCR_2BYTES 0x00 /**< 2 bytes */ +#define DCR_4BYTES 0x40 /**< 4 bytes */ +#define DCR_8BYTES 0x20 /**< 8 bytes */ +#define DCR_12BYTES 0x60 /**< 12 bytes */ + +/* Bits in Transmit Configuration Register */ +#define TCR_CRC 0x01 /**< Inhibit CRC */ +#define TCR_ELC 0x06 /**< Encoded Loopback Control */ +#define TCR_NORMAL 0x00 /**< ELC: Normal Operation */ +#define TCR_INTERNAL 0x02 /**< ELC: Internal Loopback */ +#define TCR_0EXTERNAL 0x04 /**< ELC: External Loopback LPBK=0 */ +#define TCR_1EXTERNAL 0x06 /**< ELC: External Loopback LPBK=1 */ +#define TCR_ATD 0x08 /**< Auto Transmit Disable */ +#define TCR_OFST 0x10 /**< Collision Offset Enable (be nice) */ + +/* Bits in Interrupt Status Register */ +#define TSR_PTX 0x01 /**< Packet Transmitted (without error) */ +#define TSR_DFR 0x02 /**< Transmit Deferred (reserved) */ +#define TSR_COL 0x04 /**< Transmit Collided */ +#define TSR_ABT 0x08 /**< Transmit Aborted */ +#define TSR_CRS 0x10 /**< Carrier Sense Lost */ +#define TSR_FU 0x20 /**< FIFO Underrun */ +#define TSR_CDH 0x40 /**< CD Heartbeat */ +#define TSR_OWC 0x80 /**< Out of Window Collision */ + +/* Bits in Receive Configuration Register */ +#define RCR_SEP 0x01 /**< Save Errored Packets */ +#define RCR_AR 0x02 /**< Accept Runt Packets */ +#define RCR_AB 0x04 /**< Accept Broadcast */ +#define RCR_AM 0x08 /**< Accept Multicast */ +#define RCR_PRO 0x10 /**< Physical Promiscuous */ +#define RCR_MON 0x20 /**< Monitor Mode */ + +/* Bits in Receive Status Register */ +#define RSR_PRX 0x01 /**< Packet Received Intact */ +#define RSR_CRC 0x02 /**< CRC Error */ +#define RSR_FAE 0x04 /**< Frame Alignment Error */ +#define RSR_FO 0x08 /**< FIFO Overrun */ +#define RSR_MPA 0x10 /**< Missed Packet */ +#define RSR_PHY 0x20 /**< Multicast Address Match */ +#define RSR_DIS 0x40 /**< Receiver Disabled */ +#define RSR_DFR 0x80 /**< In later manuals: Deferring */ + +typedef struct { + /* Device configuration */ + void *base_port; /**< Port assigned from ISA configuration **/ + void *port; + void *data_port; + int irq; + nic_address_t mac; + + uint8_t start_page; /**< Ring buffer start page */ + uint8_t stop_page; /**< Ring buffer stop page */ + + /* Send queue */ + struct { + bool dirty; /**< Buffer contains a packet */ + size_t size; /**< Packet size */ + uint8_t page; /**< Starting page of the buffer */ + } sq; + fibril_mutex_t sq_mutex; + fibril_condvar_t sq_cv; + + /* Driver run-time variables */ + bool probed; + bool up; + + /* Irq code with assigned addresses for this device */ + irq_code_t code; + + /* Copy of the receive configuration register */ + uint8_t receive_configuration; + + /* Device statistics */ + // TODO: shouldn't be these directly in device.h - nic_device_stats? + uint64_t misses; /**< Receive frame misses */ + uint64_t underruns; /**< FIFO underruns */ + uint64_t overruns; /**< FIFO overruns */ +} ne2k_t; + +extern int ne2k_probe(ne2k_t *); +extern int ne2k_up(ne2k_t *); +extern void ne2k_down(ne2k_t *); +extern void ne2k_send(nic_t *, packet_t *); +extern void ne2k_interrupt(nic_t *, uint8_t, uint8_t); +extern packet_t *ne2k_alloc_packet(nic_t *, size_t); + +extern void ne2k_set_accept_mcast(ne2k_t *, int); +extern void ne2k_set_accept_bcast(ne2k_t *, int); +extern void ne2k_set_promisc_phys(ne2k_t *, int); +extern void ne2k_set_mcast_hash(ne2k_t *, uint64_t); +extern void ne2k_set_physical_address(ne2k_t *, const nic_address_t *address); + +#endif + +/** @} + */ Index: uspace/drv/nic/ne2k/ne2k.c =================================================================== --- uspace/drv/nic/ne2k/ne2k.c (revision bd83012835a346d3b98fb0fa4aac917aa404a734) +++ uspace/drv/nic/ne2k/ne2k.c (revision bd83012835a346d3b98fb0fa4aac917aa404a734) @@ -0,0 +1,410 @@ +/* + * Copyright (c) 2011 Martin Decky + * Copyright (c) 2011 Radim Vansa + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @addtogroup drv_ne2k + * @brief Novell NE2000 NIC driver + * @{ + */ +/** + * @file + * @brief Bridge between NICF, DDF and business logic for the NIC + */ + +#include +#include +#include +#include +#include +#include "dp8390.h" + +#define NAME "ne2k" + +/** Return the ISR from the interrupt call. + * + * @param[in] call The interrupt call. + * + */ +#define IRQ_GET_ISR(call) ((int) IPC_GET_ARG2(call)) + +/** Return the TSR from the interrupt call. + * + * @param[in] call The interrupt call. + * + */ +#define IRQ_GET_TSR(call) ((int) IPC_GET_ARG3(call)) + +#define DRIVER_DATA(dev) ((nic_t *) ((dev)->driver_data)) +#define NE2K(device) ((ne2k_t *) nic_get_specific(DRIVER_DATA(device))) + +/** NE2000 kernel interrupt command sequence. + * + */ +static irq_cmd_t ne2k_cmds_prototype[] = { + { + /* Read Interrupt Status Register */ + .cmd = CMD_PIO_READ_8, + .addr = NULL, + .dstarg = 2 + }, + { + /* Mask supported interrupt causes */ + .cmd = CMD_BTEST, + .value = (ISR_PRX | ISR_PTX | ISR_RXE | ISR_TXE | ISR_OVW | + ISR_CNT | ISR_RDC), + .srcarg = 2, + .dstarg = 3, + }, + { + /* Predicate for accepting the interrupt */ + .cmd = CMD_PREDICATE, + .value = 4, + .srcarg = 3 + }, + { + /* + * Mask future interrupts via + * Interrupt Mask Register + */ + .cmd = CMD_PIO_WRITE_8, + .addr = NULL, + .value = 0 + }, + { + /* Acknowledge the current interrupt */ + .cmd = CMD_PIO_WRITE_A_8, + .addr = NULL, + .srcarg = 3 + }, + { + /* Read Transmit Status Register */ + .cmd = CMD_PIO_READ_8, + .addr = NULL, + .dstarg = 3 + }, + { + .cmd = CMD_ACCEPT + } +}; + +static void ne2k_interrupt_handler(ddf_dev_t *dev, ipc_callid_t iid, + ipc_call_t *call); + +static int ne2k_register_interrupt(nic_t *nic_data) +{ + ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data); + + if (ne2k->code.cmdcount == 0) { + irq_cmd_t *ne2k_cmds = malloc(sizeof(ne2k_cmds_prototype)); + if (ne2k_cmds == NULL) { + return ENOMEM; + } + memcpy(ne2k_cmds, ne2k_cmds_prototype, sizeof (ne2k_cmds_prototype)); + ne2k_cmds[0].addr = ne2k->port + DP_ISR; + ne2k_cmds[3].addr = ne2k->port + DP_IMR; + ne2k_cmds[4].addr = ne2k_cmds[0].addr; + ne2k_cmds[5].addr = ne2k->port + DP_TSR; + + ne2k->code.cmdcount = sizeof(ne2k_cmds_prototype) / sizeof(irq_cmd_t); + ne2k->code.cmds = ne2k_cmds; + } + + int rc = register_interrupt_handler(nic_get_ddf_dev(nic_data), + ne2k->irq, ne2k_interrupt_handler, &ne2k->code); + return rc; +} + +static ddf_dev_ops_t ne2k_dev_ops; + +static void ne2k_dev_cleanup(ddf_dev_t *dev) +{ + if (dev->driver_data != NULL) { + ne2k_t *ne2k = NE2K(dev); + if (ne2k) { + free(ne2k->code.cmds); + } + nic_unbind_and_destroy(dev); + } + if (dev->parent_sess != NULL) { + async_hangup(dev->parent_sess); + dev->parent_sess = NULL; + } +} + +static int ne2k_dev_init(nic_t *nic_data) +{ + /* Get HW resources */ + hw_res_list_parsed_t hw_res_parsed; + hw_res_list_parsed_init(&hw_res_parsed); + + int rc = nic_get_resources(nic_data, &hw_res_parsed); + + if (rc != EOK) + goto failed; + + if (hw_res_parsed.irqs.count == 0) { + rc = EINVAL; + goto failed; + } + + if (hw_res_parsed.io_ranges.count == 0) { + rc = EINVAL; + goto failed; + } + + if (hw_res_parsed.io_ranges.ranges[0].size < NE2K_IO_SIZE) { + rc = EINVAL; + goto failed; + } + + ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data); + ne2k->irq = hw_res_parsed.irqs.irqs[0]; + + ne2k->base_port = (void *) (uintptr_t) + hw_res_parsed.io_ranges.ranges[0].address; + + hw_res_list_parsed_clean(&hw_res_parsed); + + /* Enable port I/O */ + if (pio_enable(ne2k->base_port, NE2K_IO_SIZE, &ne2k->port) != EOK) + return EADDRNOTAVAIL; + + + ne2k->data_port = ne2k->port + NE2K_DATA; + ne2k->receive_configuration = RCR_AB | RCR_AM; + ne2k->probed = false; + ne2k->up = false; + + /* Find out whether the device is present. */ + if (ne2k_probe(ne2k) != EOK) + return ENOENT; + + ne2k->probed = true; + + rc = ne2k_register_interrupt(nic_data); + if (rc != EOK) + return EINVAL; + + return EOK; + +failed: + hw_res_list_parsed_clean(&hw_res_parsed); + return rc; +} + +void ne2k_interrupt_handler(ddf_dev_t *dev, ipc_callid_t iid, ipc_call_t *call) +{ + nic_t *nic_data = DRIVER_DATA(dev); + ne2k_interrupt(nic_data, IRQ_GET_ISR(*call), IRQ_GET_TSR(*call)); + + async_answer_0(iid, EOK); +} + +static int ne2k_on_activating(nic_t *nic_data) +{ + ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data); + + if (!ne2k->up) { + int rc = ne2k_up(ne2k); + if (rc != EOK) { + return rc; + } + + nic_enable_interrupt(nic_data, ne2k->irq); + } + return EOK; +} + +static int ne2k_on_stopping(nic_t *nic_data) +{ + ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data); + + nic_disable_interrupt(nic_data, ne2k->irq); + ne2k->receive_configuration = RCR_AB | RCR_AM; + ne2k_down(ne2k); + return EOK; +} + +static int ne2k_set_address(ddf_fun_t *fun, const nic_address_t *address) +{ + nic_t *nic_data = DRIVER_DATA(fun); + int rc = nic_report_address(nic_data, address); + if (rc != EOK) { + return EINVAL; + } + /* Note: some frame with previous physical address may slip to NIL here + * (for a moment the filtering is not exact), but ethernet should be OK with + * that. Some packet may also be lost, but this is not a problem. + */ + ne2k_set_physical_address((ne2k_t *) nic_get_specific(nic_data), address); + return EOK; +} + +static int ne2k_on_unicast_mode_change(nic_t *nic_data, + nic_unicast_mode_t new_mode, + const nic_address_t *address_list, size_t address_count) +{ + ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data); + switch (new_mode) { + case NIC_UNICAST_BLOCKED: + ne2k_set_promisc_phys(ne2k, false); + nic_report_hw_filtering(nic_data, 0, -1, -1); + return EOK; + case NIC_UNICAST_DEFAULT: + ne2k_set_promisc_phys(ne2k, false); + nic_report_hw_filtering(nic_data, 1, -1, -1); + return EOK; + case NIC_UNICAST_LIST: + ne2k_set_promisc_phys(ne2k, true); + nic_report_hw_filtering(nic_data, 0, -1, -1); + return EOK; + case NIC_UNICAST_PROMISC: + ne2k_set_promisc_phys(ne2k, true); + nic_report_hw_filtering(nic_data, 1, -1, -1); + return EOK; + default: + return ENOTSUP; + } +} + +static int ne2k_on_multicast_mode_change(nic_t *nic_data, + nic_multicast_mode_t new_mode, + const nic_address_t *address_list, size_t address_count) +{ + ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data); + switch (new_mode) { + case NIC_MULTICAST_BLOCKED: + ne2k_set_accept_mcast(ne2k, false); + nic_report_hw_filtering(nic_data, -1, 1, -1); + return EOK; + case NIC_MULTICAST_LIST: + ne2k_set_accept_mcast(ne2k, true); + ne2k_set_mcast_hash(ne2k, + nic_mcast_hash(address_list, address_count)); + nic_report_hw_filtering(nic_data, -1, 0, -1); + return EOK; + case NIC_MULTICAST_PROMISC: + ne2k_set_accept_mcast(ne2k, true); + ne2k_set_mcast_hash(ne2k, 0xFFFFFFFFFFFFFFFFllu); + nic_report_hw_filtering(nic_data, -1, 1, -1); + return EOK; + default: + return ENOTSUP; + } +} + +static int ne2k_on_broadcast_mode_change(nic_t *nic_data, + nic_broadcast_mode_t new_mode) +{ + ne2k_t *ne2k = (ne2k_t *) nic_get_specific(nic_data); + switch (new_mode) { + case NIC_BROADCAST_BLOCKED: + ne2k_set_accept_bcast(ne2k, false); + return EOK; + case NIC_BROADCAST_ACCEPTED: + ne2k_set_accept_bcast(ne2k, true); + return EOK; + default: + return ENOTSUP; + } +} + +static int ne2k_add_device(ddf_dev_t *dev) +{ + /* Allocate driver data for the device. */ + nic_t *nic_data = nic_create_and_bind(dev); + if (nic_data == NULL) + return ENOMEM; + + nic_set_write_packet_handler(nic_data, ne2k_send); + nic_set_state_change_handlers(nic_data, + ne2k_on_activating, NULL, ne2k_on_stopping); + nic_set_filtering_change_handlers(nic_data, + ne2k_on_unicast_mode_change, ne2k_on_multicast_mode_change, + ne2k_on_broadcast_mode_change, NULL, NULL); + + ne2k_t *ne2k = malloc(sizeof(ne2k_t)); + if (NULL != ne2k) { + memset(ne2k, 0, sizeof(ne2k_t)); + nic_set_specific(nic_data, ne2k); + } else { + nic_unbind_and_destroy(dev); + return ENOMEM; + } + + int rc = ne2k_dev_init(nic_data); + if (rc != EOK) { + ne2k_dev_cleanup(dev); + return rc; + } + + rc = nic_report_address(nic_data, &ne2k->mac); + if (rc != EOK) { + ne2k_dev_cleanup(dev); + return rc; + } + + rc = nic_register_as_ddf_fun(nic_data, &ne2k_dev_ops); + if (rc != EOK) { + ne2k_dev_cleanup(dev); + return rc; + } + + rc = nic_connect_to_services(nic_data); + if (rc != EOK) { + ne2k_dev_cleanup(dev); + return rc; + } + + return EOK; +} + +static nic_iface_t ne2k_nic_iface = { + .set_address = ne2k_set_address +}; + +static driver_ops_t ne2k_driver_ops = { + .add_device = ne2k_add_device +}; + +static driver_t ne2k_driver = { + .name = NAME, + .driver_ops = &ne2k_driver_ops +}; + +int main(int argc, char *argv[]) +{ + nic_driver_init(NAME); + nic_driver_implement(&ne2k_driver_ops, &ne2k_dev_ops, &ne2k_nic_iface); + + return ddf_driver_main(&ne2k_driver); +} + +/** @} + */ Index: uspace/drv/nic/ne2k/ne2k.ma =================================================================== --- uspace/drv/nic/ne2k/ne2k.ma (revision bd83012835a346d3b98fb0fa4aac917aa404a734) +++ uspace/drv/nic/ne2k/ne2k.ma (revision bd83012835a346d3b98fb0fa4aac917aa404a734) @@ -0,0 +1,1 @@ +10 isa/ne2k