Index: kernel/arch/abs32le/include/asm.h =================================================================== --- kernel/arch/abs32le/include/asm.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/abs32le/include/asm.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -38,10 +38,11 @@ #include #include - -static inline void asm_delay_loop(uint32_t usec) -{ -} - -static inline __attribute__((noreturn)) void cpu_halt(void) +#include + +NO_TRACE static inline void asm_delay_loop(uint32_t usec) +{ +} + +NO_TRACE static inline __attribute__((noreturn)) void cpu_halt(void) { /* On real hardware this should stop processing further @@ -53,5 +54,5 @@ } -static inline void cpu_sleep(void) +NO_TRACE static inline void cpu_sleep(void) { /* On real hardware this should put the CPU into low-power @@ -61,5 +62,5 @@ } -static inline void pio_write_8(ioport8_t *port, uint8_t val) +NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val) { } @@ -73,5 +74,5 @@ * */ -static inline void pio_write_16(ioport16_t *port, uint16_t val) +NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val) { } @@ -85,5 +86,5 @@ * */ -static inline void pio_write_32(ioport32_t *port, uint32_t val) +NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val) { } @@ -97,5 +98,5 @@ * */ -static inline uint8_t pio_read_8(ioport8_t *port) +NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port) { return 0; @@ -110,5 +111,5 @@ * */ -static inline uint16_t pio_read_16(ioport16_t *port) +NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port) { return 0; @@ -123,59 +124,72 @@ * */ -static inline uint32_t pio_read_32(ioport32_t *port) -{ - return 0; -} - -static inline ipl_t interrupts_enable(void) -{ - /* On real hardware this unconditionally enables preemption - by internal and external interrupts. - - The return value stores the previous interrupt level. */ - - return 0; -} - -static inline ipl_t interrupts_disable(void) -{ - /* On real hardware this disables preemption by the usual - set of internal and external interrupts. This does not - apply to special non-maskable interrupts and sychronous - CPU exceptions. - - The return value stores the previous interrupt level. */ - - return 0; -} - -static inline void interrupts_restore(ipl_t ipl) -{ - /* On real hardware this either enables or disables preemption - according to the interrupt level value from the argument. */ -} - -static inline ipl_t interrupts_read(void) -{ - /* On real hardware the return value stores the current interrupt - level. */ - - return 0; -} - -static inline bool interrupts_disabled(void) -{ - /* On real hardware the return value is true iff interrupts are - disabled. */ +NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port) +{ + return 0; +} + +NO_TRACE static inline ipl_t interrupts_enable(void) +{ + /* + * On real hardware this unconditionally enables preemption + * by internal and external interrupts. + * + * The return value stores the previous interrupt level. + */ + + return 0; +} + +NO_TRACE static inline ipl_t interrupts_disable(void) +{ + /* + * On real hardware this disables preemption by the usual + * set of internal and external interrupts. This does not + * apply to special non-maskable interrupts and sychronous + * CPU exceptions. + * + * The return value stores the previous interrupt level. + */ + + return 0; +} + +NO_TRACE static inline void interrupts_restore(ipl_t ipl) +{ + /* + * On real hardware this either enables or disables preemption + * according to the interrupt level value from the argument. + */ +} + +NO_TRACE static inline ipl_t interrupts_read(void) +{ + /* + * On real hardware the return value stores the current interrupt + * level. + */ + + return 0; +} + +NO_TRACE static inline bool interrupts_disabled(void) +{ + /* + * On real hardware the return value is true iff interrupts are + * disabled. + */ + return false; } -static inline uintptr_t get_stack_base(void) -{ - /* On real hardware this returns the address of the bottom - of the current CPU stack. The the_t structure is stored - on the bottom of stack and this is used to identify the - current CPU, current task, current thread and current - address space. */ +NO_TRACE static inline uintptr_t get_stack_base(void) +{ + /* + * On real hardware this returns the address of the bottom + * of the current CPU stack. The the_t structure is stored + * on the bottom of stack and this is used to identify the + * current CPU, current task, current thread and current + * address space. + */ return 0; Index: kernel/arch/abs32le/include/atomic.h =================================================================== --- kernel/arch/abs32le/include/atomic.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/abs32le/include/atomic.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -39,6 +39,12 @@ #include #include +#include +#include -static inline void atomic_inc(atomic_t *val) { +NO_TRACE ATOMIC static inline void atomic_inc(atomic_t *val) + WRITES(&val->count) + REQUIRES_EXTENT_MUTABLE(val) + REQUIRES(val->count < ATOMIC_COUNT_MAX) +{ /* On real hardware the increment has to be done as an atomic action. */ @@ -47,12 +53,19 @@ } -static inline void atomic_dec(atomic_t *val) { +NO_TRACE ATOMIC static inline void atomic_dec(atomic_t *val) + WRITES(&val->count) + REQUIRES_EXTENT_MUTABLE(val) + REQUIRES(val->count > ATOMIC_COUNT_MIN) +{ /* On real hardware the decrement has to be done as an atomic action. */ - val->count++; + val->count--; } -static inline atomic_count_t atomic_postinc(atomic_t *val) +NO_TRACE ATOMIC static inline atomic_count_t atomic_postinc(atomic_t *val) + WRITES(&val->count) + REQUIRES_EXTENT_MUTABLE(val) + REQUIRES(val->count < ATOMIC_COUNT_MAX) { /* On real hardware both the storing of the previous @@ -66,5 +79,8 @@ } -static inline atomic_count_t atomic_postdec(atomic_t *val) +NO_TRACE ATOMIC static inline atomic_count_t atomic_postdec(atomic_t *val) + WRITES(&val->count) + REQUIRES_EXTENT_MUTABLE(val) + REQUIRES(val->count > ATOMIC_COUNT_MIN) { /* On real hardware both the storing of the previous @@ -81,6 +97,12 @@ #define atomic_predec(val) (atomic_postdec(val) - 1) -static inline atomic_count_t test_and_set(atomic_t *val) +NO_TRACE ATOMIC static inline atomic_count_t test_and_set(atomic_t *val) + WRITES(&val->count) + REQUIRES_EXTENT_MUTABLE(val) { + /* On real hardware the retrieving of the original + value and storing 1 have to be done as a single + atomic action. */ + atomic_count_t prev = val->count; val->count = 1; @@ -88,5 +110,7 @@ } -static inline void atomic_lock_arch(atomic_t *val) +NO_TRACE static inline void atomic_lock_arch(atomic_t *val) + WRITES(&val->count) + REQUIRES_EXTENT_MUTABLE(val) { do { Index: kernel/arch/abs32le/include/cycle.h =================================================================== --- kernel/arch/abs32le/include/cycle.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/abs32le/include/cycle.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -36,5 +36,7 @@ #define KERN_abs32le_CYCLE_H_ -static inline uint64_t get_cycle(void) +#include + +NO_TRACE static inline uint64_t get_cycle(void) { return 0; Index: kernel/arch/abs32le/include/interrupt.h =================================================================== --- kernel/arch/abs32le/include/interrupt.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/abs32le/include/interrupt.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -37,4 +37,6 @@ #include +#include +#include #define IVT_ITEMS 0 @@ -53,5 +55,6 @@ } istate_t; -static inline int istate_from_uspace(istate_t *istate) +NO_TRACE static inline int istate_from_uspace(istate_t *istate) + REQUIRES_EXTENT_MUTABLE(istate) { /* On real hardware this checks whether the interrupted @@ -61,5 +64,7 @@ } -static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) +NO_TRACE static inline void istate_set_retaddr(istate_t *istate, + uintptr_t retaddr) + WRITES(&istate->ip) { /* On real hardware this sets the instruction pointer. */ @@ -68,5 +73,6 @@ } -static inline unative_t istate_get_pc(istate_t *istate) +NO_TRACE static inline unative_t istate_get_pc(istate_t *istate) + REQUIRES_EXTENT_MUTABLE(istate) { /* On real hardware this returns the instruction pointer. */ @@ -75,5 +81,6 @@ } -static inline unative_t istate_get_fp(istate_t *istate) +NO_TRACE static inline unative_t istate_get_fp(istate_t *istate) + REQUIRES_EXTENT_MUTABLE(istate) { /* On real hardware this returns the frame pointer. */ Index: kernel/arch/abs32le/include/mm/page.h =================================================================== --- kernel/arch/abs32le/include/mm/page.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/abs32le/include/mm/page.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -37,4 +37,5 @@ #include +#include #define PAGE_WIDTH FRAME_WIDTH @@ -139,18 +140,23 @@ } __attribute__((packed)) pte_t; -static inline unsigned int get_pt_flags(pte_t *pt, size_t i) +NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i) + REQUIRES_ARRAY_MUTABLE(pt, PTL0_ENTRIES_ARCH) { pte_t *p = &pt[i]; - return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT | - (!p->present) << PAGE_PRESENT_SHIFT | - p->uaccessible << PAGE_USER_SHIFT | - 1 << PAGE_READ_SHIFT | - p->writeable << PAGE_WRITE_SHIFT | - 1 << PAGE_EXEC_SHIFT | - p->global << PAGE_GLOBAL_SHIFT); + return ( + ((unsigned int) (!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT) | + ((unsigned int) (!p->present) << PAGE_PRESENT_SHIFT) | + ((unsigned int) p->uaccessible << PAGE_USER_SHIFT) | + (1 << PAGE_READ_SHIFT) | + ((unsigned int) p->writeable << PAGE_WRITE_SHIFT) | + (1 << PAGE_EXEC_SHIFT) | + ((unsigned int) p->global << PAGE_GLOBAL_SHIFT) + ); } -static inline void set_pt_flags(pte_t *pt, size_t i, int flags) +NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags) + WRITES(ARRAY_RANGE(pt, PTL0_ENTRIES_ARCH)) + REQUIRES_ARRAY_MUTABLE(pt, PTL0_ENTRIES_ARCH) { pte_t *p = &pt[i]; Index: kernel/arch/abs32le/include/types.h =================================================================== --- kernel/arch/abs32le/include/types.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/abs32le/include/types.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -35,4 +35,7 @@ #ifndef KERN_abs32le_TYPES_H_ #define KERN_abs32le_TYPES_H_ + +#define ATOMIC_COUNT_MIN UINT32_MIN +#define ATOMIC_COUNT_MAX UINT32_MAX typedef uint32_t size_t; Index: kernel/arch/abs32le/src/abs32le.c =================================================================== --- kernel/arch/abs32le/src/abs32le.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/abs32le/src/abs32le.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -114,13 +114,7 @@ } -void panic_printf(const char *fmt, ...) +void istate_decode(istate_t *istate) { - va_list args; - - va_start(args, fmt); - vprintf(fmt, args); - va_end(args); - - halt(); + (void) istate; } @@ -157,4 +151,8 @@ } +void early_putchar(wchar_t ch) +{ +} + /** @} */ Index: kernel/arch/amd64/Makefile.inc =================================================================== --- kernel/arch/amd64/Makefile.inc (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/Makefile.inc (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -33,5 +33,5 @@ FPU_NO_CFLAGS = -mno-sse -mno-sse2 -CMN1 = -m64 -mcmodel=kernel -mno-red-zone -fno-unwind-tables -fno-omit-frame-pointer +CMN1 = -m64 -mcmodel=large -mno-red-zone -fno-unwind-tables -fno-omit-frame-pointer GCC_CFLAGS += $(CMN1) ICC_CFLAGS += $(CMN1) @@ -71,5 +71,5 @@ arch/$(KARCH)/src/mm/page.c \ arch/$(KARCH)/src/mm/tlb.c \ - arch/$(KARCH)/src/asm_utils.S \ + arch/$(KARCH)/src/asm.S \ arch/$(KARCH)/src/cpu/cpu.c \ arch/$(KARCH)/src/proc/scheduler.c \ Index: kernel/arch/amd64/_link.ld.in =================================================================== --- kernel/arch/amd64/_link.ld.in (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/_link.ld.in (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -1,10 +1,10 @@ /** AMD64 linker script - * + * * umapped section: - * kernel text - * kernel data + * kernel text + * kernel data * mapped section: - * kernel text - * kernel data + * kernel text + * kernel data */ @@ -17,5 +17,5 @@ *(K_TEXT_START); unmapped_ktext_end = .; - + unmapped_kdata_start = .; *(K_DATA_START); @@ -23,13 +23,13 @@ unmapped_kdata_end = .; } - + .mapped (PA2KA(BOOT_OFFSET)+SIZEOF(.unmapped)) : AT (SIZEOF(.unmapped)) { ktext_start = .; *(.text); ktext_end = .; - + kdata_start = .; - *(.data); /* initialized data */ - *(.rodata*); /* string literals */ + *(.data); /* initialized data */ + *(.rodata*); /* string literals */ hardcoded_load_address = .; QUAD(PA2KA(BOOT_OFFSET)); @@ -42,26 +42,25 @@ hardcoded_unmapped_kdata_size = .; QUAD(unmapped_kdata_end - unmapped_kdata_start); - *(COMMON); /* global variables */ - + *(COMMON); /* global variables */ + . = ALIGN(8); symbol_table = .; - *(symtab.*); /* Symbol table, must be LAST symbol!*/ - - *(.bss); /* uninitialized static variables */ - + *(symtab.*); /* Symbol table, must be LAST symbol!*/ + + *(.bss); /* uninitialized static variables */ + kdata_end = .; } - + /DISCARD/ : { *(*); } -#ifdef CONFIG_SMP +#ifdef CONFIG_SMP _hardcoded_unmapped_size = (unmapped_ktext_end - unmapped_ktext_start) + (unmapped_kdata_end - unmapped_kdata_start); ap_boot = unmapped_ap_boot - BOOT_OFFSET + AP_BOOT_OFFSET; ap_gdtr = unmapped_ap_gdtr - BOOT_OFFSET + AP_BOOT_OFFSET; protected_ap_gdtr = PA2KA(ap_gdtr); - #endif /* CONFIG_SMP */ - + } Index: kernel/arch/amd64/include/arch.h =================================================================== --- kernel/arch/amd64/include/arch.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/include/arch.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup amd64 +/** @addtogroup amd64 * @{ */ Index: kernel/arch/amd64/include/asm.h =================================================================== --- kernel/arch/amd64/include/asm.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/include/asm.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -39,7 +39,5 @@ #include #include - -extern void asm_delay_loop(uint32_t t); -extern void asm_fake_loop(uint32_t t); +#include /** Return base address of current stack. @@ -50,5 +48,5 @@ * */ -static inline uintptr_t get_stack_base(void) +NO_TRACE static inline uintptr_t get_stack_base(void) { uintptr_t v; @@ -57,5 +55,5 @@ "andq %%rsp, %[v]\n" : [v] "=r" (v) - : "0" (~((uint64_t) STACK_SIZE-1)) + : "0" (~((uint64_t) STACK_SIZE - 1)) ); @@ -63,10 +61,12 @@ } -static inline void cpu_sleep(void) -{ - asm volatile ("hlt\n"); -} - -static inline void __attribute__((noreturn)) cpu_halt(void) +NO_TRACE static inline void cpu_sleep(void) +{ + asm volatile ( + "hlt\n" + ); +} + +NO_TRACE static inline void __attribute__((noreturn)) cpu_halt(void) { while (true) { @@ -77,5 +77,4 @@ } - /** Byte from port * @@ -86,5 +85,5 @@ * */ -static inline uint8_t pio_read_8(ioport8_t *port) +NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port) { uint8_t val; @@ -107,5 +106,5 @@ * */ -static inline uint16_t pio_read_16(ioport16_t *port) +NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port) { uint16_t val; @@ -128,5 +127,5 @@ * */ -static inline uint32_t pio_read_32(ioport32_t *port) +NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port) { uint32_t val; @@ -149,9 +148,10 @@ * */ -static inline void pio_write_8(ioport8_t *port, uint8_t val) +NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val) { asm volatile ( "outb %b[val], %w[port]\n" - :: [val] "a" (val), [port] "d" (port) + :: [val] "a" (val), + [port] "d" (port) ); } @@ -165,9 +165,10 @@ * */ -static inline void pio_write_16(ioport16_t *port, uint16_t val) +NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val) { asm volatile ( "outw %w[val], %w[port]\n" - :: [val] "a" (val), [port] "d" (port) + :: [val] "a" (val), + [port] "d" (port) ); } @@ -181,16 +182,19 @@ * */ -static inline void pio_write_32(ioport32_t *port, uint32_t val) +NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val) { asm volatile ( "outl %[val], %w[port]\n" - :: [val] "a" (val), [port] "d" (port) + :: [val] "a" (val), + [port] "d" (port) ); } /** Swap Hidden part of GS register with visible one */ -static inline void swapgs(void) -{ - asm volatile("swapgs"); +NO_TRACE static inline void swapgs(void) +{ + asm volatile ( + "swapgs" + ); } @@ -203,5 +207,5 @@ * */ -static inline ipl_t interrupts_enable(void) { +NO_TRACE static inline ipl_t interrupts_enable(void) { ipl_t v; @@ -224,5 +228,5 @@ * */ -static inline ipl_t interrupts_disable(void) { +NO_TRACE static inline ipl_t interrupts_disable(void) { ipl_t v; @@ -244,5 +248,5 @@ * */ -static inline void interrupts_restore(ipl_t ipl) { +NO_TRACE static inline void interrupts_restore(ipl_t ipl) { asm volatile ( "pushq %[ipl]\n" @@ -259,5 +263,5 @@ * */ -static inline ipl_t interrupts_read(void) { +NO_TRACE static inline ipl_t interrupts_read(void) { ipl_t v; @@ -276,5 +280,5 @@ * */ -static inline bool interrupts_disabled(void) +NO_TRACE static inline bool interrupts_disabled(void) { ipl_t v; @@ -289,7 +293,6 @@ } - /** Write to MSR */ -static inline void write_msr(uint32_t msr, uint64_t value) +NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value) { asm volatile ( @@ -301,5 +304,5 @@ } -static inline unative_t read_msr(uint32_t msr) +NO_TRACE static inline unative_t read_msr(uint32_t msr) { uint32_t ax, dx; @@ -314,5 +317,4 @@ } - /** Enable local APIC * @@ -320,5 +322,5 @@ * */ -static inline void enable_l_apic_in_msr() +NO_TRACE static inline void enable_l_apic_in_msr() { asm volatile ( @@ -328,5 +330,5 @@ "orl $(0xfee00000),%%eax\n" "wrmsr\n" - ::: "%eax","%ecx","%edx" + ::: "%eax", "%ecx", "%edx" ); } @@ -337,5 +339,5 @@ * */ -static inline void invlpg(uintptr_t addr) +NO_TRACE static inline void invlpg(uintptr_t addr) { asm volatile ( @@ -350,5 +352,5 @@ * */ -static inline void gdtr_load(ptr_16_64_t *gdtr_reg) +NO_TRACE static inline void gdtr_load(ptr_16_64_t *gdtr_reg) { asm volatile ( @@ -363,5 +365,5 @@ * */ -static inline void gdtr_store(ptr_16_64_t *gdtr_reg) +NO_TRACE static inline void gdtr_store(ptr_16_64_t *gdtr_reg) { asm volatile ( @@ -376,5 +378,5 @@ * */ -static inline void idtr_load(ptr_16_64_t *idtr_reg) +NO_TRACE static inline void idtr_load(ptr_16_64_t *idtr_reg) { asm volatile ( @@ -388,5 +390,5 @@ * */ -static inline void tr_load(uint16_t sel) +NO_TRACE static inline void tr_load(uint16_t sel) { asm volatile ( @@ -396,5 +398,5 @@ } -#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ +#define GEN_READ_REG(reg) NO_TRACE static inline unative_t read_ ##reg (void) \ { \ unative_t res; \ @@ -406,5 +408,5 @@ } -#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ +#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (unative_t regn) \ { \ asm volatile ( \ @@ -436,4 +438,7 @@ extern void interrupt_handlers(void); +extern void asm_delay_loop(uint32_t); +extern void asm_fake_loop(uint32_t); + #endif Index: kernel/arch/amd64/include/atomic.h =================================================================== --- kernel/arch/amd64/include/atomic.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/include/atomic.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -39,6 +39,7 @@ #include #include +#include -static inline void atomic_inc(atomic_t *val) +NO_TRACE static inline void atomic_inc(atomic_t *val) { #ifdef CONFIG_SMP @@ -55,5 +56,5 @@ } -static inline void atomic_dec(atomic_t *val) +NO_TRACE static inline void atomic_dec(atomic_t *val) { #ifdef CONFIG_SMP @@ -70,5 +71,5 @@ } -static inline atomic_count_t atomic_postinc(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val) { atomic_count_t r = 1; @@ -83,5 +84,5 @@ } -static inline atomic_count_t atomic_postdec(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val) { atomic_count_t r = -1; @@ -99,5 +100,5 @@ #define atomic_predec(val) (atomic_postdec(val) - 1) -static inline atomic_count_t test_and_set(atomic_t *val) +NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val) { atomic_count_t v = 1; @@ -113,5 +114,5 @@ /** amd64 specific fast spinlock */ -static inline void atomic_lock_arch(atomic_t *val) +NO_TRACE static inline void atomic_lock_arch(atomic_t *val) { atomic_count_t tmp; @@ -120,13 +121,13 @@ asm volatile ( "0:\n" - "pause\n" - "mov %[count], %[tmp]\n" - "testq %[tmp], %[tmp]\n" - "jnz 0b\n" /* lightweight looping on locked spinlock */ + " pause\n" + " mov %[count], %[tmp]\n" + " testq %[tmp], %[tmp]\n" + " jnz 0b\n" /* lightweight looping on locked spinlock */ - "incq %[tmp]\n" /* now use the atomic operation */ - "xchgq %[count], %[tmp]\n" - "testq %[tmp], %[tmp]\n" - "jnz 0b\n" + " incq %[tmp]\n" /* now use the atomic operation */ + " xchgq %[count], %[tmp]\n" + " testq %[tmp], %[tmp]\n" + " jnz 0b\n" : [count] "+m" (val->count), [tmp] "=&r" (tmp) Index: kernel/arch/amd64/include/boot/boot.h =================================================================== --- kernel/arch/amd64/include/boot/boot.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/include/boot/boot.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup amd64 +/** @addtogroup amd64 * @{ */ @@ -36,10 +36,10 @@ #define KERN_amd64_BOOT_H_ -#define BOOT_OFFSET 0x108000 -#define AP_BOOT_OFFSET 0x8000 -#define BOOT_STACK_SIZE 0x400 +#define BOOT_OFFSET 0x108000 +#define AP_BOOT_OFFSET 0x008000 +#define BOOT_STACK_SIZE 0x000400 -#define MULTIBOOT_HEADER_MAGIC 0x1BADB002 -#define MULTIBOOT_HEADER_FLAGS 0x00010003 +#define MULTIBOOT_HEADER_MAGIC 0x1BADB002 +#define MULTIBOOT_HEADER_FLAGS 0x00010003 #ifndef __ASM__ Index: kernel/arch/amd64/include/context.h =================================================================== --- kernel/arch/amd64/include/context.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/include/context.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -59,16 +59,16 @@ */ typedef struct { - uintptr_t sp; - uintptr_t pc; - - uint64_t rbx; - uint64_t rbp; - - uint64_t r12; - uint64_t r13; - uint64_t r14; - uint64_t r15; - - ipl_t ipl; + uintptr_t sp; + uintptr_t pc; + + uint64_t rbx; + uint64_t rbp; + + uint64_t r12; + uint64_t r13; + uint64_t r14; + uint64_t r15; + + ipl_t ipl; } __attribute__ ((packed)) context_t; Index: kernel/arch/amd64/include/cycle.h =================================================================== --- kernel/arch/amd64/include/cycle.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/include/cycle.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -36,5 +36,7 @@ #define KERN_amd64_CYCLE_H_ -static inline uint64_t get_cycle(void) +#include + +NO_TRACE static inline uint64_t get_cycle(void) { uint32_t lower; Index: kernel/arch/amd64/include/elf.h =================================================================== --- kernel/arch/amd64/include/elf.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/include/elf.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup amd64 +/** @addtogroup amd64 * @{ */ @@ -36,7 +36,7 @@ #define KERN_amd64_ELF_H_ -#define ELF_MACHINE EM_X86_64 -#define ELF_DATA_ENCODING ELFDATA2LSB -#define ELF_CLASS ELFCLASS64 +#define ELF_MACHINE EM_X86_64 +#define ELF_DATA_ENCODING ELFDATA2LSB +#define ELF_CLASS ELFCLASS64 #endif Index: kernel/arch/amd64/include/faddr.h =================================================================== --- kernel/arch/amd64/include/faddr.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/include/faddr.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup amd64 +/** @addtogroup amd64 * @{ */ @@ -38,5 +38,5 @@ #include -#define FADDR(fptr) ((uintptr_t) (fptr)) +#define FADDR(fptr) ((uintptr_t) (fptr)) #endif Index: kernel/arch/amd64/include/interrupt.h =================================================================== --- kernel/arch/amd64/include/interrupt.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/include/interrupt.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -38,24 +38,25 @@ #include #include +#include -#define IVT_ITEMS IDT_ITEMS -#define IVT_FIRST 0 +#define IVT_ITEMS IDT_ITEMS +#define IVT_FIRST 0 -#define EXC_COUNT 32 -#define IRQ_COUNT 16 +#define EXC_COUNT 32 +#define IRQ_COUNT 16 -#define IVT_EXCBASE 0 -#define IVT_IRQBASE (IVT_EXCBASE + EXC_COUNT) -#define IVT_FREEBASE (IVT_IRQBASE + IRQ_COUNT) +#define IVT_EXCBASE 0 +#define IVT_IRQBASE (IVT_EXCBASE + EXC_COUNT) +#define IVT_FREEBASE (IVT_IRQBASE + IRQ_COUNT) -#define IRQ_CLK 0 -#define IRQ_KBD 1 -#define IRQ_PIC1 2 -#define IRQ_PIC_SPUR 7 -#define IRQ_MOUSE 12 -#define IRQ_DP8390 9 +#define IRQ_CLK 0 +#define IRQ_KBD 1 +#define IRQ_PIC1 2 +#define IRQ_PIC_SPUR 7 +#define IRQ_MOUSE 12 +#define IRQ_DP8390 9 -/* this one must have four least significant bits set to ones */ -#define VECTOR_APIC_SPUR (IVT_ITEMS - 1) +/* This one must have four least significant bits set to ones */ +#define VECTOR_APIC_SPUR (IVT_ITEMS - 1) #if (((VECTOR_APIC_SPUR + 1) % 16) || VECTOR_APIC_SPUR >= IVT_ITEMS) @@ -63,10 +64,10 @@ #endif -#define VECTOR_DEBUG 1 -#define VECTOR_CLK (IVT_IRQBASE + IRQ_CLK) -#define VECTOR_PIC_SPUR (IVT_IRQBASE + IRQ_PIC_SPUR) -#define VECTOR_SYSCALL IVT_FREEBASE -#define VECTOR_TLB_SHOOTDOWN_IPI (IVT_FREEBASE + 1) -#define VECTOR_DEBUG_IPI (IVT_FREEBASE + 2) +#define VECTOR_DEBUG 1 +#define VECTOR_CLK (IVT_IRQBASE + IRQ_CLK) +#define VECTOR_PIC_SPUR (IVT_IRQBASE + IRQ_PIC_SPUR) +#define VECTOR_SYSCALL IVT_FREEBASE +#define VECTOR_TLB_SHOOTDOWN_IPI (IVT_FREEBASE + 1) +#define VECTOR_DEBUG_IPI (IVT_FREEBASE + 2) /** This is passed to interrupt handlers */ @@ -86,37 +87,36 @@ uint64_t cs; uint64_t rflags; - uint64_t stack[]; /* Additional data on stack */ + uint64_t stack[]; /* Additional data on stack */ } istate_t; /** Return true if exception happened while in userspace */ -static inline int istate_from_uspace(istate_t *istate) +NO_TRACE static inline int istate_from_uspace(istate_t *istate) { return !(istate->rip & 0x8000000000000000); } -static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) +NO_TRACE static inline void istate_set_retaddr(istate_t *istate, + uintptr_t retaddr) { istate->rip = retaddr; } -static inline unative_t istate_get_pc(istate_t *istate) + +NO_TRACE static inline unative_t istate_get_pc(istate_t *istate) { return istate->rip; } -static inline unative_t istate_get_fp(istate_t *istate) + +NO_TRACE static inline unative_t istate_get_fp(istate_t *istate) { return istate->rbp; } -extern void (* disable_irqs_function)(uint16_t irqmask); -extern void (* enable_irqs_function)(uint16_t irqmask); +extern void (* disable_irqs_function)(uint16_t); +extern void (* enable_irqs_function)(uint16_t); extern void (* eoi_function)(void); -extern void decode_istate(int n, istate_t *istate); extern void interrupt_init(void); -extern void trap_virtual_enable_irqs(uint16_t irqmask); -extern void trap_virtual_disable_irqs(uint16_t irqmask); - -/* AMD64 - specific page handler */ -extern void ident_page_fault(unsigned int, istate_t *); +extern void trap_virtual_enable_irqs(uint16_t); +extern void trap_virtual_disable_irqs(uint16_t); #endif Index: kernel/arch/amd64/include/mm/as.h =================================================================== --- kernel/arch/amd64/include/mm/as.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/include/mm/as.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup amd64mm +/** @addtogroup amd64mm * @{ */ @@ -36,16 +36,18 @@ #define KERN_amd64_AS_H_ -#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0 +#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0 -#define KERNEL_ADDRESS_SPACE_START_ARCH (unsigned long) 0xffff800000000000 -#define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffff80000000 -#define USER_ADDRESS_SPACE_START_ARCH (unsigned long) 0x0000000000000000 -#define USER_ADDRESS_SPACE_END_ARCH (unsigned long) 0x00007fffffffffff +#define KERNEL_ADDRESS_SPACE_START_ARCH (unsigned long) 0xffff800000000000 +#define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffffffffffff -#define USTACK_ADDRESS_ARCH (USER_ADDRESS_SPACE_END_ARCH-(PAGE_SIZE-1)) +#define USER_ADDRESS_SPACE_START_ARCH (unsigned long) 0x0000000000000000 +#define USER_ADDRESS_SPACE_END_ARCH (unsigned long) 0x00007fffffffffff -#define as_constructor_arch(as, flags) (as != as) -#define as_destructor_arch(as) (as != as) -#define as_create_arch(as, flags) (as != as) +#define USTACK_ADDRESS_ARCH (USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1)) + +#define as_constructor_arch(as, flags) (as != as) +#define as_destructor_arch(as) (as != as) +#define as_create_arch(as, flags) (as != as) + #define as_install_arch(as) #define as_deinstall_arch(as) Index: kernel/arch/amd64/include/mm/frame.h =================================================================== --- kernel/arch/amd64/include/mm/frame.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/include/mm/frame.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -36,16 +36,18 @@ #define KERN_amd64_FRAME_H_ -#ifndef __ASM__ -#include -#endif /* __ASM__ */ - #define FRAME_WIDTH 12 /* 4K */ #define FRAME_SIZE (1 << FRAME_WIDTH) +#ifdef KERNEL #ifndef __ASM__ + +#include + extern uintptr_t last_frame; extern void frame_arch_init(void); extern void physmem_print(void); + #endif /* __ASM__ */ +#endif /* KERNEL */ #endif Index: kernel/arch/amd64/include/mm/page.h =================================================================== --- kernel/arch/amd64/include/mm/page.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/include/mm/page.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -35,12 +35,9 @@ /** Paging on AMD64 * - * The space is divided in positive numbers - userspace and - * negative numbers - kernel space. The 'negative' space starting - * with 0xffff800000000000 and ending with 0xffffffff80000000 - * (-2GB) is identically mapped physical memory. The area - * (0xffffffff80000000 ... 0xffffffffffffffff is again identically - * mapped first 2GB. - * - * ATTENTION - PA2KA(KA2PA(x)) != x if 'x' is in kernel + * The space is divided in positive numbers (uspace) and + * negative numbers (kernel). The 'negative' space starting + * with 0xffff800000000000 and ending with 0xffffffffffffffff + * is identically mapped physical memory. + * */ @@ -49,48 +46,40 @@ #include - -#define PAGE_WIDTH FRAME_WIDTH -#define PAGE_SIZE FRAME_SIZE +#include + +#define PAGE_WIDTH FRAME_WIDTH +#define PAGE_SIZE FRAME_SIZE #ifdef KERNEL #ifndef __ASM__ -# include -# include -# include - -static inline uintptr_t ka2pa(uintptr_t x) -{ - if (x > 0xffffffff80000000) - return x - 0xffffffff80000000; - else - return x - 0xffff800000000000; -} - -# define KA2PA(x) ka2pa((uintptr_t) x) -# define PA2KA_CODE(x) (((uintptr_t) (x)) + 0xffffffff80000000) -# define PA2KA(x) (((uintptr_t) (x)) + 0xffff800000000000) -#else -# define KA2PA(x) ((x) - 0xffffffff80000000) -# define PA2KA(x) ((x) + 0xffffffff80000000) -#endif + +#define KA2PA(x) (((uintptr_t) (x)) - 0xffff800000000000) +#define PA2KA(x) (((uintptr_t) (x)) + 0xffff800000000000) + +#else /* __ASM__ */ + +#define KA2PA(x) ((x) - 0xffff800000000000) +#define PA2KA(x) ((x) + 0xffff800000000000) + +#endif /* __ASM__ */ /* Number of entries in each level. */ -#define PTL0_ENTRIES_ARCH 512 -#define PTL1_ENTRIES_ARCH 512 -#define PTL2_ENTRIES_ARCH 512 -#define PTL3_ENTRIES_ARCH 512 +#define PTL0_ENTRIES_ARCH 512 +#define PTL1_ENTRIES_ARCH 512 +#define PTL2_ENTRIES_ARCH 512 +#define PTL3_ENTRIES_ARCH 512 /* Page table sizes for each level. */ -#define PTL0_SIZE_ARCH ONE_FRAME -#define PTL1_SIZE_ARCH ONE_FRAME -#define PTL2_SIZE_ARCH ONE_FRAME -#define PTL3_SIZE_ARCH ONE_FRAME +#define PTL0_SIZE_ARCH ONE_FRAME +#define PTL1_SIZE_ARCH ONE_FRAME +#define PTL2_SIZE_ARCH ONE_FRAME +#define PTL3_SIZE_ARCH ONE_FRAME /* Macros calculating indices into page tables in each level. */ -#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 39) & 0x1ff) -#define PTL1_INDEX_ARCH(vaddr) (((vaddr) >> 30) & 0x1ff) -#define PTL2_INDEX_ARCH(vaddr) (((vaddr) >> 21) & 0x1ff) -#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x1ff) +#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 39) & 0x1ff) +#define PTL1_INDEX_ARCH(vaddr) (((vaddr) >> 30) & 0x1ff) +#define PTL2_INDEX_ARCH(vaddr) (((vaddr) >> 21) & 0x1ff) +#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x1ff) /* Get PTE address accessors for each level. */ @@ -156,4 +145,8 @@ #ifndef __ASM__ +#include +#include +#include + /* Page fault error codes. */ @@ -161,39 +154,39 @@ * page. */ -#define PFERR_CODE_P (1 << 0) +#define PFERR_CODE_P (1 << 0) /** When bit on this position is 1, the page fault was caused by a write. */ -#define PFERR_CODE_RW (1 << 1) +#define PFERR_CODE_RW (1 << 1) /** When bit on this position is 1, the page fault was caused in user mode. */ -#define PFERR_CODE_US (1 << 2) +#define PFERR_CODE_US (1 << 2) /** When bit on this position is 1, a reserved bit was set in page directory. */ -#define PFERR_CODE_RSVD (1 << 3) +#define PFERR_CODE_RSVD (1 << 3) /** When bit on this position os 1, the page fault was caused during instruction * fecth. */ -#define PFERR_CODE_ID (1 << 4) +#define PFERR_CODE_ID (1 << 4) /** Page Table Entry. */ typedef struct { - unsigned present : 1; - unsigned writeable : 1; - unsigned uaccessible : 1; - unsigned page_write_through : 1; - unsigned page_cache_disable : 1; - unsigned accessed : 1; - unsigned dirty : 1; - unsigned unused: 1; - unsigned global : 1; - unsigned soft_valid : 1; /**< Valid content even if present bit is cleared. */ - unsigned avl : 2; - unsigned addr_12_31 : 30; - unsigned addr_32_51 : 21; - unsigned no_execute : 1; + unsigned int present : 1; + unsigned int writeable : 1; + unsigned int uaccessible : 1; + unsigned int page_write_through : 1; + unsigned int page_cache_disable : 1; + unsigned int accessed : 1; + unsigned int dirty : 1; + unsigned int unused: 1; + unsigned int global : 1; + unsigned int soft_valid : 1; /**< Valid content even if present bit is cleared. */ + unsigned int avl : 2; + unsigned int addr_12_31 : 30; + unsigned int addr_32_51 : 21; + unsigned int no_execute : 1; } __attribute__ ((packed)) pte_t; -static inline unsigned int get_pt_flags(pte_t *pt, size_t i) +NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i) { pte_t *p = &pt[i]; @@ -208,13 +201,13 @@ } -static inline void set_pt_addr(pte_t *pt, size_t i, uintptr_t a) +NO_TRACE static inline void set_pt_addr(pte_t *pt, size_t i, uintptr_t a) { pte_t *p = &pt[i]; - + p->addr_12_31 = (a >> 12) & 0xfffff; p->addr_32_51 = a >> 32; } -static inline void set_pt_flags(pte_t *pt, size_t i, int flags) +NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags) { pte_t *p = &pt[i]; Index: kernel/arch/amd64/include/mm/ptl.h =================================================================== --- kernel/arch/amd64/include/mm/ptl.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/include/mm/ptl.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup amd64mm +/** @addtogroup amd64mm * @{ */ @@ -36,12 +36,12 @@ #define KERN_amd64_PTL_H_ -#define PTL_NO_EXEC (1<<63) -#define PTL_ACCESSED (1<<5) -#define PTL_CACHE_DISABLE (1<<4) -#define PTL_CACHE_THROUGH (1<<3) -#define PTL_USER (1<<2) -#define PTL_WRITABLE (1<<1) -#define PTL_PRESENT 1 -#define PTL_2MB_PAGE (1<<7) +#define PTL_NO_EXEC (1 << 63) +#define PTL_ACCESSED (1 << 5) +#define PTL_CACHE_DISABLE (1 << 4) +#define PTL_CACHE_THROUGH (1 << 3) +#define PTL_USER (1 << 2) +#define PTL_WRITABLE (1 << 1) +#define PTL_PRESENT 1 +#define PTL_2MB_PAGE (1 << 7) Index: kernel/arch/amd64/include/mm/tlb.h =================================================================== --- kernel/arch/amd64/include/mm/tlb.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/include/mm/tlb.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup amd64mm +/** @addtogroup amd64mm * @{ */ Index: kernel/arch/amd64/include/pm.h =================================================================== --- kernel/arch/amd64/include/pm.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/include/pm.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -71,5 +71,5 @@ #define PL_USER 3 -#define AR_PRESENT ( 1 << 7) +#define AR_PRESENT (1 << 7) #define AR_DATA (2 << 3) #define AR_CODE (3 << 3) Index: kernel/arch/amd64/include/proc/thread.h =================================================================== --- kernel/arch/amd64/include/proc/thread.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/include/proc/thread.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -37,11 +37,11 @@ /* CAUTION: keep these in sync with low level assembly code in syscall_entry */ -#define SYSCALL_USTACK_RSP 0 -#define SYSCALL_KSTACK_RSP 1 +#define SYSCALL_USTACK_RSP 0 +#define SYSCALL_KSTACK_RSP 1 typedef struct { unative_t tls; /** User and kernel RSP for syscalls. */ - uint64_t syscall_rsp[2]; + uint64_t syscall_rsp[2]; } thread_arch_t; Index: kernel/arch/amd64/include/types.h =================================================================== --- kernel/arch/amd64/include/types.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/include/types.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -50,9 +50,9 @@ } fncptr_t; -/**< Formats for uintptr_t, size_t */ +/* Formats for uintptr_t, size_t */ #define PRIp "llx" #define PRIs "llu" -/**< Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */ +/* Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */ #define PRId8 "d" #define PRId16 "d" Index: kernel/arch/amd64/src/amd64.c =================================================================== --- kernel/arch/amd64/src/amd64.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/src/amd64.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -122,5 +122,5 @@ /* Enable FPU */ cpu_setup_fpu(); - + /* Initialize segmentation */ pm_init(); @@ -132,5 +132,5 @@ /* Disable alignment check */ clean_AM_flag(); - + if (config.cpu_active == 1) { interrupt_init(); @@ -260,4 +260,5 @@ THREAD->arch.tls = addr; write_msr(AMD_MSR_FS, addr); + return 0; } Index: kernel/arch/amd64/src/asm.S =================================================================== --- kernel/arch/amd64/src/asm.S (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) +++ kernel/arch/amd64/src/asm.S (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -0,0 +1,489 @@ +/* + * Copyright (c) 2005 Ondrej Palkovsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#define IREGISTER_SPACE 80 + +#define IOFFSET_RAX 0x00 +#define IOFFSET_RCX 0x08 +#define IOFFSET_RDX 0x10 +#define IOFFSET_RSI 0x18 +#define IOFFSET_RDI 0x20 +#define IOFFSET_R8 0x28 +#define IOFFSET_R9 0x30 +#define IOFFSET_R10 0x38 +#define IOFFSET_R11 0x40 +#define IOFFSET_RBP 0x48 + +/** + * Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int + * has no error word and 1 means interrupt with error word + * + */ +#define ERROR_WORD_INTERRUPT_LIST 0x00027D00 + +#include +#include + +.text +.global interrupt_handlers +.global syscall_entry +.global cpuid +.global has_cpuid +.global read_efer_flag +.global set_efer_flag +.global memsetb +.global memsetw +.global memcpy +.global memcpy_from_uspace +.global memcpy_to_uspace +.global memcpy_from_uspace_failover_address +.global memcpy_to_uspace_failover_address +.global early_putchar + +/* Wrapper for generic memsetb */ +memsetb: + jmp _memsetb + +/* Wrapper for generic memsetw */ +memsetw: + jmp _memsetw + +#define MEMCPY_DST %rdi +#define MEMCPY_SRC %rsi +#define MEMCPY_SIZE %rdx + +/** + * Copy memory from/to userspace. + * + * This is almost conventional memcpy(). + * The difference is that there is a failover part + * to where control is returned from a page fault if + * the page fault occurs during copy_from_uspace() + * or copy_to_uspace(). + * + * @param MEMCPY_DST Destination address. + * @param MEMCPY_SRC Source address. + * @param MEMCPY_SIZE Number of bytes to copy. + * + * @retrun MEMCPY_DST on success, 0 on failure. + * + */ +memcpy: +memcpy_from_uspace: +memcpy_to_uspace: + movq MEMCPY_DST, %rax + + movq MEMCPY_SIZE, %rcx + shrq $3, %rcx /* size / 8 */ + + rep movsq /* copy as much as possible word by word */ + + movq MEMCPY_SIZE, %rcx + andq $7, %rcx /* size % 8 */ + jz 0f + + rep movsb /* copy the rest byte by byte */ + + 0: + ret /* return MEMCPY_SRC, success */ + +memcpy_from_uspace_failover_address: +memcpy_to_uspace_failover_address: + xorq %rax, %rax /* return 0, failure */ + ret + +/** Determine CPUID support +* +* @return 0 in EAX if CPUID is not support, 1 if supported. +* +*/ +has_cpuid: + /* Load RFLAGS */ + pushfq + popq %rax + movq %rax, %rdx + + /* Flip the ID bit */ + btcl $21, %edx + + /* Store RFLAGS */ + pushq %rdx + popfq + pushfq + + /* Get the ID bit again */ + popq %rdx + andl $(1 << 21), %eax + andl $(1 << 21), %edx + + /* 0 if not supported, 1 if supported */ + xorl %edx, %eax + ret + +cpuid: + /* Preserve %rbx across function calls */ + movq %rbx, %r10 + + /* Load the command into %eax */ + movl %edi, %eax + + cpuid + movl %eax, 0(%rsi) + movl %ebx, 4(%rsi) + movl %ecx, 8(%rsi) + movl %edx, 12(%rsi) + + movq %r10, %rbx + ret + +set_efer_flag: + movq $0xc0000080, %rcx + rdmsr + btsl %edi, %eax + wrmsr + ret + +read_efer_flag: + movq $0xc0000080, %rcx + rdmsr + ret + +/** Push all volatile general purpose registers on stack + * + */ +.macro save_all_gpr + movq %rax, IOFFSET_RAX(%rsp) + movq %rcx, IOFFSET_RCX(%rsp) + movq %rdx, IOFFSET_RDX(%rsp) + movq %rsi, IOFFSET_RSI(%rsp) + movq %rdi, IOFFSET_RDI(%rsp) + movq %r8, IOFFSET_R8(%rsp) + movq %r9, IOFFSET_R9(%rsp) + movq %r10, IOFFSET_R10(%rsp) + movq %r11, IOFFSET_R11(%rsp) + movq %rbp, IOFFSET_RBP(%rsp) +.endm + +.macro restore_all_gpr + movq IOFFSET_RAX(%rsp), %rax + movq IOFFSET_RCX(%rsp), %rcx + movq IOFFSET_RDX(%rsp), %rdx + movq IOFFSET_RSI(%rsp), %rsi + movq IOFFSET_RDI(%rsp), %rdi + movq IOFFSET_R8(%rsp), %r8 + movq IOFFSET_R9(%rsp), %r9 + movq IOFFSET_R10(%rsp), %r10 + movq IOFFSET_R11(%rsp), %r11 + movq IOFFSET_RBP(%rsp), %rbp +.endm + +#define INTERRUPT_ALIGN 128 + +/** Declare interrupt handlers + * + * Declare interrupt handlers for n interrupt + * vectors starting at vector i. + * + * The handlers call exc_dispatch(). + * + */ +.macro handler i n + + /* + * Choose between version with error code and version without error + * code. Both versions have to be of the same size. amd64 assembly is, + * however, a little bit tricky. For instance, subq $0x80, %rsp and + * subq $0x78, %rsp can result in two instructions with different + * op-code lengths. + * Therefore we align the interrupt handlers. + */ + + .iflt \i-32 + .if (1 << \i) & ERROR_WORD_INTERRUPT_LIST + /* + * Version with error word. + */ + subq $IREGISTER_SPACE, %rsp + .else + /* + * Version without error word, + */ + subq $(IREGISTER_SPACE + 8), %rsp + .endif + .else + /* + * Version without error word, + */ + subq $(IREGISTER_SPACE + 8), %rsp + .endif + + save_all_gpr + cld + + /* + * Stop stack traces here if we came from userspace. + */ + movq %cs, %rax + xorq %rdx, %rdx + cmpq %rax, IREGISTER_SPACE+16(%rsp) + cmovneq %rdx, %rbp + + movq $(\i), %rdi /* %rdi - first argument */ + movq %rsp, %rsi /* %rsi - pointer to istate */ + + /* Call exc_dispatch(i, istate) */ + call exc_dispatch + + restore_all_gpr + + /* $8 = Skip error word */ + addq $(IREGISTER_SPACE + 8), %rsp + iretq + + .align INTERRUPT_ALIGN + .if (\n - \i) - 1 + handler "(\i + 1)", \n + .endif +.endm + +.align INTERRUPT_ALIGN +interrupt_handlers: + h_start: + handler 0 IDT_ITEMS + h_end: + +/** Low-level syscall handler + * + * Registers on entry: + * + * @param %rcx Userspace return address. + * @param %r11 Userspace RLFAGS. + * + * @param %rax Syscall number. + * @param %rdi 1st syscall argument. + * @param %rsi 2nd syscall argument. + * @param %rdx 3rd syscall argument. + * @param %r10 4th syscall argument. Used instead of RCX because + * the SYSCALL instruction clobbers it. + * @param %r8 5th syscall argument. + * @param %r9 6th syscall argument. + * + * @return Return value is in %rax. + * + */ +syscall_entry: + /* Switch to hidden %gs */ + swapgs + + /* + * %gs:0 Scratch space for this thread's user RSP + * %gs:8 Address to be used as this thread's kernel RSP + */ + + movq %rsp, %gs:0 /* save this thread's user RSP */ + movq %gs:8, %rsp /* set this thread's kernel RSP */ + + /* Switch back to remain consistent */ + swapgs + sti + + pushq %rcx + pushq %r11 + pushq %rbp + + xorq %rbp, %rbp /* stop the stack traces here */ + + /* Copy the 4th argument where it is expected */ + movq %r10, %rcx + pushq %rax + + call syscall_handler + + addq $8, %rsp + + popq %rbp + popq %r11 + popq %rcx + + cli + swapgs + + /* Restore the user RSP */ + movq %gs:0, %rsp + swapgs + + sysretq + +/** Print Unicode character to EGA display. + * + * If CONFIG_EGA is undefined or CONFIG_FB is defined + * then this function does nothing. + * + * Since the EGA can only display Extended ASCII (usually + * ISO Latin 1) characters, some of the Unicode characters + * can be displayed in a wrong way. Only newline and backspace + * are interpreted, all other characters (even unprintable) are + * printed verbatim. + * + * @param %rdi Unicode character to be printed. + * + */ +early_putchar: + +#if ((defined(CONFIG_EGA)) && (!defined(CONFIG_FB))) + + /* Prologue, save preserved registers */ + pushq %rbp + movq %rsp, %rbp + pushq %rbx + + movq %rdi, %rsi + movq $(PA2KA(0xb8000)), %rdi /* base of EGA text mode memory */ + xorq %rax, %rax + + /* Read bits 8 - 15 of the cursor address */ + movw $0x3d4, %dx + movb $0xe, %al + outb %al, %dx + + movw $0x3d5, %dx + inb %dx, %al + shl $8, %ax + + /* Read bits 0 - 7 of the cursor address */ + movw $0x3d4, %dx + movb $0xf, %al + outb %al, %dx + + movw $0x3d5, %dx + inb %dx, %al + + /* Sanity check for the cursor on screen */ + cmp $2000, %ax + jb early_putchar_cursor_ok + + movw $1998, %ax + + early_putchar_cursor_ok: + + movw %ax, %bx + shl $1, %rax + addq %rax, %rdi + + movq %rsi, %rax + + cmp $0x0a, %al + jne early_putchar_backspace + + /* Interpret newline */ + + movw %bx, %ax /* %bx -> %dx:%ax */ + xorw %dx, %dx + + movw $80, %cx + idivw %cx, %ax /* %dx = %bx % 80 */ + + /* %bx <- %bx + 80 - (%bx % 80) */ + addw %cx, %bx + subw %dx, %bx + + jmp early_putchar_skip + + early_putchar_backspace: + + cmp $0x08, %al + jne early_putchar_print + + /* Interpret backspace */ + + cmp $0x0000, %bx + je early_putchar_skip + + dec %bx + jmp early_putchar_skip + + early_putchar_print: + + /* Print character */ + + movb $0x0e, %ah /* black background, yellow foreground */ + stosw + inc %bx + + early_putchar_skip: + + /* Sanity check for the cursor on the last line */ + cmp $2000, %bx + jb early_putchar_no_scroll + + /* Scroll the screen (24 rows) */ + movq $(PA2KA(0xb80a0)), %rsi + movq $(PA2KA(0xb8000)), %rdi + movq $480, %rcx + rep movsq + + /* Clear the 24th row */ + xorq %rax, %rax + movq $20, %rcx + rep stosq + + /* Go to row 24 */ + movw $1920, %bx + + early_putchar_no_scroll: + + /* Write bits 8 - 15 of the cursor address */ + movw $0x3d4, %dx + movb $0xe, %al + outb %al, %dx + + movw $0x3d5, %dx + movb %bh, %al + outb %al, %dx + + /* Write bits 0 - 7 of the cursor address */ + movw $0x3d4, %dx + movb $0xf, %al + outb %al, %dx + + movw $0x3d5, %dx + movb %bl, %al + outb %al, %dx + + /* Epilogue, restore preserved registers */ + popq %rbx + leave + +#endif + + ret + +.data +.global interrupt_handler_size + +interrupt_handler_size: .quad (h_end - h_start) / IDT_ITEMS Index: kernel/arch/amd64/src/asm_utils.S =================================================================== --- kernel/arch/amd64/src/asm_utils.S (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ (revision ) @@ -1,308 +1,0 @@ -# -# Copyright (c) 2005 Ondrej Palkovsky -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -#define IREGISTER_SPACE 80 - -#define IOFFSET_RAX 0x0 -#define IOFFSET_RCX 0x8 -#define IOFFSET_RDX 0x10 -#define IOFFSET_RSI 0x18 -#define IOFFSET_RDI 0x20 -#define IOFFSET_R8 0x28 -#define IOFFSET_R9 0x30 -#define IOFFSET_R10 0x38 -#define IOFFSET_R11 0x40 -#define IOFFSET_RBP 0x48 - -# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word -# and 1 means interrupt with error word -#define ERROR_WORD_INTERRUPT_LIST 0x00027D00 - -#include -#include - -.text -.global interrupt_handlers -.global syscall_entry -.global panic_printf - -panic_printf: - movq $halt, (%rsp) - jmp printf - -.global cpuid -.global has_cpuid -.global read_efer_flag -.global set_efer_flag -.global memsetb -.global memsetw -.global memcpy -.global memcpy_from_uspace -.global memcpy_to_uspace -.global memcpy_from_uspace_failover_address -.global memcpy_to_uspace_failover_address - -# Wrapper for generic memsetb -memsetb: - jmp _memsetb - -# Wrapper for generic memsetw -memsetw: - jmp _memsetw - -#define MEMCPY_DST %rdi -#define MEMCPY_SRC %rsi -#define MEMCPY_SIZE %rdx - -/** - * Copy memory from/to userspace. - * - * This is almost conventional memcpy(). - * The difference is that there is a failover part - * to where control is returned from a page fault if - * the page fault occurs during copy_from_uspace() - * or copy_to_uspace(). - * - * @param MEMCPY_DST Destination address. - * @param MEMCPY_SRC Source address. - * @param MEMCPY_SIZE Number of bytes to copy. - * - * @retrun MEMCPY_DST on success, 0 on failure. - */ -memcpy: -memcpy_from_uspace: -memcpy_to_uspace: - movq MEMCPY_DST, %rax - - movq MEMCPY_SIZE, %rcx - shrq $3, %rcx /* size / 8 */ - - rep movsq /* copy as much as possible word by word */ - - movq MEMCPY_SIZE, %rcx - andq $7, %rcx /* size % 8 */ - jz 0f - - rep movsb /* copy the rest byte by byte */ - -0: - ret /* return MEMCPY_SRC, success */ - -memcpy_from_uspace_failover_address: -memcpy_to_uspace_failover_address: - xorq %rax, %rax /* return 0, failure */ - ret - -## Determine CPUID support -# -# Return 0 in EAX if CPUID is not support, 1 if supported. -# -has_cpuid: - pushfq # store flags - popq %rax # read flags - movq %rax,%rdx # copy flags - btcl $21,%edx # swap the ID bit - pushq %rdx - popfq # propagate the change into flags - pushfq - popq %rdx # read flags - andl $(1<<21),%eax # interested only in ID bit - andl $(1<<21),%edx - xorl %edx,%eax # 0 if not supported, 1 if supported - ret - -cpuid: - movq %rbx, %r10 # we have to preserve rbx across function calls - - movl %edi,%eax # load the command into %eax - - cpuid - movl %eax,0(%rsi) - movl %ebx,4(%rsi) - movl %ecx,8(%rsi) - movl %edx,12(%rsi) - - movq %r10, %rbx - ret - -set_efer_flag: - movq $0xc0000080, %rcx - rdmsr - btsl %edi, %eax - wrmsr - ret - -read_efer_flag: - movq $0xc0000080, %rcx - rdmsr - ret - -# Push all volatile general purpose registers on stack -.macro save_all_gpr - movq %rax, IOFFSET_RAX(%rsp) - movq %rcx, IOFFSET_RCX(%rsp) - movq %rdx, IOFFSET_RDX(%rsp) - movq %rsi, IOFFSET_RSI(%rsp) - movq %rdi, IOFFSET_RDI(%rsp) - movq %r8, IOFFSET_R8(%rsp) - movq %r9, IOFFSET_R9(%rsp) - movq %r10, IOFFSET_R10(%rsp) - movq %r11, IOFFSET_R11(%rsp) - movq %rbp, IOFFSET_RBP(%rsp) -.endm - -.macro restore_all_gpr - movq IOFFSET_RAX(%rsp), %rax - movq IOFFSET_RCX(%rsp), %rcx - movq IOFFSET_RDX(%rsp), %rdx - movq IOFFSET_RSI(%rsp), %rsi - movq IOFFSET_RDI(%rsp), %rdi - movq IOFFSET_R8(%rsp), %r8 - movq IOFFSET_R9(%rsp), %r9 - movq IOFFSET_R10(%rsp), %r10 - movq IOFFSET_R11(%rsp), %r11 - movq IOFFSET_RBP(%rsp), %rbp -.endm - -#define INTERRUPT_ALIGN 128 - -## Declare interrupt handlers -# -# Declare interrupt handlers for n interrupt -# vectors starting at vector i. -# -# The handlers call exc_dispatch(). -# -.macro handler i n - - /* - * Choose between version with error code and version without error - * code. Both versions have to be of the same size. amd64 assembly is, - * however, a little bit tricky. For instance, subq $0x80, %rsp and - * subq $0x78, %rsp can result in two instructions with different - * op-code lengths. - * Therefore we align the interrupt handlers. - */ - - .iflt \i-32 - .if (1 << \i) & ERROR_WORD_INTERRUPT_LIST - /* - * Version with error word. - */ - subq $IREGISTER_SPACE, %rsp - .else - /* - * Version without error word, - */ - subq $(IREGISTER_SPACE+8), %rsp - .endif - .else - /* - * Version without error word, - */ - subq $(IREGISTER_SPACE+8), %rsp - .endif - - save_all_gpr - cld - - # Stop stack traces here - xorq %rbp, %rbp - - movq $(\i), %rdi # %rdi - first parameter - movq %rsp, %rsi # %rsi - pointer to istate - call exc_dispatch # exc_dispatch(i, istate) - - restore_all_gpr - # $8 = Skip error word - addq $(IREGISTER_SPACE+8), %rsp - iretq - - .align INTERRUPT_ALIGN - .if (\n-\i)-1 - handler "(\i+1)",\n - .endif -.endm - -.align INTERRUPT_ALIGN -interrupt_handlers: -h_start: - handler 0 IDT_ITEMS -h_end: - -## Low-level syscall handler -# -# Registers on entry: -# -# @param rcx Userspace return address. -# @param r11 Userspace RLFAGS. -# -# @param rax Syscall number. -# @param rdi 1st syscall argument. -# @param rsi 2nd syscall argument. -# @param rdx 3rd syscall argument. -# @param r10 4th syscall argument. Used instead of RCX because the -# SYSCALL instruction clobbers it. -# @param r8 5th syscall argument. -# @param r9 6th syscall argument. -# -# @return Return value is in rax. -# -syscall_entry: - swapgs # Switch to hidden gs - # - # %gs:0 Scratch space for this thread's user RSP - # %gs:8 Address to be used as this thread's kernel RSP - # - movq %rsp, %gs:0 # Save this thread's user RSP - movq %gs:8, %rsp # Set this thread's kernel RSP - swapgs # Switch back to remain consistent - sti - - pushq %rcx - pushq %r11 - - movq %r10, %rcx # Copy the 4th argument where it is expected - pushq %rax - call syscall_handler - addq $8, %rsp - - popq %r11 - popq %rcx - - cli - swapgs - movq %gs:0, %rsp # Restore the user RSP - swapgs - - sysretq - -.data -.global interrupt_handler_size - -interrupt_handler_size: .quad (h_end-h_start)/IDT_ITEMS Index: kernel/arch/amd64/src/boot/boot.S =================================================================== --- kernel/arch/amd64/src/boot/boot.S (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/src/boot/boot.S (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -1,35 +1,35 @@ -# -# Copyright (c) 2005 Ondrej Palkovsky -# Copyright (c) 2006 Martin Decky -# Copyright (c) 2008 Jakub Jermar -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# +/* + * Copyright (c) 2005 Ondrej Palkovsky + * Copyright (c) 2006 Martin Decky + * Copyright (c) 2008 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ #include #include -#include +#include #include #include @@ -37,9 +37,30 @@ #include -#define START_STACK (BOOT_OFFSET - BOOT_STACK_SIZE) +#define START_STACK (BOOT_OFFSET - BOOT_STACK_SIZE) .section K_TEXT_START, "ax" .code32 + +.macro pm_error msg + movl \msg, %esi + jmp pm_error_halt +.endm + +.macro pm_status msg +#ifdef CONFIG_EGA + pushl %esi + movl \msg, %esi + call pm_early_puts + popl %esi +#endif +.endm + +.macro pm2_status msg +#ifndef CONFIG_FB + pm_status \msg +#endif +.endm + .align 4 .global multiboot_image_start @@ -47,5 +68,5 @@ .long MULTIBOOT_HEADER_MAGIC .long MULTIBOOT_HEADER_FLAGS - .long -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS) # checksum + .long -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS) /* checksum */ .long multiboot_header .long unmapped_ktext_start @@ -56,17 +77,21 @@ multiboot_image_start: cld - movl $START_STACK, %esp # initialize stack pointer - lgdtl bootstrap_gdtr # initialize Global Descriptor Table register - + + /* Initialize stack pointer */ + movl $START_STACK, %esp + + /* Initialize Global Descriptor Table register */ + lgdtl bootstrap_gdtr + + /* Kernel data + stack */ movw $gdtselector(KDATA_DES), %cx movw %cx, %es - movw %cx, %ds # kernel data + stack + movw %cx, %ds movw %cx, %ss - # - # Simics seems to remove hidden part of GS on entering user mode - # when _visible_ part of GS does not point to user-mode segment. - # - + /* + * Simics seems to remove hidden part of GS on entering user mode + * when _visible_ part of GS does not point to user-mode segment. + */ movw $gdtselector(UDATA_DES), %cx movw %cx, %fs @@ -76,11 +101,9 @@ multiboot_meeting_point: - movl %eax, grub_eax # save parameters from GRUB + /* Save GRUB arguments */ + movl %eax, grub_eax movl %ebx, grub_ebx - # - # Protected 32-bit. We want to reuse the code-seg descriptor, - # the Default operand size must not be 1 when entering long mode. - # + pm_status $status_prot movl $(INTEL_CPUID_EXTENDED), %eax @@ -89,6 +112,5 @@ ja extended_cpuid_supported - movl $extended_cpuid_msg, %esi - jmp error_halt + pm_error $err_extended_cpuid extended_cpuid_supported: @@ -99,6 +121,5 @@ jc long_mode_supported - movl $long_mode_msg, %esi - jmp error_halt + pm_error $err_long_mode long_mode_supported: @@ -107,6 +128,5 @@ jc noexecute_supported - movl $noexecute_msg, %esi - jmp error_halt + pm_error $err_noexecute noexecute_supported: @@ -117,6 +137,5 @@ jc fx_supported - movl $fx_msg, %esi - jmp error_halt + pm_error $err_fx fx_supported: @@ -125,15 +144,21 @@ jc sse2_supported - movl $sse2_msg, %esi - jmp error_halt + pm_error $err_sse2 sse2_supported: - + #include "vesa_prot.inc" - - # - # Enable 64-bit page translation entries - CR4.PAE = 1. - # Paging is not enabled until after long mode is enabled. - # + + /* + * Protected 32-bit. We want to reuse the code-seg descriptor, + * the Default operand size must not be 1 when entering long mode. + */ + + pm2_status $status_prot2 + + /* + * Enable 64-bit page translation entries - CR4.PAE = 1. + * Paging is not enabled until after long mode is enabled. + */ movl %cr4, %eax @@ -141,45 +166,276 @@ movl %eax, %cr4 - # set up paging tables - + /* Set up paging tables */ leal ptl_0, %eax movl %eax, %cr3 - # enable long mode - - movl $EFER_MSR_NUM, %ecx # EFER MSR number - rdmsr # read EFER - btsl $AMD_LME_FLAG, %eax # set LME = 1 - wrmsr # write EFER - - # enable paging to activate long mode (set CR0.PG = 1) - + /* Enable long mode */ + movl $EFER_MSR_NUM, %ecx + rdmsr /* read EFER */ + btsl $AMD_LME_FLAG, %eax /* set LME = 1 */ + wrmsr + + /* Enable paging to activate long mode (set CR0.PG = 1) */ movl %cr0, %eax btsl $31, %eax movl %eax, %cr0 - # at this point we are in compatibility mode - + /* At this point we are in compatibility mode */ jmpl $gdtselector(KTEXT_DES), $start64 +/** Print string to EGA display (in light red) and halt. + * + * Should be executed from 32 bit protected mode with paging + * turned off. Stack is not required. This routine is used even + * if CONFIG_EGA is not enabled. Since we are going to halt the + * CPU anyway, it is always better to at least try to print + * some hints. + * + * @param %esi Pointer to the NULL-terminated string + * to be print. + * + */ +pm_error_halt: + movl $0xb8000, %edi /* base of EGA text mode memory */ + xorl %eax, %eax + + /* Read bits 8 - 15 of the cursor address */ + movw $0x3d4, %dx + movb $0xe, %al + outb %al, %dx + + movw $0x3d5, %dx + inb %dx, %al + shl $8, %ax + + /* Read bits 0 - 7 of the cursor address */ + movw $0x3d4, %dx + movb $0xf, %al + outb %al, %dx + + movw $0x3d5, %dx + inb %dx, %al + + /* Sanity check for the cursor on screen */ + cmp $2000, %ax + jb err_cursor_ok + + movw $1998, %ax + + err_cursor_ok: + + movw %ax, %bx + shl $1, %eax + addl %eax, %edi + + err_ploop: + lodsb + + cmp $0, %al + je err_ploop_end + + movb $0x0c, %ah /* black background, light red foreground */ + stosw + + /* Sanity check for the cursor on the last line */ + inc %bx + cmp $2000, %bx + jb err_ploop + + /* Scroll the screen (24 rows) */ + movl %esi, %edx + movl $0xb80a0, %esi + movl $0xb8000, %edi + movl $960, %ecx + rep movsl + + /* Clear the 24th row */ + xorl %eax, %eax + movl $40, %ecx + rep stosl + + /* Go to row 24 */ + movl %edx, %esi + movl $0xb8f00, %edi + movw $1920, %bx + + jmp err_ploop + err_ploop_end: + + /* Write bits 8 - 15 of the cursor address */ + movw $0x3d4, %dx + movb $0xe, %al + outb %al, %dx + + movw $0x3d5, %dx + movb %bh, %al + outb %al, %dx + + /* Write bits 0 - 7 of the cursor address */ + movw $0x3d4, %dx + movb $0xf, %al + outb %al, %dx + + movw $0x3d5, %dx + movb %bl, %al + outb %al, %dx + + cli + hlt1: + hlt + jmp hlt1 + +/** Print string to EGA display (in light green). + * + * Should be called from 32 bit protected mode with paging + * turned off. A stack space of at least 24 bytes is required, + * but the function does not establish a stack frame. + * + * Macros such as pm_status and pm2_status take care that + * this function is used only when CONFIG_EGA is enabled + * and CONFIG_FB is disabled. + * + * @param %esi Pointer to the NULL-terminated string + * to be print. + * + */ +pm_early_puts: + pushl %eax + pushl %ebx + pushl %ecx + pushl %edx + pushl %edi + + movl $0xb8000, %edi /* base of EGA text mode memory */ + xorl %eax, %eax + + /* Read bits 8 - 15 of the cursor address */ + movw $0x3d4, %dx + movb $0xe, %al + outb %al, %dx + + movw $0x3d5, %dx + inb %dx, %al + shl $8, %ax + + /* Read bits 0 - 7 of the cursor address */ + movw $0x3d4, %dx + movb $0xf, %al + outb %al, %dx + + movw $0x3d5, %dx + inb %dx, %al + + /* Sanity check for the cursor on screen */ + cmp $2000, %ax + jb pm_puts_cursor_ok + + movw $1998, %ax + + pm_puts_cursor_ok: + + movw %ax, %bx + shl $1, %eax + addl %eax, %edi + + pm_puts_ploop: + lodsb + + cmp $0, %al + je pm_puts_ploop_end + + movb $0x0a, %ah /* black background, light green foreground */ + stosw + + /* Sanity check for the cursor on the last line */ + inc %bx + cmp $2000, %bx + jb pm_puts_ploop + + /* Scroll the screen (24 rows) */ + movl %esi, %edx + movl $0xb80a0, %esi + movl $0xb8000, %edi + movl $960, %ecx + rep movsl + + /* Clear the 24th row */ + xorl %eax, %eax + movl $40, %ecx + rep stosl + + /* Go to row 24 */ + movl %edx, %esi + movl $0xb8f00, %edi + movw $1920, %bx + + jmp pm_puts_ploop + pm_puts_ploop_end: + + /* Write bits 8 - 15 of the cursor address */ + movw $0x3d4, %dx + movb $0xe, %al + outb %al, %dx + + movw $0x3d5, %dx + movb %bh, %al + outb %al, %dx + + /* Write bits 0 - 7 of the cursor address */ + movw $0x3d4, %dx + movb $0xf, %al + outb %al, %dx + + movw $0x3d5, %dx + movb %bl, %al + outb %al, %dx + + popl %edi + popl %edx + popl %ecx + popl %ebx + popl %eax + + ret + .code64 + +.macro long_status msg + pushq %rdi + movq \msg, %rdi + call early_puts + popq %rdi +.endm + start64: + + /* + * Long mode. + */ + movq $(PA2KA(START_STACK)), %rsp - # call arch_pre_main(grub_eax, grub_ebx) + /* Create the first stack frame */ + pushq $0 + movq %rsp, %rbp + + long_status $status_long + + /* Call arch_pre_main(grub_eax, grub_ebx) */ xorq %rdi, %rdi movl grub_eax, %edi xorq %rsi, %rsi movl grub_ebx, %esi - call arch_pre_main - - # create the first stack frame - pushq $0 - movq %rsp, %rbp - - call main_bsp - - # not reached - + + movabsq $arch_pre_main, %rax + callq *%rax + + long_status $status_main + + /* Call main_bsp() */ + movabsq $main_bsp, %rax + call *%rax + + /* Not reached */ cli hlt0: @@ -187,10 +443,32 @@ jmp hlt0 -# Print string from %esi to EGA display (in red) and halt -error_halt: - movl $0xb8000, %edi # base of EGA text mode memory - xorl %eax, %eax - - movw $0x3d4, %dx # read bits 8 - 15 of the cursor address +/** Print string to EGA display. + * + * Should be called from long mode (with paging enabled + * and stack established). This function is ABI compliant + * (without red-zone). + * + * If CONFIG_EGA is undefined or CONFIG_FB is defined + * then this function does nothing. + * + * @param %rdi Pointer to the NULL-terminated string + * to be printed. + * + */ +early_puts: + +#if ((defined(CONFIG_EGA)) && (!defined(CONFIG_FB))) + + /* Prologue, save preserved registers */ + pushq %rbp + movq %rsp, %rbp + pushq %rbx + + movq %rdi, %rsi + movq $(PA2KA(0xb8000)), %rdi /* base of EGA text mode memory */ + xorq %rax, %rax + + /* Read bits 8 - 15 of the cursor address */ + movw $0x3d4, %dx movb $0xe, %al outb %al, %dx @@ -200,5 +478,6 @@ shl $8, %ax - movw $0x3d4, %dx # read bits 0 - 7 of the cursor address + /* Read bits 0 - 7 of the cursor address */ + movw $0x3d4, %dx movb $0xf, %al outb %al, %dx @@ -207,27 +486,52 @@ inb %dx, %al - cmp $1920, %ax - jbe cursor_ok - - movw $1920, %ax # sanity check for the cursor on the last line - - cursor_ok: + /* Sanity check for the cursor on screen */ + cmp $2000, %ax + jb early_puts_cursor_ok + + movw $1998, %ax + + early_puts_cursor_ok: movw %ax, %bx - shl $1, %eax - addl %eax, %edi - - movw $0x0c00, %ax # black background, light red foreground - - ploop: + shl $1, %rax + addq %rax, %rdi + + early_puts_ploop: lodsb + cmp $0, %al - je ploop_end + je early_puts_ploop_end + + movb $0x0e, %ah /* black background, yellow foreground */ stosw + + /* Sanity check for the cursor on the last line */ inc %bx - jmp ploop - ploop_end: - - movw $0x3d4, %dx # write bits 8 - 15 of the cursor address + cmp $2000, %bx + jb early_puts_ploop + + /* Scroll the screen (24 rows) */ + movq %rsi, %rdx + movq $(PA2KA(0xb80a0)), %rsi + movq $(PA2KA(0xb8000)), %rdi + movq $480, %rcx + rep movsq + + /* Clear the 24th row */ + xorq %rax, %rax + movq $20, %rcx + rep stosq + + /* Go to row 24 */ + movq %rdx, %rsi + movq $(PA2KA(0xb8f00)), %rdi + movw $1920, %bx + + jmp early_puts_ploop + early_puts_ploop_end: + + /* Write bits 8 - 15 of the cursor address */ + movw $0x3d4, %dx movb $0xe, %al outb %al, %dx @@ -237,5 +541,6 @@ outb %al, %dx - movw $0x3d4, %dx # write bits 0 - 7 of the cursor address + /* Write bits 0 - 7 of the cursor address */ + movw $0x3d4, %dx movb $0xf, %al outb %al, %dx @@ -245,8 +550,11 @@ outb %al, %dx - cli - hlt1: - hlt - jmp hlt1 + /* Epilogue, restore preserved registers */ + popq %rbx + leave + +#endif + + ret #include "vesa_real.inc" @@ -254,59 +562,76 @@ .section K_INI_PTLS, "aw", @progbits -# -# Macro for generating initial page table contents. -# @param cnt Number of entries to generat. Must be multiple of 8. -# @param g Number of GB that will be added to the mapping. -# -.macro ptl2gen cnt g -.if \cnt - ptl2gen "\cnt - 8" \g - .quad ((\cnt - 8) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE) - .quad ((\cnt - 7) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE) - .quad ((\cnt - 6) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE) - .quad ((\cnt - 5) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE) - .quad ((\cnt - 4) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE) - .quad ((\cnt - 3) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE) - .quad ((\cnt - 2) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE) - .quad ((\cnt - 1) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE) -.endif +/** Generate initial page table contents. + * + * @param cnt Number of entries to generate. Must be multiple of 8. + * @param g Number of GB that will be added to the mapping. + * + */ +.macro ptl2gen cnt g + .if \cnt + ptl2gen "\cnt - 8" \g + .quad ((\cnt - 8) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE) + .quad ((\cnt - 7) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE) + .quad ((\cnt - 6) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE) + .quad ((\cnt - 5) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE) + .quad ((\cnt - 4) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE) + .quad ((\cnt - 3) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE) + .quad ((\cnt - 2) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE) + .quad ((\cnt - 1) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE) + .endif .endm -# Page table for pages in the first gigabyte. -.align 4096 -.global ptl_2_0g -ptl_2_0g: +/* Page table for pages in the 1st gigabyte. */ +.align 4096 +ptl_2_0g: ptl2gen 512 0 -# Page table for pages in the second gigabyte. -.align 4096 -.global ptl_2_1g +/* Page table for pages in the 2nd gigabyte. */ +.align 4096 ptl_2_1g: ptl2gen 512 1 -# Page table for pages in the third gigabyte. -.align 4096 -.global ptl_2_2g +/* Page table for pages in the 3rd gigabyte. */ +.align 4096 ptl_2_2g: ptl2gen 512 2 -# Page table for pages in the fourth gigabyte. -.align 4096 -.global ptl_2_3g +/* Page table for pages in the 4th gigabyte. */ +.align 4096 ptl_2_3g: ptl2gen 512 3 -.align 4096 -.global ptl_1 +/* Page table for pages in the 5th gigabyte. */ +.align 4096 +ptl_2_4g: + ptl2gen 512 4 + +/* Page table for pages in the 6th gigabyte. */ +.align 4096 +ptl_2_5g: + ptl2gen 512 5 + +/* Page table for pages in the 7th gigabyte. */ +.align 4096 +ptl_2_6g: + ptl2gen 512 6 + +/* Page table for pages in the 8th gigabyte. */ +.align 4096 +ptl_2_7g: + ptl2gen 512 7 + +.align 4096 ptl_1: - # Identity mapping for [0; 4G) + /* Identity mapping for [0; 8G) */ .quad ptl_2_0g + (PTL_WRITABLE | PTL_PRESENT) - .quad ptl_2_1g + (PTL_WRITABLE | PTL_PRESENT) + .quad ptl_2_1g + (PTL_WRITABLE | PTL_PRESENT) .quad ptl_2_2g + (PTL_WRITABLE | PTL_PRESENT) .quad ptl_2_3g + (PTL_WRITABLE | PTL_PRESENT) - .fill 506, 8, 0 - # Mapping of [0; 1G) at -2G - .quad ptl_2_0g + (PTL_WRITABLE | PTL_PRESENT) - .fill 1, 8, 0 + .quad ptl_2_4g + (PTL_WRITABLE | PTL_PRESENT) + .quad ptl_2_5g + (PTL_WRITABLE | PTL_PRESENT) + .quad ptl_2_6g + (PTL_WRITABLE | PTL_PRESENT) + .quad ptl_2_7g + (PTL_WRITABLE | PTL_PRESENT) + .fill 504, 8, 0 .align 4096 @@ -314,8 +639,7 @@ ptl_0: .quad ptl_1 + (PTL_WRITABLE | PTL_PRESENT) - .fill 255,8,0 + .fill 255, 8, 0 .quad ptl_1 + (PTL_WRITABLE | PTL_PRESENT) - .fill 254,8,0 - .quad ptl_1 + (PTL_WRITABLE | PTL_PRESENT) + .fill 255, 8, 0 .section K_DATA_START, "aw", @progbits @@ -332,12 +656,27 @@ .long 0 -extended_cpuid_msg: +err_extended_cpuid: .asciz "Error: Extended CPUID not supported -- CPU is not 64-bit. System halted." -long_mode_msg: +err_long_mode: .asciz "Error: 64-bit long mode not supported. System halted." -noexecute_msg: +err_noexecute: .asciz "Error: No-execute pages not supported. System halted." -fx_msg: +err_fx: .asciz "Error: FXSAVE/FXRESTORE instructions not supported. System halted." -sse2_msg: +err_sse2: .asciz "Error: SSE2 instructions not supported. System halted." + +status_prot: + .asciz "[prot] " +status_vesa_copy: + .asciz "[vesa_copy] " +status_grub_cmdline: + .asciz "[grub_cmdline] " +status_vesa_real: + .asciz "[vesa_real] " +status_prot2: + .asciz "[prot2] " +status_long: + .asciz "[long] " +status_main: + .asciz "[main] " Index: kernel/arch/amd64/src/boot/vesa_ret.inc =================================================================== --- kernel/arch/amd64/src/boot/vesa_ret.inc (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/src/boot/vesa_ret.inc (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -1,13 +1,19 @@ .code32 vesa_init_protected: + cld + + /* Initialize stack pointer */ + movl $START_STACK, %esp + + /* Kernel data + stack */ movw $gdtselector(KDATA_DES), %cx movw %cx, %es - movw %cx, %ds # kernel data + stack + movw %cx, %ds movw %cx, %ss - # - # Simics seems to remove hidden part of GS on entering user mode - # when _visible_ part of GS does not point to user-mode segment. - # + /* + * Simics seems to remove hidden part of GS on entering user mode + * when _visible_ part of GS does not point to user-mode segment. + */ movw $gdtselector(UDATA_DES), %cx @@ -15,5 +21,3 @@ movw %cx, %gs - movl $START_STACK, %esp # initialize stack pointer - jmpl $gdtselector(KTEXT32_DES), $vesa_meeting_point Index: kernel/arch/amd64/src/context.S =================================================================== --- kernel/arch/amd64/src/context.S (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/src/context.S (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -41,9 +41,9 @@ context_save_arch: movq (%rsp), %rdx # the caller's return %eip - - # In %edi is passed 1st argument - CONTEXT_SAVE_ARCH_CORE %rdi %rdx - xorq %rax,%rax # context_save returns 1 + # 1st argument passed in %edi + CONTEXT_SAVE_ARCH_CORE %rdi %rdx + + xorq %rax, %rax # context_save returns 1 incq %rax ret @@ -55,10 +55,9 @@ # pointed by the 1st argument. Returns 0 in EAX. # -context_restore_arch: - +context_restore_arch: CONTEXT_RESTORE_ARCH_CORE %rdi %rdx - - movq %rdx,(%rsp) - - xorq %rax,%rax # context_restore returns 0 + + movq %rdx, (%rsp) + + xorq %rax, %rax # context_restore returns 0 ret Index: kernel/arch/amd64/src/cpu/cpu.c =================================================================== --- kernel/arch/amd64/src/cpu/cpu.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/src/cpu/cpu.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -47,11 +47,11 @@ * Contains only non-MP-Specification specific SMP code. */ -#define AMD_CPUID_EBX 0x68747541 -#define AMD_CPUID_ECX 0x444d4163 -#define AMD_CPUID_EDX 0x69746e65 +#define AMD_CPUID_EBX 0x68747541 +#define AMD_CPUID_ECX 0x444d4163 +#define AMD_CPUID_EDX 0x69746e65 -#define INTEL_CPUID_EBX 0x756e6547 -#define INTEL_CPUID_ECX 0x6c65746e -#define INTEL_CPUID_EDX 0x49656e69 +#define INTEL_CPUID_EBX 0x756e6547 +#define INTEL_CPUID_ECX 0x6c65746e +#define INTEL_CPUID_EDX 0x49656e69 @@ -127,31 +127,31 @@ { cpu_info_t info; - + CPU->arch.vendor = VendorUnknown; if (has_cpuid()) { cpuid(INTEL_CPUID_LEVEL, &info); - + /* * Check for AMD processor. */ - if (info.cpuid_ebx == AMD_CPUID_EBX && - info.cpuid_ecx == AMD_CPUID_ECX && - info.cpuid_edx == AMD_CPUID_EDX) { + if ((info.cpuid_ebx == AMD_CPUID_EBX) && + (info.cpuid_ecx == AMD_CPUID_ECX) && + (info.cpuid_edx == AMD_CPUID_EDX)) { CPU->arch.vendor = VendorAMD; } - + /* * Check for Intel processor. - */ - if (info.cpuid_ebx == INTEL_CPUID_EBX && - info.cpuid_ecx == INTEL_CPUID_ECX && - info.cpuid_edx == INTEL_CPUID_EDX) { + */ + if ((info.cpuid_ebx == INTEL_CPUID_EBX) && + (info.cpuid_ecx == INTEL_CPUID_ECX) && + (info.cpuid_edx == INTEL_CPUID_EDX)) { CPU->arch.vendor = VendorIntel; } - + cpuid(INTEL_CPUID_STANDARD, &info); CPU->arch.family = (info.cpuid_eax >> 8) & 0xf; CPU->arch.model = (info.cpuid_eax >> 4) & 0xf; - CPU->arch.stepping = (info.cpuid_eax >> 0) & 0xf; + CPU->arch.stepping = (info.cpuid_eax >> 0) & 0xf; } } Index: kernel/arch/amd64/src/debug/stacktrace.c =================================================================== --- kernel/arch/amd64/src/debug/stacktrace.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/src/debug/stacktrace.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -37,6 +37,6 @@ #include -#define FRAME_OFFSET_FP_PREV 0 -#define FRAME_OFFSET_RA 1 +#define FRAME_OFFSET_FP_PREV 0 +#define FRAME_OFFSET_RA 1 bool kernel_frame_pointer_validate(uintptr_t fp) @@ -49,4 +49,5 @@ uint64_t *stack = (void *) fp; *prev = stack[FRAME_OFFSET_FP_PREV]; + return true; } @@ -56,4 +57,5 @@ uint64_t *stack = (void *) fp; *ra = stack[FRAME_OFFSET_RA]; + return true; } Index: kernel/arch/amd64/src/debugger.c =================================================================== --- kernel/arch/amd64/src/debugger.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/src/debugger.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -230,13 +230,13 @@ return; - printf("*** Found ZERO on address %lx (slot %d) ***\n", + printf("*** Found ZERO on address %" PRIp " (slot %d) ***\n", breakpoints[slot].address, slot); } else { - printf("Data watchpoint - new data: %lx\n", + printf("Data watchpoint - new data: %" PRIp "\n", *((unative_t *) breakpoints[slot].address)); } } - printf("Reached breakpoint %d:%lx (%s)\n", slot, getip(istate), + printf("Reached breakpoint %d:%" PRIp " (%s)\n", slot, getip(istate), symtab_fmt_name_lookup(getip(istate))); @@ -349,11 +349,9 @@ { #ifdef __32_BITS__ - printf("# Count Address In symbol\n"); - printf("-- ----- ---------- ---------\n"); + printf("[nr] [count] [address ] [in symbol\n"); #endif #ifdef __64_BITS__ - printf("# Count Address In symbol\n"); - printf("-- ----- ------------------ ---------\n"); + printf("[nr] [count] [address ] [in symbol\n"); #endif @@ -365,5 +363,5 @@ #ifdef __32_BITS__ - printf("%-2u %-5" PRIs " %p %s\n", i, + printf("%-4u %7" PRIs " %p %s\n", i, breakpoints[i].counter, breakpoints[i].address, symbol); @@ -371,5 +369,5 @@ #ifdef __64_BITS__ - printf("%-2u %-5" PRIs " %p %s\n", i, + printf("%-4u %7" PRIs " %p %s\n", i, breakpoints[i].counter, breakpoints[i].address, symbol); Index: kernel/arch/amd64/src/delay.S =================================================================== --- kernel/arch/amd64/src/delay.S (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/src/delay.S (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -37,10 +37,14 @@ asm_delay_loop: -0: dec %rdi - jnz 0b + 0: + dec %rdi + jnz 0b + ret asm_fake_loop: -0: dec %rdi - jz 0b + 0: + dec %rdi + jz 0b + ret Index: kernel/arch/amd64/src/fpu_context.c =================================================================== --- kernel/arch/amd64/src/fpu_context.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/src/fpu_context.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup amd64 +/** @addtogroup amd64 * @{ */ Index: kernel/arch/amd64/src/interrupt.c =================================================================== --- kernel/arch/amd64/src/interrupt.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/src/interrupt.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -63,22 +63,15 @@ void (* eoi_function)(void) = NULL; -void decode_istate(int n, istate_t *istate) -{ - const char *symbol = symtab_fmt_name_lookup(istate->rip); - - printf("-----EXCEPTION(%d) OCCURED----- ( %s )\n", n, __func__); - printf("%%rip: %#llx (%s)\n", istate->rip, symbol); - printf("ERROR_WORD=%#llx\n", istate->error_word); - printf("%%cs=%#llx, rflags=%#llx, %%cr0=%#llx\n", istate->cs, - istate->rflags, read_cr0()); - printf("%%rax=%#llx, %%rcx=%#llx, %%rdx=%#llx\n", istate->rax, +void istate_decode(istate_t *istate) +{ + printf("error_word=%#llx\n", istate->error_word); + printf("cs =%#0.16llx\trflags=%#0.16llx\n", istate->cs, + istate->rflags); + printf("rax=%#0.16llx\trbx=%#0.16llx\trcx=%#0.16llx\n", istate->rax, istate->rcx, istate->rdx); - printf("%%rsi=%#llx, %%rdi=%#llx, %%r8=%#llx\n", istate->rsi, + printf("rsi=%#0.16llx\trdi=%#0.16llx\tr8 =%#0.16llx\n", istate->rsi, istate->rdi, istate->r8); - printf("%%r9=%#llx, %%r10=%#llx, %%r11=%#llx\n", istate->r9, + printf("r9 =%#0.16llx\tr10=%#0.16llx\tr11=%#0.16llx\n", istate->r9, istate->r10, istate->r11); - printf("%%rsp=%#llx\n", &istate->stack[0]); - - stack_trace_istate(istate); } @@ -95,6 +88,5 @@ { fault_if_from_uspace(istate, "Unserviced interrupt: %u.", n); - decode_istate(n, istate); - panic("Unserviced interrupt."); + panic_badtrap(istate, n, "Unserviced interrupt."); } @@ -102,6 +94,5 @@ { fault_if_from_uspace(istate, "Divide error."); - decode_istate(n, istate); - panic("Divide error."); + panic_badtrap(istate, n, "Divide error."); } @@ -129,7 +120,5 @@ fault_if_from_uspace(istate, "General protection fault."); } - - decode_istate(n, istate); - panic("General protection fault."); + panic_badtrap(istate, n, "General protection fault."); } @@ -137,6 +126,5 @@ { fault_if_from_uspace(istate, "Stack fault."); - decode_istate(n, istate); - panic("Stack fault."); + panic_badtrap(istate, n, "Stack fault."); } @@ -214,5 +202,4 @@ exc_register(12, "ss_fault", true, (iroutine_t) ss_fault); exc_register(13, "gp_fault", true, (iroutine_t) gp_fault); - exc_register(14, "ident_mapper", true, (iroutine_t) ident_page_fault); #ifdef CONFIG_SMP Index: kernel/arch/amd64/src/mm/page.c =================================================================== --- kernel/arch/amd64/src/mm/page.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/src/mm/page.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -39,5 +39,4 @@ #include #include -#include #include #include @@ -48,72 +47,23 @@ #include -/* Definitions for identity page mapper */ -pte_t helper_ptl1[512] __attribute__((aligned (PAGE_SIZE))); -pte_t helper_ptl2[512] __attribute__((aligned (PAGE_SIZE))); -pte_t helper_ptl3[512] __attribute__((aligned (PAGE_SIZE))); -extern pte_t ptl_0; /* From boot.S */ - -#define PTL1_PRESENT(ptl0, page) (!(GET_PTL1_FLAGS_ARCH(ptl0, PTL0_INDEX_ARCH(page)) & PAGE_NOT_PRESENT)) -#define PTL2_PRESENT(ptl1, page) (!(GET_PTL2_FLAGS_ARCH(ptl1, PTL1_INDEX_ARCH(page)) & PAGE_NOT_PRESENT)) -#define PTL3_PRESENT(ptl2, page) (!(GET_PTL3_FLAGS_ARCH(ptl2, PTL2_INDEX_ARCH(page)) & PAGE_NOT_PRESENT)) - -#define PTL1_ADDR(ptl0, page) ((pte_t *)PA2KA(GET_PTL1_ADDRESS_ARCH(ptl0, PTL0_INDEX_ARCH(page)))) -#define PTL2_ADDR(ptl1, page) ((pte_t *)PA2KA(GET_PTL2_ADDRESS_ARCH(ptl1, PTL1_INDEX_ARCH(page)))) -#define PTL3_ADDR(ptl2, page) ((pte_t *)PA2KA(GET_PTL3_ADDRESS_ARCH(ptl2, PTL2_INDEX_ARCH(page)))) - -#define SETUP_PTL1(ptl0, page, tgt) { \ - SET_PTL1_ADDRESS_ARCH(ptl0, PTL0_INDEX_ARCH(page), (uintptr_t)KA2PA(tgt)); \ - SET_PTL1_FLAGS_ARCH(ptl0, PTL0_INDEX_ARCH(page), PAGE_WRITE | PAGE_EXEC); \ - } -#define SETUP_PTL2(ptl1, page, tgt) { \ - SET_PTL2_ADDRESS_ARCH(ptl1, PTL1_INDEX_ARCH(page), (uintptr_t)KA2PA(tgt)); \ - SET_PTL2_FLAGS_ARCH(ptl1, PTL1_INDEX_ARCH(page), PAGE_WRITE | PAGE_EXEC); \ - } -#define SETUP_PTL3(ptl2, page, tgt) { \ - SET_PTL3_ADDRESS_ARCH(ptl2, PTL2_INDEX_ARCH(page), (uintptr_t)KA2PA(tgt)); \ - SET_PTL3_FLAGS_ARCH(ptl2, PTL2_INDEX_ARCH(page), PAGE_WRITE | PAGE_EXEC); \ - } -#define SETUP_FRAME(ptl3, page, tgt) { \ - SET_FRAME_ADDRESS_ARCH(ptl3, PTL3_INDEX_ARCH(page), (uintptr_t)KA2PA(tgt)); \ - SET_FRAME_FLAGS_ARCH(ptl3, PTL3_INDEX_ARCH(page), PAGE_WRITE | PAGE_EXEC); \ - } - - void page_arch_init(void) { - uintptr_t cur; - unsigned int i; - int identity_flags = PAGE_CACHEABLE | PAGE_EXEC | PAGE_GLOBAL | PAGE_WRITE; - if (config.cpu_active == 1) { + uintptr_t cur; + unsigned int identity_flags = + PAGE_CACHEABLE | PAGE_EXEC | PAGE_GLOBAL | PAGE_WRITE; + page_mapping_operations = &pt_mapping_operations; - + page_table_lock(AS_KERNEL, true); - + /* * PA2KA(identity) mapping for all frames. */ - for (cur = 0; cur < last_frame; cur += FRAME_SIZE) { - /* Standard identity mapping */ + for (cur = 0; cur < last_frame; cur += FRAME_SIZE) page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, identity_flags); - } - /* Upper kernel mapping - * - from zero to top of kernel (include bottom addresses - * because some are needed for init) - */ - for (cur = PA2KA_CODE(0); cur < config.base + config.kernel_size; cur += FRAME_SIZE) - page_mapping_insert(AS_KERNEL, cur, KA2PA(cur), identity_flags); + page_table_unlock(AS_KERNEL, true); - for (cur = config.stack_base; cur < config.stack_base + config.stack_size; cur += FRAME_SIZE) - page_mapping_insert(AS_KERNEL, cur, KA2PA(cur), identity_flags); - - for (i = 0; i < init.cnt; i++) { - for (cur = init.tasks[i].addr; cur < init.tasks[i].addr + init.tasks[i].size; cur += FRAME_SIZE) - page_mapping_insert(AS_KERNEL, PA2KA_CODE(KA2PA(cur)), KA2PA(cur), identity_flags); - } - - page_table_unlock(AS_KERNEL, true); - exc_register(14, "page_fault", true, (iroutine_t) page_fault); write_cr3((uintptr_t) AS_KERNEL->genarch.page_table); @@ -122,68 +72,12 @@ } - -/** Identity page mapper - * - * We need to map whole physical memory identically before the page subsystem - * is initializaed. This thing clears page table and fills in the specific - * items. - */ -void ident_page_fault(unsigned int n, istate_t *istate) -{ - uintptr_t page; - static uintptr_t oldpage = 0; - pte_t *aptl_1, *aptl_2, *aptl_3; - - page = read_cr2(); - if (oldpage) { - /* Unmap old address */ - aptl_1 = PTL1_ADDR(&ptl_0, oldpage); - aptl_2 = PTL2_ADDR(aptl_1, oldpage); - aptl_3 = PTL3_ADDR(aptl_2, oldpage); - - SET_FRAME_FLAGS_ARCH(aptl_3, PTL3_INDEX_ARCH(oldpage), PAGE_NOT_PRESENT); - if (KA2PA(aptl_3) == KA2PA(helper_ptl3)) - SET_PTL3_FLAGS_ARCH(aptl_2, PTL2_INDEX_ARCH(oldpage), PAGE_NOT_PRESENT); - if (KA2PA(aptl_2) == KA2PA(helper_ptl2)) - SET_PTL2_FLAGS_ARCH(aptl_1, PTL1_INDEX_ARCH(oldpage), PAGE_NOT_PRESENT); - if (KA2PA(aptl_1) == KA2PA(helper_ptl1)) - SET_PTL1_FLAGS_ARCH(&ptl_0, PTL0_INDEX_ARCH(oldpage), PAGE_NOT_PRESENT); - } - if (PTL1_PRESENT(&ptl_0, page)) - aptl_1 = PTL1_ADDR(&ptl_0, page); - else { - SETUP_PTL1(&ptl_0, page, helper_ptl1); - aptl_1 = helper_ptl1; - } - - if (PTL2_PRESENT(aptl_1, page)) - aptl_2 = PTL2_ADDR(aptl_1, page); - else { - SETUP_PTL2(aptl_1, page, helper_ptl2); - aptl_2 = helper_ptl2; - } - - if (PTL3_PRESENT(aptl_2, page)) - aptl_3 = PTL3_ADDR(aptl_2, page); - else { - SETUP_PTL3(aptl_2, page, helper_ptl3); - aptl_3 = helper_ptl3; - } - - SETUP_FRAME(aptl_3, page, page); - - oldpage = page; -} - - void page_fault(unsigned int n, istate_t *istate) { - uintptr_t page; - pf_access_t access; - - page = read_cr2(); + uintptr_t page = read_cr2(); if (istate->error_word & PFERR_CODE_RSVD) panic("Reserved bit set in page table entry."); + + pf_access_t access; if (istate->error_word & PFERR_CODE_RW) @@ -196,24 +90,22 @@ if (as_page_fault(page, access, istate) == AS_PF_FAULT) { fault_if_from_uspace(istate, "Page fault: %#x.", page); - - decode_istate(n, istate); - printf("Page fault address: %llx.\n", page); - panic("Page fault."); + panic_memtrap(istate, access, page, "Page fault."); } } - uintptr_t hw_map(uintptr_t physaddr, size_t size) { if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH)) - panic("Unable to map physical memory %p (%d bytes).", physaddr, + panic("Unable to map physical memory %p (%" PRIs " bytes).", physaddr, size); uintptr_t virtaddr = PA2KA(last_frame); pfn_t i; - + page_table_lock(AS_KERNEL, true); + for (i = 0; i < ADDR2PFN(ALIGN_UP(size, PAGE_SIZE)); i++) page_mapping_insert(AS_KERNEL, virtaddr + PFN2ADDR(i), physaddr + PFN2ADDR(i), PAGE_NOT_CACHEABLE | PAGE_WRITE); + page_table_unlock(AS_KERNEL, true); Index: kernel/arch/amd64/src/proc/scheduler.c =================================================================== --- kernel/arch/amd64/src/proc/scheduler.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/src/proc/scheduler.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -38,5 +38,5 @@ #include #include -#include /* SP_DELTA */ +#include #include #include @@ -58,12 +58,12 @@ CPU->arch.tss->rsp0 = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE - SP_DELTA]; - + /* * Syscall support. */ swapgs(); - write_msr(AMD_MSR_GS, (uintptr_t)THREAD->arch.syscall_rsp); + write_msr(AMD_MSR_GS, (uintptr_t) THREAD->arch.syscall_rsp); swapgs(); - + /* TLS support - set FS to thread local storage */ write_msr(AMD_MSR_FS, THREAD->arch.tls); Index: kernel/arch/amd64/src/proc/task.c =================================================================== --- kernel/arch/amd64/src/proc/task.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/src/proc/task.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -39,20 +39,22 @@ /** Perform amd64 specific task initialization. * - * @param t Task to be initialized. + * @param task Task to be initialized. + * */ -void task_create_arch(task_t *t) +void task_create_arch(task_t *task) { - t->arch.iomapver = 0; - bitmap_initialize(&t->arch.iomap, NULL, 0); + task->arch.iomapver = 0; + bitmap_initialize(&task->arch.iomap, NULL, 0); } /** Perform amd64 specific task destruction. * - * @param t Task to be initialized. + * @param task Task to be initialized. + * */ -void task_destroy_arch(task_t *t) +void task_destroy_arch(task_t *task) { - if (t->arch.iomap.map) - free(t->arch.iomap.map); + if (task->arch.iomap.map) + free(task->arch.iomap.map); } Index: kernel/arch/amd64/src/proc/thread.c =================================================================== --- kernel/arch/amd64/src/proc/thread.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/src/proc/thread.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -37,15 +37,17 @@ /** Perform amd64 specific thread initialization. * - * @param t Thread to be initialized. + * @param thread Thread to be initialized. + * */ -void thread_create_arch(thread_t *t) +void thread_create_arch(thread_t *thread) { - t->arch.tls = 0; - t->arch.syscall_rsp[SYSCALL_USTACK_RSP] = 0; + thread->arch.tls = 0; + thread->arch.syscall_rsp[SYSCALL_USTACK_RSP] = 0; + /* * Kernel RSP can be precalculated at thread creation time. */ - t->arch.syscall_rsp[SYSCALL_KSTACK_RSP] = - (uintptr_t) &t->kstack[PAGE_SIZE - sizeof(uint64_t)]; + thread->arch.syscall_rsp[SYSCALL_KSTACK_RSP] = + (uintptr_t) &thread->kstack[PAGE_SIZE - sizeof(uint64_t)]; } Index: kernel/arch/amd64/src/smp/ap.S =================================================================== --- kernel/arch/amd64/src/smp/ap.S (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/amd64/src/smp/ap.S (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -55,12 +55,12 @@ xorw %ax, %ax movw %ax, %ds - - lgdtl ap_gdtr # initialize Global Descriptor Table register + + lgdtl ap_gdtr # initialize Global Descriptor Table register movl %cr0, %eax orl $1, %eax - movl %eax, %cr0 # switch to protected mode + movl %eax, %cr0 # switch to protected mode jmpl $gdtselector(KTEXT32_DES), $jump_to_kernel - BOOT_OFFSET + AP_BOOT_OFFSET - + jump_to_kernel: .code32 @@ -72,5 +72,5 @@ movw %ax, %gs - # Enable 64-bit page transaltion entries - CR4.PAE = 1. + # Enable 64-bit page transaltion entries (CR4.PAE = 1). # Paging is not enabled until after long mode is enabled @@ -78,15 +78,15 @@ btsl $5, %eax movl %eax, %cr4 - + leal ptl_0, %eax movl %eax, %cr3 # Enable long mode - movl $EFER_MSR_NUM, %ecx # EFER MSR number - rdmsr # Read EFER - btsl $AMD_LME_FLAG, %eax # Set LME=1 - wrmsr # Write EFER + movl $EFER_MSR_NUM, %ecx # EFER MSR number + rdmsr # Read EFER + btsl $AMD_LME_FLAG, %eax # Set LME=1 + wrmsr # Write EFER - # Enable paging to activate long mode (set CR0.PG=1) + # Enable paging to activate long mode (set CR0.PG = 1) movl %cr0, %eax btsl $31, %eax @@ -98,8 +98,12 @@ .code64 start64: - movq (ctx), %rsp + movabsq $ctx, %rsp + movq (%rsp), %rsp + pushq $0 movq %rsp, %rbp - call main_ap - AP_BOOT_OFFSET + BOOT_OFFSET # never returns + + movabsq $main_ap, %rax + callq *%rax # never returns #endif /* CONFIG_SMP */ Index: kernel/arch/arm32/Makefile.inc =================================================================== --- kernel/arch/arm32/Makefile.inc (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/arm32/Makefile.inc (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -46,5 +46,4 @@ arch/$(KARCH)/src/context.S \ arch/$(KARCH)/src/dummy.S \ - arch/$(KARCH)/src/panic.S \ arch/$(KARCH)/src/cpu/cpu.c \ arch/$(KARCH)/src/ddi/ddi.c \ Index: kernel/arch/arm32/include/asm.h =================================================================== --- kernel/arch/arm32/include/asm.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/arm32/include/asm.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -41,36 +41,37 @@ #include #include +#include /** No such instruction on ARM to sleep CPU. */ -static inline void cpu_sleep(void) +NO_TRACE static inline void cpu_sleep(void) { } -static inline void pio_write_8(ioport8_t *port, uint8_t v) +NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v) { *port = v; } -static inline void pio_write_16(ioport16_t *port, uint16_t v) +NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v) { *port = v; } -static inline void pio_write_32(ioport32_t *port, uint32_t v) +NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v) { *port = v; } -static inline uint8_t pio_read_8(ioport8_t *port) +NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port) { return *port; } -static inline uint16_t pio_read_16(ioport16_t *port) +NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port) { return *port; } -static inline uint32_t pio_read_32(ioport32_t *port) +NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port) { return *port; @@ -84,7 +85,8 @@ * */ -static inline uintptr_t get_stack_base(void) +NO_TRACE static inline uintptr_t get_stack_base(void) { uintptr_t v; + asm volatile ( "and %[v], sp, %[size]\n" @@ -92,4 +94,5 @@ : [size] "r" (~(STACK_SIZE - 1)) ); + return v; } Index: kernel/arch/arm32/include/atomic.h =================================================================== --- kernel/arch/arm32/include/atomic.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/arm32/include/atomic.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -38,4 +38,5 @@ #include +#include /** Atomic addition. @@ -47,5 +48,6 @@ * */ -static inline atomic_count_t atomic_add(atomic_t *val, atomic_count_t i) +NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val, + atomic_count_t i) { /* @@ -66,5 +68,5 @@ * */ -static inline void atomic_inc(atomic_t *val) +NO_TRACE static inline void atomic_inc(atomic_t *val) { atomic_add(val, 1); @@ -76,5 +78,5 @@ * */ -static inline void atomic_dec(atomic_t *val) { +NO_TRACE static inline void atomic_dec(atomic_t *val) { atomic_add(val, -1); } @@ -86,5 +88,5 @@ * */ -static inline atomic_count_t atomic_preinc(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_preinc(atomic_t *val) { return atomic_add(val, 1); @@ -97,5 +99,5 @@ * */ -static inline atomic_count_t atomic_predec(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_predec(atomic_t *val) { return atomic_add(val, -1); @@ -108,5 +110,5 @@ * */ -static inline atomic_count_t atomic_postinc(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val) { return atomic_add(val, 1) - 1; @@ -119,5 +121,5 @@ * */ -static inline atomic_count_t atomic_postdec(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val) { return atomic_add(val, -1) + 1; Index: kernel/arch/arm32/include/cycle.h =================================================================== --- kernel/arch/arm32/include/cycle.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/arm32/include/cycle.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -37,11 +37,14 @@ #define KERN_arm32_CYCLE_H_ -/** Returns count of CPU cycles. +#include + +/** Return count of CPU cycles. * - * No such instruction on ARM to get count of cycles. + * No such instruction on ARM to get count of cycles. * - * @return Count of CPU cycles. + * @return Count of CPU cycles. + * */ -static inline uint64_t get_cycle(void) +NO_TRACE static inline uint64_t get_cycle(void) { return 0; Index: kernel/arch/arm32/include/exception.h =================================================================== --- kernel/arch/arm32/include/exception.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/arm32/include/exception.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -28,5 +28,5 @@ */ -/** @addtogroup arm32 +/** @addtogroup arm32 * @{ */ @@ -40,4 +40,5 @@ #include #include +#include /** If defined, forces using of high exception vectors. */ @@ -45,17 +46,17 @@ #ifdef HIGH_EXCEPTION_VECTORS - #define EXC_BASE_ADDRESS 0xffff0000 + #define EXC_BASE_ADDRESS 0xffff0000 #else - #define EXC_BASE_ADDRESS 0x0 + #define EXC_BASE_ADDRESS 0x0 #endif /* Exception Vectors */ -#define EXC_RESET_VEC (EXC_BASE_ADDRESS + 0x0) -#define EXC_UNDEF_INSTR_VEC (EXC_BASE_ADDRESS + 0x4) -#define EXC_SWI_VEC (EXC_BASE_ADDRESS + 0x8) -#define EXC_PREFETCH_ABORT_VEC (EXC_BASE_ADDRESS + 0xc) -#define EXC_DATA_ABORT_VEC (EXC_BASE_ADDRESS + 0x10) -#define EXC_IRQ_VEC (EXC_BASE_ADDRESS + 0x18) -#define EXC_FIQ_VEC (EXC_BASE_ADDRESS + 0x1c) +#define EXC_RESET_VEC (EXC_BASE_ADDRESS + 0x0) +#define EXC_UNDEF_INSTR_VEC (EXC_BASE_ADDRESS + 0x4) +#define EXC_SWI_VEC (EXC_BASE_ADDRESS + 0x8) +#define EXC_PREFETCH_ABORT_VEC (EXC_BASE_ADDRESS + 0xc) +#define EXC_DATA_ABORT_VEC (EXC_BASE_ADDRESS + 0x10) +#define EXC_IRQ_VEC (EXC_BASE_ADDRESS + 0x18) +#define EXC_FIQ_VEC (EXC_BASE_ADDRESS + 0x1c) /* Exception numbers */ @@ -68,12 +69,11 @@ #define EXC_FIQ 6 - /** Kernel stack pointer. * * It is set when thread switches to user mode, * and then used for exception handling. + * */ extern uintptr_t supervisor_sp; - /** Temporary exception stack pointer. @@ -81,7 +81,7 @@ * Temporary stack is used in exceptions handling routines * before switching to thread's kernel stack. + * */ extern uintptr_t exc_stack; - /** Struct representing CPU state saved when an exception occurs. */ @@ -90,5 +90,5 @@ uint32_t sp; uint32_t lr; - + uint32_t r0; uint32_t r1; @@ -104,42 +104,39 @@ uint32_t fp; uint32_t r12; - + uint32_t pc; } istate_t; - -/** Sets Program Counter member of given istate structure. +/** Set Program Counter member of given istate structure. * - * @param istate istate structure + * @param istate istate structure * @param retaddr new value of istate's PC member + * */ -static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) +NO_TRACE static inline void istate_set_retaddr(istate_t *istate, + uintptr_t retaddr) { - istate->pc = retaddr; + istate->pc = retaddr; } - -/** Returns true if exception happened while in userspace. */ -static inline int istate_from_uspace(istate_t *istate) +/** Return true if exception happened while in userspace. */ +NO_TRACE static inline int istate_from_uspace(istate_t *istate) { - return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE; + return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE; } - -/** Returns Program Counter member of given istate structure. */ -static inline unative_t istate_get_pc(istate_t *istate) +/** Return Program Counter member of given istate structure. */ +NO_TRACE static inline unative_t istate_get_pc(istate_t *istate) { - return istate->pc; + return istate->pc; } -static inline unative_t istate_get_fp(istate_t *istate) +NO_TRACE static inline unative_t istate_get_fp(istate_t *istate) { return istate->fp; } - extern void install_exception_handlers(void); extern void exception_init(void); -extern void print_istate(istate_t *istate); extern void reset_exception_entry(void); extern void irq_exception_entry(void); @@ -150,5 +147,4 @@ extern void swi_exception_entry(void); - #endif Index: kernel/arch/arm32/include/faddr.h =================================================================== --- kernel/arch/arm32/include/faddr.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/arm32/include/faddr.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup arm32 +/** @addtogroup arm32 * @{ */ @@ -42,6 +42,7 @@ * * @param fptr Function pointer. + * */ -#define FADDR(fptr) ((uintptr_t) (fptr)) +#define FADDR(fptr) ((uintptr_t) (fptr)) #endif Index: kernel/arch/arm32/include/interrupt.h =================================================================== --- kernel/arch/arm32/include/interrupt.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/arm32/include/interrupt.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -41,9 +41,8 @@ /** Initial size of exception dispatch table. */ -#define IVT_ITEMS 6 +#define IVT_ITEMS 6 /** Index of the first item in exception dispatch table. */ -#define IVT_FIRST 0 - +#define IVT_FIRST 0 extern void interrupt_init(void); @@ -54,5 +53,4 @@ extern bool interrupts_disabled(void); - #endif Index: kernel/arch/arm32/include/mm/page.h =================================================================== --- kernel/arch/arm32/include/mm/page.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/arm32/include/mm/page.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup arm32mm +/** @addtogroup arm32mm * @{ */ @@ -40,4 +40,5 @@ #include #include +#include #define PAGE_WIDTH FRAME_WIDTH @@ -192,7 +193,8 @@ /** Sets the address of level 0 page table. * - * @param pt Pointer to the page table to set. - */ -static inline void set_ptl0_addr(pte_t *pt) + * @param pt Pointer to the page table to set. + * + */ +NO_TRACE static inline void set_ptl0_addr(pte_t *pt) { asm volatile ( @@ -205,12 +207,13 @@ /** Returns level 0 page table entry flags. * - * @param pt Level 0 page table. - * @param i Index of the entry to return. - */ -static inline int get_pt_level0_flags(pte_t *pt, size_t i) + * @param pt Level 0 page table. + * @param i Index of the entry to return. + * + */ +NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i) { pte_level0_t *p = &pt[i].l0; int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); - + return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | @@ -220,14 +223,15 @@ /** Returns level 1 page table entry flags. * - * @param pt Level 1 page table. - * @param i Index of the entry to return. - */ -static inline int get_pt_level1_flags(pte_t *pt, size_t i) + * @param pt Level 1 page table. + * @param i Index of the entry to return. + * + */ +NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i) { pte_level1_t *p = &pt[i].l1; - + int dt = p->descriptor_type; int ap = p->access_permission_0; - + return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) | @@ -241,15 +245,15 @@ } - /** Sets flags of level 0 page table entry. * - * @param pt level 0 page table - * @param i index of the entry to be changed - * @param flags new flags - */ -static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags) + * @param pt level 0 page table + * @param i index of the entry to be changed + * @param flags new flags + * + */ +NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags) { pte_level0_t *p = &pt[i].l0; - + if (flags & PAGE_NOT_PRESENT) { p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; @@ -262,5 +266,5 @@ p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; p->should_be_zero = 0; - } + } } @@ -268,13 +272,14 @@ /** Sets flags of level 1 page table entry. * - * We use same access rights for the whole page. When page is not preset we - * store 1 in acess_rigts_3 so that at least one bit is 1 (to mark correct - * page entry, see #PAGE_VALID_ARCH). - * - * @param pt Level 1 page table. - * @param i Index of the entry to be changed. - * @param flags New flags. - */ -static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags) + * We use same access rights for the whole page. When page + * is not preset we store 1 in acess_rigts_3 so that at least + * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH). + * + * @param pt Level 1 page table. + * @param i Index of the entry to be changed. + * @param flags New flags. + * + */ +NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags) { pte_level1_t *p = &pt[i].l1; @@ -287,12 +292,12 @@ p->access_permission_3 = p->access_permission_0; } - + p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; - + /* default access permission */ p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = PTE_AP_USER_NO_KERNEL_RW; - + if (flags & PAGE_USER) { if (flags & PAGE_READ) { Index: kernel/arch/arm32/include/mm/tlb.h =================================================================== --- kernel/arch/arm32/include/mm/tlb.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/arm32/include/mm/tlb.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup arm32mm +/** @addtogroup arm32mm * @{ */ Index: kernel/arch/arm32/src/asm.S =================================================================== --- kernel/arch/arm32/src/asm.S (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/arm32/src/asm.S (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -1,31 +1,30 @@ -# -# Copyright (c) 2007 Michal Kebrt -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# +/* + * Copyright (c) 2007 Michal Kebrt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ - .text @@ -37,4 +36,5 @@ .global memcpy_from_uspace_failover_address .global memcpy_to_uspace_failover_address +.global early_putchar memsetb: @@ -47,57 +47,67 @@ memcpy_from_uspace: memcpy_to_uspace: - add r3, r1, #3 - bic r3, r3, #3 - cmp r1, r3 - stmdb sp!, {r4, r5, lr} - mov r5, r0 /* save dst */ - beq 4f -1: - cmp r2, #0 - movne ip, #0 - beq 3f -2: - ldrb r3, [ip, r1] - strb r3, [ip, r0] - add ip, ip, #1 - cmp ip, r2 - bne 2b -3: - mov r0, r5 - ldmia sp!, {r4, r5, pc} -4: - add r3, r0, #3 - bic r3, r3, #3 - cmp r0, r3 - bne 1b - movs r4, r2, lsr #2 - moveq lr, r4 - beq 6f - mov lr, #0 - mov ip, lr -5: - ldr r3, [ip, r1] - add lr, lr, #1 - cmp lr, r4 - str r3, [ip, r0] - add ip, ip, #4 - bne 5b -6: - ands r4, r2, #3 - beq 3b - mov r3, lr, lsl #2 - add r0, r3, r0 - add ip, r3, r1 - mov r2, #0 -7: - ldrb r3, [r2, ip] - strb r3, [r2, r0] - add r2, r2, #1 - cmp r2, r4 - bne 7b - b 3b + add r3, r1, #3 + bic r3, r3, #3 + cmp r1, r3 + stmdb sp!, {r4, r5, lr} + mov r5, r0 /* save dst */ + beq 4f + + 1: + cmp r2, #0 + movne ip, #0 + beq 3f + + 2: + ldrb r3, [ip, r1] + strb r3, [ip, r0] + add ip, ip, #1 + cmp ip, r2 + bne 2b + + 3: + mov r0, r5 + ldmia sp!, {r4, r5, pc} + + 4: + add r3, r0, #3 + bic r3, r3, #3 + cmp r0, r3 + bne 1b + movs r4, r2, lsr #2 + moveq lr, r4 + beq 6f + mov lr, #0 + mov ip, lr + + 5: + ldr r3, [ip, r1] + add lr, lr, #1 + cmp lr, r4 + str r3, [ip, r0] + add ip, ip, #4 + bne 5b + + 6: + ands r4, r2, #3 + beq 3b + mov r3, lr, lsl #2 + add r0, r3, r0 + add ip, r3, r1 + mov r2, #0 + + 7: + ldrb r3, [r2, ip] + strb r3, [r2, r0] + add r2, r2, #1 + cmp r2, r4 + bne 7b + b 3b memcpy_from_uspace_failover_address: memcpy_to_uspace_failover_address: - mov r0, #0 - ldmia sp!, {r4, r5, pc} + mov r0, #0 + ldmia sp!, {r4, r5, pc} + +early_putchar: + mov pc, lr Index: kernel/arch/arm32/src/exc_handler.S =================================================================== --- kernel/arch/arm32/src/exc_handler.S (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/arm32/src/exc_handler.S (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -98,4 +98,8 @@ stmfd r13!, {r13, lr}^ stmfd r13!, {r2} + + # Stop stack traces here + mov fp, #0 + b 2f @@ -123,6 +127,4 @@ stmfd r13!, {r2} 2: - # Stop stack traces here - mov fp, #0 .endm Index: kernel/arch/arm32/src/exception.c =================================================================== --- kernel/arch/arm32/src/exception.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/arm32/src/exception.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -173,20 +173,14 @@ * @param istate Structure to be printed. */ -void print_istate(istate_t *istate) +void istate_decode(istate_t *istate) { - printf("istate dump:\n"); - - printf(" r0: %x r1: %x r2: %x r3: %x\n", + printf("r0 =%#0.8lx\tr1 =%#0.8lx\tr2 =%#0.8lx\tr3 =%#0.8lx\n", istate->r0, istate->r1, istate->r2, istate->r3); - printf(" r4: %x r5: %x r6: %x r7: %x\n", + printf("r4 =%#0.8lx\tr5 =%#0.8lx\tr6 =%#0.8lx\tr7 =%#0.8lx\n", istate->r4, istate->r5, istate->r6, istate->r7); - printf(" r8: %x r8: %x r10: %x fp: %x\n", + printf("r8 =%#0.8lx\tr9 =%#0.8lx\tr10=%#0.8lx\tfp =%#0.8lx\n", istate->r8, istate->r9, istate->r10, istate->fp); - printf(" r12: %x sp: %x lr: %x spsr: %x\n", + printf("r12=%#0.8lx\tsp =%#0.8lx\tlr =%#0.8lx\tspsr=%#0.8lx\n", istate->r12, istate->sp, istate->lr, istate->spsr); - - printf(" pc: %x\n", istate->pc); - - stack_trace_istate(istate); } Index: kernel/arch/arm32/src/mm/page.c =================================================================== --- kernel/arch/arm32/src/mm/page.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/arm32/src/mm/page.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup arm32mm +/** @addtogroup arm32mm * @{ */ Index: kernel/arch/arm32/src/mm/page_fault.c =================================================================== --- kernel/arch/arm32/src/mm/page_fault.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/arm32/src/mm/page_fault.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -183,10 +183,5 @@ if (ret == AS_PF_FAULT) { fault_if_from_uspace(istate, "Page fault: %#x.", badvaddr); - print_istate(istate); - printf("page fault - pc: %x, va: %x, status: %x(%x), " - "access:%d\n", istate->pc, badvaddr, fsr.status, fsr, - access); - - panic("Page fault."); + panic_memtrap(istate, access, badvaddr, "Page fault."); } } @@ -203,8 +198,6 @@ if (ret == AS_PF_FAULT) { - printf("prefetch_abort\n"); - print_istate(istate); - panic("page fault - prefetch_abort at address: %x.", - istate->pc); + panic_memtrap(istate, PF_ACCESS_EXEC, istate->pc, + "Page fault - prefetch_abort."); } } Index: kernel/arch/arm32/src/panic.S =================================================================== --- kernel/arch/arm32/src/panic.S (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ (revision ) @@ -1,35 +1,0 @@ -# -# Copyright (c) 2007 Michal Kebrt -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -.text - -.global panic_printf - -panic_printf: - bl printf - bl cpu_halt Index: kernel/arch/ia32/Makefile.inc =================================================================== --- kernel/arch/ia32/Makefile.inc (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/Makefile.inc (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -76,5 +76,4 @@ ARCH_SOURCES = \ arch/$(KARCH)/src/context.S \ - arch/$(KARCH)/src/debug/panic.s \ arch/$(KARCH)/src/debug/stacktrace.c \ arch/$(KARCH)/src/debug/stacktrace_asm.S \ Index: kernel/arch/ia32/include/asm.h =================================================================== --- kernel/arch/ia32/include/asm.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/include/asm.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -41,18 +41,8 @@ #include #include +#include extern uint32_t interrupt_handler_size; -extern void paging_on(void); - -extern void interrupt_handlers(void); - -extern void enable_l_apic_in_msr(void); - - -extern void asm_delay_loop(uint32_t t); -extern void asm_fake_loop(uint32_t t); - - /** Halt CPU * @@ -60,5 +50,5 @@ * */ -static inline __attribute__((noreturn)) void cpu_halt(void) +NO_TRACE static inline __attribute__((noreturn)) void cpu_halt(void) { while (true) { @@ -69,10 +59,12 @@ } -static inline void cpu_sleep(void) -{ - asm volatile ("hlt\n"); -} - -#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ +NO_TRACE static inline void cpu_sleep(void) +{ + asm volatile ( + "hlt\n" + ); +} + +#define GEN_READ_REG(reg) NO_TRACE static inline unative_t read_ ##reg (void) \ { \ unative_t res; \ @@ -84,5 +76,5 @@ } -#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ +#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (unative_t regn) \ { \ asm volatile ( \ @@ -119,9 +111,10 @@ * */ -static inline void pio_write_8(ioport8_t *port, uint8_t val) +NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val) { asm volatile ( "outb %b[val], %w[port]\n" - :: [val] "a" (val), [port] "d" (port) + :: [val] "a" (val), + [port] "d" (port) ); } @@ -135,9 +128,10 @@ * */ -static inline void pio_write_16(ioport16_t *port, uint16_t val) +NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val) { asm volatile ( "outw %w[val], %w[port]\n" - :: [val] "a" (val), [port] "d" (port) + :: [val] "a" (val), + [port] "d" (port) ); } @@ -151,9 +145,10 @@ * */ -static inline void pio_write_32(ioport32_t *port, uint32_t val) +NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val) { asm volatile ( "outl %[val], %w[port]\n" - :: [val] "a" (val), [port] "d" (port) + :: [val] "a" (val), + [port] "d" (port) ); } @@ -167,5 +162,5 @@ * */ -static inline uint8_t pio_read_8(ioport8_t *port) +NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port) { uint8_t val; @@ -188,5 +183,5 @@ * */ -static inline uint16_t pio_read_16(ioport16_t *port) +NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port) { uint16_t val; @@ -209,5 +204,5 @@ * */ -static inline uint32_t pio_read_32(ioport32_t *port) +NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port) { uint32_t val; @@ -230,5 +225,5 @@ * */ -static inline ipl_t interrupts_enable(void) +NO_TRACE static inline ipl_t interrupts_enable(void) { ipl_t v; @@ -252,5 +247,5 @@ * */ -static inline ipl_t interrupts_disable(void) +NO_TRACE static inline ipl_t interrupts_disable(void) { ipl_t v; @@ -273,5 +268,5 @@ * */ -static inline void interrupts_restore(ipl_t ipl) +NO_TRACE static inline void interrupts_restore(ipl_t ipl) { asm volatile ( @@ -287,5 +282,5 @@ * */ -static inline ipl_t interrupts_read(void) +NO_TRACE static inline ipl_t interrupts_read(void) { ipl_t v; @@ -305,5 +300,5 @@ * */ -static inline bool interrupts_disabled(void) +NO_TRACE static inline bool interrupts_disabled(void) { ipl_t v; @@ -319,14 +314,15 @@ /** Write to MSR */ -static inline void write_msr(uint32_t msr, uint64_t value) +NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value) { asm volatile ( "wrmsr" - :: "c" (msr), "a" ((uint32_t) (value)), + :: "c" (msr), + "a" ((uint32_t) (value)), "d" ((uint32_t) (value >> 32)) ); } -static inline uint64_t read_msr(uint32_t msr) +NO_TRACE static inline uint64_t read_msr(uint32_t msr) { uint32_t ax, dx; @@ -334,5 +330,6 @@ asm volatile ( "rdmsr" - : "=a" (ax), "=d" (dx) + : "=a" (ax), + "=d" (dx) : "c" (msr) ); @@ -349,5 +346,5 @@ * */ -static inline uintptr_t get_stack_base(void) +NO_TRACE static inline uintptr_t get_stack_base(void) { uintptr_t v; @@ -367,5 +364,5 @@ * */ -static inline void invlpg(uintptr_t addr) +NO_TRACE static inline void invlpg(uintptr_t addr) { asm volatile ( @@ -380,5 +377,5 @@ * */ -static inline void gdtr_load(ptr_16_32_t *gdtr_reg) +NO_TRACE static inline void gdtr_load(ptr_16_32_t *gdtr_reg) { asm volatile ( @@ -393,5 +390,5 @@ * */ -static inline void gdtr_store(ptr_16_32_t *gdtr_reg) +NO_TRACE static inline void gdtr_store(ptr_16_32_t *gdtr_reg) { asm volatile ( @@ -406,5 +403,5 @@ * */ -static inline void idtr_load(ptr_16_32_t *idtr_reg) +NO_TRACE static inline void idtr_load(ptr_16_32_t *idtr_reg) { asm volatile ( @@ -419,5 +416,5 @@ * */ -static inline void tr_load(uint16_t sel) +NO_TRACE static inline void tr_load(uint16_t sel) { asm volatile ( @@ -427,4 +424,75 @@ } +extern void paging_on(void); +extern void enable_l_apic_in_msr(void); + +extern void asm_delay_loop(uint32_t); +extern void asm_fake_loop(uint32_t); + +extern uintptr_t int_0; +extern uintptr_t int_1; +extern uintptr_t int_2; +extern uintptr_t int_3; +extern uintptr_t int_4; +extern uintptr_t int_5; +extern uintptr_t int_6; +extern uintptr_t int_7; +extern uintptr_t int_8; +extern uintptr_t int_9; +extern uintptr_t int_10; +extern uintptr_t int_11; +extern uintptr_t int_12; +extern uintptr_t int_13; +extern uintptr_t int_14; +extern uintptr_t int_15; +extern uintptr_t int_16; +extern uintptr_t int_17; +extern uintptr_t int_18; +extern uintptr_t int_19; +extern uintptr_t int_20; +extern uintptr_t int_21; +extern uintptr_t int_22; +extern uintptr_t int_23; +extern uintptr_t int_24; +extern uintptr_t int_25; +extern uintptr_t int_26; +extern uintptr_t int_27; +extern uintptr_t int_28; +extern uintptr_t int_29; +extern uintptr_t int_30; +extern uintptr_t int_31; +extern uintptr_t int_32; +extern uintptr_t int_33; +extern uintptr_t int_34; +extern uintptr_t int_35; +extern uintptr_t int_36; +extern uintptr_t int_37; +extern uintptr_t int_38; +extern uintptr_t int_39; +extern uintptr_t int_40; +extern uintptr_t int_41; +extern uintptr_t int_42; +extern uintptr_t int_43; +extern uintptr_t int_44; +extern uintptr_t int_45; +extern uintptr_t int_46; +extern uintptr_t int_47; +extern uintptr_t int_48; +extern uintptr_t int_49; +extern uintptr_t int_50; +extern uintptr_t int_51; +extern uintptr_t int_52; +extern uintptr_t int_53; +extern uintptr_t int_54; +extern uintptr_t int_55; +extern uintptr_t int_56; +extern uintptr_t int_57; +extern uintptr_t int_58; +extern uintptr_t int_59; +extern uintptr_t int_60; +extern uintptr_t int_61; +extern uintptr_t int_62; +extern uintptr_t int_63; + #endif Index: kernel/arch/ia32/include/atomic.h =================================================================== --- kernel/arch/ia32/include/atomic.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/include/atomic.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -39,6 +39,7 @@ #include #include +#include -static inline void atomic_inc(atomic_t *val) +NO_TRACE static inline void atomic_inc(atomic_t *val) { #ifdef CONFIG_SMP @@ -55,5 +56,5 @@ } -static inline void atomic_dec(atomic_t *val) +NO_TRACE static inline void atomic_dec(atomic_t *val) { #ifdef CONFIG_SMP @@ -70,5 +71,5 @@ } -static inline atomic_count_t atomic_postinc(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val) { atomic_count_t r = 1; @@ -83,5 +84,5 @@ } -static inline atomic_count_t atomic_postdec(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val) { atomic_count_t r = -1; @@ -99,5 +100,5 @@ #define atomic_predec(val) (atomic_postdec(val) - 1) -static inline atomic_count_t test_and_set(atomic_t *val) +NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val) { atomic_count_t v = 1; @@ -113,5 +114,5 @@ /** ia32 specific fast spinlock */ -static inline void atomic_lock_arch(atomic_t *val) +NO_TRACE static inline void atomic_lock_arch(atomic_t *val) { atomic_count_t tmp; Index: kernel/arch/ia32/include/barrier.h =================================================================== --- kernel/arch/ia32/include/barrier.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/include/barrier.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -36,4 +36,6 @@ #define KERN_ia32_BARRIER_H_ +#include + /* * NOTE: @@ -50,5 +52,5 @@ #define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") -static inline void cpuid_serialization(void) +NO_TRACE static inline void cpuid_serialization(void) { asm volatile ( Index: kernel/arch/ia32/include/bios/bios.h =================================================================== --- kernel/arch/ia32/include/bios/bios.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/include/bios/bios.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup ia32 +/** @addtogroup ia32 * @{ */ @@ -38,5 +38,5 @@ #include -#define BIOS_EBDA_PTR 0x40e +#define BIOS_EBDA_PTR 0x40e extern uintptr_t ebda; Index: kernel/arch/ia32/include/cycle.h =================================================================== --- kernel/arch/ia32/include/cycle.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/include/cycle.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup ia32 +/** @addtogroup ia32 * @{ */ @@ -36,5 +36,7 @@ #define KERN_ia32_CYCLE_H_ -static inline uint64_t get_cycle(void) +#include + +NO_TRACE static inline uint64_t get_cycle(void) { uint64_t v; Index: kernel/arch/ia32/include/drivers/i8259.h =================================================================== --- kernel/arch/ia32/include/drivers/i8259.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/include/drivers/i8259.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -48,6 +48,6 @@ extern void i8259_init(void); -extern void pic_enable_irqs(uint16_t irqmask); -extern void pic_disable_irqs(uint16_t irqmask); +extern void pic_enable_irqs(uint16_t); +extern void pic_disable_irqs(uint16_t); extern void pic_eoi(void); Index: kernel/arch/ia32/include/fpu_context.h =================================================================== --- kernel/arch/ia32/include/fpu_context.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/include/fpu_context.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup ia32 +/** @addtogroup ia32 * @{ */ @@ -38,13 +38,12 @@ #include -#define FPU_CONTEXT_ALIGN 16 - -void fpu_fxsr(void); -void fpu_fsr(void); - +#define FPU_CONTEXT_ALIGN 16 typedef struct { - uint8_t fpu[512]; /* FXSAVE & FXRSTOR storage area */ + uint8_t fpu[512]; /* FXSAVE & FXRSTOR storage area */ } fpu_context_t; + +extern void fpu_fxsr(void); +extern void fpu_fsr(void); #endif Index: kernel/arch/ia32/include/interrupt.h =================================================================== --- kernel/arch/ia32/include/interrupt.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/include/interrupt.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -38,24 +38,25 @@ #include #include +#include -#define IVT_ITEMS IDT_ITEMS -#define IVT_FIRST 0 +#define IVT_ITEMS IDT_ITEMS +#define IVT_FIRST 0 -#define EXC_COUNT 32 -#define IRQ_COUNT 16 +#define EXC_COUNT 32 +#define IRQ_COUNT 16 -#define IVT_EXCBASE 0 -#define IVT_IRQBASE (IVT_EXCBASE + EXC_COUNT) -#define IVT_FREEBASE (IVT_IRQBASE + IRQ_COUNT) +#define IVT_EXCBASE 0 +#define IVT_IRQBASE (IVT_EXCBASE + EXC_COUNT) +#define IVT_FREEBASE (IVT_IRQBASE + IRQ_COUNT) -#define IRQ_CLK 0 -#define IRQ_KBD 1 -#define IRQ_PIC1 2 -#define IRQ_PIC_SPUR 7 -#define IRQ_MOUSE 12 -#define IRQ_DP8390 9 +#define IRQ_CLK 0 +#define IRQ_KBD 1 +#define IRQ_PIC1 2 +#define IRQ_PIC_SPUR 7 +#define IRQ_MOUSE 12 +#define IRQ_DP8390 9 -/* this one must have four least significant bits set to ones */ -#define VECTOR_APIC_SPUR (IVT_ITEMS - 1) +/* This one must have four least significant bits set to ones */ +#define VECTOR_APIC_SPUR (IVT_ITEMS - 1) #if (((VECTOR_APIC_SPUR + 1) % 16) || VECTOR_APIC_SPUR >= IVT_ITEMS) @@ -63,58 +64,70 @@ #endif -#define VECTOR_DEBUG 1 -#define VECTOR_CLK (IVT_IRQBASE + IRQ_CLK) -#define VECTOR_PIC_SPUR (IVT_IRQBASE + IRQ_PIC_SPUR) -#define VECTOR_SYSCALL IVT_FREEBASE -#define VECTOR_TLB_SHOOTDOWN_IPI (IVT_FREEBASE + 1) -#define VECTOR_DEBUG_IPI (IVT_FREEBASE + 2) +#define VECTOR_DEBUG 1 +#define VECTOR_CLK (IVT_IRQBASE + IRQ_CLK) +#define VECTOR_PIC_SPUR (IVT_IRQBASE + IRQ_PIC_SPUR) +#define VECTOR_SYSCALL IVT_FREEBASE +#define VECTOR_TLB_SHOOTDOWN_IPI (IVT_FREEBASE + 1) +#define VECTOR_DEBUG_IPI (IVT_FREEBASE + 2) typedef struct istate { + /* + * The strange order of the GPRs is given by the requirement to use the + * istate structure for both regular interrupts and exceptions as well + * as for syscall handlers which use this order as an optimization. + */ + uint32_t edx; + uint32_t ecx; + uint32_t ebx; + uint32_t esi; + uint32_t edi; + uint32_t ebp; uint32_t eax; - uint32_t ecx; - uint32_t edx; - uint32_t ebp; - + + uint32_t ebp_frame; /* imitation of frame pointer linkage */ + uint32_t eip_frame; /* imitation of return address linkage */ + uint32_t gs; uint32_t fs; uint32_t es; uint32_t ds; - - uint32_t error_word; + + uint32_t error_word; /* real or fake error word */ uint32_t eip; uint32_t cs; uint32_t eflags; - uint32_t stack[]; + uint32_t esp; /* only if istate_t is from uspace */ + uint32_t ss; /* only if istate_t is from uspace */ } istate_t; /** Return true if exception happened while in userspace */ -static inline int istate_from_uspace(istate_t *istate) +NO_TRACE static inline int istate_from_uspace(istate_t *istate) { return !(istate->eip & 0x80000000); } -static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) +NO_TRACE static inline void istate_set_retaddr(istate_t *istate, + uintptr_t retaddr) { istate->eip = retaddr; } -static inline unative_t istate_get_pc(istate_t *istate) +NO_TRACE static inline unative_t istate_get_pc(istate_t *istate) { return istate->eip; } -static inline unative_t istate_get_fp(istate_t *istate) +NO_TRACE static inline unative_t istate_get_fp(istate_t *istate) { return istate->ebp; } -extern void (* disable_irqs_function)(uint16_t irqmask); -extern void (* enable_irqs_function)(uint16_t irqmask); +extern void (* disable_irqs_function)(uint16_t); +extern void (* enable_irqs_function)(uint16_t); extern void (* eoi_function)(void); -extern void decode_istate(istate_t *istate); extern void interrupt_init(void); -extern void trap_virtual_enable_irqs(uint16_t irqmask); -extern void trap_virtual_disable_irqs(uint16_t irqmask); +extern void trap_virtual_enable_irqs(uint16_t); +extern void trap_virtual_disable_irqs(uint16_t); #endif Index: kernel/arch/ia32/include/mm/asid.h =================================================================== --- kernel/arch/ia32/include/mm/asid.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/include/mm/asid.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup ia32mm +/** @addtogroup ia32mm * @{ */ @@ -47,7 +47,7 @@ typedef int32_t asid_t; -#define ASID_MAX_ARCH 3 +#define ASID_MAX_ARCH 3 -#define asid_get() (ASID_START + 1) +#define asid_get() (ASID_START + 1) #define asid_put(asid) Index: kernel/arch/ia32/include/mm/page.h =================================================================== --- kernel/arch/ia32/include/mm/page.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/include/mm/page.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -37,4 +37,5 @@ #include +#include #define PAGE_WIDTH FRAME_WIDTH @@ -161,5 +162,5 @@ } __attribute__ ((packed)) pte_t; -static inline unsigned int get_pt_flags(pte_t *pt, size_t i) +NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i) { pte_t *p = &pt[i]; @@ -174,5 +175,5 @@ } -static inline void set_pt_flags(pte_t *pt, size_t i, int flags) +NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags) { pte_t *p = &pt[i]; Index: kernel/arch/ia32/include/smp/apic.h =================================================================== --- kernel/arch/ia32/include/smp/apic.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/include/smp/apic.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -347,4 +347,5 @@ extern uint32_t apic_id_mask; +extern uint8_t bsp_l_apic; extern void apic_init(void); @@ -355,5 +356,4 @@ extern int l_apic_send_init_ipi(uint8_t); extern void l_apic_debug(void); -extern uint8_t l_apic_id(void); extern uint32_t io_apic_read(uint8_t); Index: kernel/arch/ia32/include/smp/mps.h =================================================================== --- kernel/arch/ia32/include/smp/mps.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/include/smp/mps.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup ia32 +/** @addtogroup ia32 * @{ */ @@ -41,6 +41,6 @@ #include -#define CT_EXT_ENTRY_TYPE 0 -#define CT_EXT_ENTRY_LEN 1 +#define CT_EXT_ENTRY_TYPE 0 +#define CT_EXT_ENTRY_LEN 1 struct mps_fs { @@ -70,5 +70,5 @@ uint16_t ext_table_length; uint8_t ext_table_checksum; - uint8_t xxx; + uint8_t reserved; uint8_t base_table[0]; } __attribute__ ((packed)); @@ -81,5 +81,5 @@ uint8_t cpu_signature[4]; uint32_t feature_flags; - uint32_t xxx[2]; + uint32_t reserved[2]; } __attribute__ ((packed)); @@ -102,5 +102,5 @@ uint8_t intr_type; uint8_t poel; - uint8_t xxx; + uint8_t reserved; uint8_t src_bus_id; uint8_t src_bus_irq; @@ -113,5 +113,5 @@ uint8_t intr_type; uint8_t poel; - uint8_t xxx; + uint8_t reserved; uint8_t src_bus_id; uint8_t src_bus_irq; Index: kernel/arch/ia32/include/smp/smp.h =================================================================== --- kernel/arch/ia32/include/smp/smp.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/include/smp/smp.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup ia32 +/** @addtogroup ia32 * @{ */ @@ -40,12 +40,18 @@ /** SMP config opertaions interface. */ struct smp_config_operations { - size_t (* cpu_count)(void); /**< Return number of detected processors. */ - bool (* cpu_enabled)(size_t i); /**< Check whether the processor of index i is enabled. */ - bool (*cpu_bootstrap)(size_t i); /**< Check whether the processor of index i is BSP. */ - uint8_t (*cpu_apic_id)(size_t i); /**< Return APIC ID of the processor of index i. */ - int (*irq_to_pin)(unsigned int irq); /**< Return mapping between irq and APIC pin. */ + /** Check whether a processor is enabled. */ + bool (* cpu_enabled)(size_t); + + /** Check whether a processor is BSP. */ + bool (*cpu_bootstrap)(size_t); + + /** Return APIC ID of a processor. */ + uint8_t (*cpu_apic_id)(size_t); + + /** Return mapping between IRQ and APIC pin. */ + int (*irq_to_pin)(unsigned int); }; -extern int smp_irq_to_pin(unsigned int irq); +extern int smp_irq_to_pin(unsigned int); #endif Index: kernel/arch/ia32/src/asm.S =================================================================== --- kernel/arch/ia32/src/asm.S (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/src/asm.S (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -1,41 +1,47 @@ -# -# Copyright (c) 2001-2004 Jakub Jermar -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -## very low and hardware-level functions - -# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error -# word and 1 means interrupt with error word -#define ERROR_WORD_INTERRUPT_LIST 0x00027d00 +/* + * Copyright (c) 2001 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** Very low and hardware-level functions + * + */ + +/** + * Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int + * has no error word and 1 means interrupt with error word + * + */ +#define ERROR_WORD_INTERRUPT_LIST 0x00027d00 + +#include +#include .text - .global paging_on .global enable_l_apic_in_msr -.global interrupt_handlers .global memsetb .global memsetw @@ -45,18 +51,17 @@ .global memcpy_to_uspace .global memcpy_to_uspace_failover_address - - -# Wrapper for generic memsetb +.global early_putchar + +/* Wrapper for generic memsetb */ memsetb: jmp _memsetb -# Wrapper for generic memsetw +/* Wrapper for generic memsetw */ memsetw: jmp _memsetw - -#define MEMCPY_DST 4 -#define MEMCPY_SRC 8 -#define MEMCPY_SIZE 12 +#define MEMCPY_DST 4 +#define MEMCPY_SRC 8 +#define MEMCPY_SIZE 12 /** Copy memory to/from userspace. @@ -68,36 +73,42 @@ * or copy_to_uspace(). * - * @param MEMCPY_DST(%esp) Destination address. - * @param MEMCPY_SRC(%esp) Source address. - * @param MEMCPY_SIZE(%esp) Size. + * @param MEMCPY_DST(%esp) Destination address. + * @param MEMCPY_SRC(%esp) Source address. + * @param MEMCPY_SIZE(%esp) Size. * * @return MEMCPY_DST(%esp) on success and 0 on failure. + * */ memcpy: memcpy_from_uspace: memcpy_to_uspace: - movl %edi, %edx /* save %edi */ - movl %esi, %eax /* save %esi */ + movl %edi, %edx /* save %edi */ + movl %esi, %eax /* save %esi */ movl MEMCPY_SIZE(%esp), %ecx - shrl $2, %ecx /* size / 4 */ + shrl $2, %ecx /* size / 4 */ movl MEMCPY_DST(%esp), %edi movl MEMCPY_SRC(%esp), %esi - rep movsl /* copy whole words */ - + /* Copy whole words */ + rep movsl + movl MEMCPY_SIZE(%esp), %ecx - andl $3, %ecx /* size % 4 */ + andl $3, %ecx /* size % 4 */ jz 0f - rep movsb /* copy the rest byte by byte */ - -0: - movl %edx, %edi - movl %eax, %esi - movl MEMCPY_DST(%esp), %eax /* MEMCPY_DST(%esp), success */ - ret - + /* Copy the rest byte by byte */ + rep movsb + + 0: + + movl %edx, %edi + movl %eax, %esi + + /* MEMCPY_DST(%esp), success */ + movl MEMCPY_DST(%esp), %eax + ret + /* * We got here from as_page_fault() after the memory operations @@ -108,26 +119,31 @@ movl %edx, %edi movl %eax, %esi - xorl %eax, %eax /* return 0, failure */ + + /* Return 0, failure */ + xorl %eax, %eax ret -## Turn paging on -# -# Enable paging and write-back caching in CR0. -# +/** Turn paging on + * + * Enable paging and write-back caching in CR0. + * + */ paging_on: movl %cr0, %edx - orl $(1 << 31), %edx # paging on - # clear Cache Disable and not Write Though + orl $(1 << 31), %edx /* paging on */ + + /* Clear Cache Disable and not Write Though */ andl $~((1 << 30) | (1 << 29)), %edx - movl %edx,%cr0 + movl %edx, %cr0 jmp 0f -0: - ret - - -## Enable local APIC -# -# Enable local APIC in MSR. -# + + 0: + ret + +/** Enable local APIC + * + * Enable local APIC in MSR. + * + */ enable_l_apic_in_msr: movl $0x1b, %ecx @@ -138,13 +154,44 @@ ret -# Clear nested flag -# overwrites %ecx +/** Clear nested flag + * + */ .macro CLEAR_NT_FLAG pushfl - pop %ecx - and $0xffffbfff, %ecx - push %ecx + andl $0xffffbfff, (%esp) popfl -.endm +.endm + +#define ISTATE_OFFSET_EDX 0 +#define ISTATE_OFFSET_ECX 4 +#define ISTATE_OFFSET_EBX 8 +#define ISTATE_OFFSET_ESI 12 +#define ISTATE_OFFSET_EDI 16 +#define ISTATE_OFFSET_EBP 20 +#define ISTATE_OFFSET_EAX 24 +#define ISTATE_OFFSET_EBP_FRAME 28 +#define ISTATE_OFFSET_EIP_FRAME 32 +#define ISTATE_OFFSET_GS 36 +#define ISTATE_OFFSET_FS 40 +#define ISTATE_OFFSET_ES 44 +#define ISTATE_OFFSET_DS 48 +#define ISTATE_OFFSET_ERROR_WORD 52 +#define ISTATE_OFFSET_EIP 56 +#define ISTATE_OFFSET_CS 60 +#define ISTATE_OFFSET_EFLAGS 64 +#define ISTATE_OFFSET_ESP 68 +#define ISTATE_OFFSET_SS 72 + +/* + * Size of the istate structure without the hardware-saved part + * and without the error word. + */ +#define ISTATE_SOFT_SIZE 52 + +/* + * Size of the entire istate structure including the error word and the + * hardware-saved part. + */ +#define ISTATE_REAL_SIZE (ISTATE_SOFT_SIZE + 24) /* @@ -160,165 +207,426 @@ sysenter_handler: sti - pushl %ebp # remember user stack - pushl %edi # remember return user address - - pushl %gs # remember TLS - - pushl %eax # syscall number - subl $8, %esp # unused sixth and fifth argument - pushl %esi # fourth argument - pushl %ebx # third argument - pushl %ecx # second argument - pushl %edx # first argument - + subl $(ISTATE_REAL_SIZE), %esp + + /* + * Save the return address and the userspace stack in the istate + * structure on locations that would normally be taken by them. + */ + movl %ebp, ISTATE_OFFSET_ESP(%esp) + movl %edi, ISTATE_OFFSET_EIP(%esp) + + /* + * Push syscall arguments onto the stack + */ + movl %eax, ISTATE_OFFSET_EAX(%esp) + movl %ebx, ISTATE_OFFSET_EBX(%esp) + movl %ecx, ISTATE_OFFSET_ECX(%esp) + movl %edx, ISTATE_OFFSET_EDX(%esp) + movl %esi, ISTATE_OFFSET_ESI(%esp) + movl %edi, ISTATE_OFFSET_EDI(%esp) /* observability; not needed */ + movl %ebp, ISTATE_OFFSET_EBP(%esp) /* observability; not needed */ + + /* + * Fake up the stack trace linkage. + */ + movl %edi, ISTATE_OFFSET_EIP_FRAME(%esp) + movl $0, ISTATE_OFFSET_EBP_FRAME(%esp) + leal ISTATE_OFFSET_EBP_FRAME(%esp), %ebp + + /* + * Save TLS. + */ + movl %gs, %edx + movl %edx, ISTATE_OFFSET_GS(%esp) + + /* + * Switch to kernel selectors. + */ movw $16, %ax movw %ax, %ds movw %ax, %es - + cld call syscall_handler - addl $28, %esp # remove arguments from stack - - pop %gs # restore TLS - - pop %edx # prepare return EIP for SYSEXIT - pop %ecx # prepare userspace ESP for SYSEXIT - - sysexit # return to userspace - - -## Declare interrupt handlers -# -# Declare interrupt handlers for n interrupt -# vectors starting at vector i. -# -# The handlers setup data segment registers -# and call exc_dispatch(). -# -#define INTERRUPT_ALIGN 64 -.macro handler i n - - .ifeq \i - 0x30 # Syscall handler - pushl %ds - pushl %es - pushl %fs - pushl %gs - - # - # Push syscall arguments onto the stack - # - # NOTE: The idea behind the order of arguments passed in registers is to - # use all scratch registers first and preserved registers next. - # An optimized libc syscall wrapper can make use of this setup. - # - pushl %eax - pushl %ebp - pushl %edi - pushl %esi - pushl %ebx - pushl %ecx - pushl %edx - - # we must fill the data segment registers - movw $16, %ax - movw %ax, %ds - movw %ax, %es + + /* + * Restore TLS. + */ + movl ISTATE_OFFSET_GS(%esp), %edx + movl %edx, %gs + + /* + * Prepare return address and userspace stack for SYSEXIT. + */ + movl ISTATE_OFFSET_EIP(%esp), %edx + movl ISTATE_OFFSET_ESP(%esp), %ecx + + addl $(ISTATE_REAL_SIZE), %esp + + sysexit /* return to userspace */ + +/** Declare interrupt handlers + * + * Declare interrupt handlers for n interrupt + * vectors starting at vector i. + * + */ + +.macro handler i +.global int_\i +int_\i: + .ifeq \i - 0x30 + /* Syscall handler */ + subl $(ISTATE_SOFT_SIZE + 4), %esp + + /* + * Push syscall arguments onto the stack + * + * NOTE: The idea behind the order of arguments passed + * in registers is to use all scratch registers + * first and preserved registers next. An optimized + * libc syscall wrapper can make use of this setup. + * The istate structure is arranged in the way to support + * this idea. + * + */ + movl %eax, ISTATE_OFFSET_EAX(%esp) + movl %ebx, ISTATE_OFFSET_EBX(%esp) + movl %ecx, ISTATE_OFFSET_ECX(%esp) + movl %edx, ISTATE_OFFSET_EDX(%esp) + movl %edi, ISTATE_OFFSET_EDI(%esp) + movl %esi, ISTATE_OFFSET_ESI(%esp) + movl %ebp, ISTATE_OFFSET_EBP(%esp) + + /* + * Save the selector registers. + */ + movl %gs, %ecx + movl %fs, %edx + + movl %ecx, ISTATE_OFFSET_GS(%esp) + movl %edx, ISTATE_OFFSET_FS(%esp) + + movl %es, %ecx + movl %ds, %edx + + movl %ecx, ISTATE_OFFSET_ES(%esp) + movl %edx, ISTATE_OFFSET_DS(%esp) + + /* + * Switch to kernel selectors. + */ + movl $16, %eax + movl %eax, %ds + movl %eax, %es + + movl $0, ISTATE_OFFSET_EBP_FRAME(%esp) + movl ISTATE_OFFSET_EIP(%esp), %eax + movl %eax, ISTATE_OFFSET_EIP_FRAME(%esp) + leal ISTATE_OFFSET_EBP_FRAME(%esp), %ebp cld sti - # syscall_handler(edx, ecx, ebx, esi, edi, ebp, eax) + + /* Call syscall_handler(edx, ecx, ebx, esi, edi, ebp, eax) */ call syscall_handler - cli - addl $28, %esp # clean-up of parameters - - popl %gs - popl %fs - popl %es - popl %ds - + CLEAR_NT_FLAG + + /* + * Restore the selector registers. + */ + movl ISTATE_OFFSET_GS(%esp), %ecx + movl ISTATE_OFFSET_FS(%esp), %edx + + movl %ecx, %gs + movl %edx, %fs + + movl ISTATE_OFFSET_ES(%esp), %ecx + movl ISTATE_OFFSET_DS(%esp), %edx + + movl %ecx, %es + movl %edx, %ds + + /* + * Restore the preserved registers the handler cloberred itself + * (i.e. EBP). + */ + movl ISTATE_OFFSET_EBP(%esp), %ebp + + addl $(ISTATE_SOFT_SIZE + 4), %esp iret + .else /* - * This macro distinguishes between two versions of ia32 exceptions. - * One version has error word and the other does not have it. - * The latter version fakes the error word on the stack so that the - * handlers and istate_t can be the same for both types. + * This macro distinguishes between two versions of ia32 + * exceptions. One version has error word and the other + * does not have it. The latter version fakes the error + * word on the stack so that the handlers and istate_t + * can be the same for both types. */ .iflt \i - 32 .if (1 << \i) & ERROR_WORD_INTERRUPT_LIST /* - * With error word, do nothing + * Exception with error word: do nothing */ .else /* - * Version without error word + * Exception without error word: fake up one */ - subl $4, %esp + pushl $0 .endif .else /* - * Version without error word + * Interrupt: fake up one */ - subl $4, %esp + pushl $0 .endif - pushl %ds - pushl %es - pushl %fs - pushl %gs - - pushl %ebp - pushl %edx - pushl %ecx - pushl %eax - - # we must fill the data segment registers - - movw $16, %ax - movw %ax, %ds - movw %ax, %es - - # stop stack traces here + subl $ISTATE_SOFT_SIZE, %esp + + /* + * Save the general purpose registers. + */ + movl %eax, ISTATE_OFFSET_EAX(%esp) + movl %ebx, ISTATE_OFFSET_EBX(%esp) + movl %ecx, ISTATE_OFFSET_ECX(%esp) + movl %edx, ISTATE_OFFSET_EDX(%esp) + movl %edi, ISTATE_OFFSET_EDI(%esp) + movl %esi, ISTATE_OFFSET_ESI(%esp) + movl %ebp, ISTATE_OFFSET_EBP(%esp) + + /* + * Save the selector registers. + */ + movl %gs, %eax + movl %fs, %ebx + movl %es, %ecx + movl %ds, %edx + + movl %eax, ISTATE_OFFSET_GS(%esp) + movl %ebx, ISTATE_OFFSET_FS(%esp) + movl %ecx, ISTATE_OFFSET_ES(%esp) + movl %edx, ISTATE_OFFSET_DS(%esp) + + /* + * Switch to kernel selectors. + */ + movl $16, %eax + movl %eax, %ds + movl %eax, %es + + /* + * Imitate a regular stack frame linkage. + * Stop stack traces here if we came from userspace. + */ + cmpl $8, ISTATE_OFFSET_CS(%esp) + jz 0f xorl %ebp, %ebp - pushl %esp # *istate - pushl $(\i) # intnum - call exc_dispatch # exc_dispatch(intnum, *istate) - addl $8, %esp # Clear arguments from stack - - CLEAR_NT_FLAG # Modifies %ecx - - popl %eax - popl %ecx - popl %edx - popl %ebp - - popl %gs - popl %fs - popl %es - popl %ds - - # skip error word, no matter whether real or fake - addl $4, %esp - iret - .endif - - .align INTERRUPT_ALIGN - .if (\n- \i) - 1 - handler "(\i + 1)", \n + 0: + + movl %ebp, ISTATE_OFFSET_EBP_FRAME(%esp) + movl ISTATE_OFFSET_EIP(%esp), %eax + movl %eax, ISTATE_OFFSET_EIP_FRAME(%esp) + leal ISTATE_OFFSET_EBP_FRAME(%esp), %ebp + + cld + + pushl %esp /* pass istate address */ + pushl $(\i) /* pass intnum */ + + /* Call exc_dispatch(intnum, istate) */ + call exc_dispatch + + addl $8, %esp /* clear arguments from the stack */ + + CLEAR_NT_FLAG + + /* + * Restore the selector registers. + */ + movl ISTATE_OFFSET_GS(%esp), %eax + movl ISTATE_OFFSET_FS(%esp), %ebx + movl ISTATE_OFFSET_ES(%esp), %ecx + movl ISTATE_OFFSET_DS(%esp), %edx + + movl %eax, %gs + movl %ebx, %fs + movl %ecx, %es + movl %edx, %ds + + /* + * Restore the scratch registers and the preserved + * registers the handler cloberred itself + * (i.e. EBX and EBP). + */ + movl ISTATE_OFFSET_EAX(%esp), %eax + movl ISTATE_OFFSET_EBX(%esp), %ebx + movl ISTATE_OFFSET_ECX(%esp), %ecx + movl ISTATE_OFFSET_EDX(%esp), %edx + movl ISTATE_OFFSET_EBP(%esp), %ebp + + addl $(ISTATE_SOFT_SIZE + 4), %esp + iret + .endif .endm -# keep in sync with pm.h !!! -IDT_ITEMS = 64 -.align INTERRUPT_ALIGN +#define LIST_0_63 \ + 0, 1, 2, 3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,\ + 28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,\ + 53,54,55,56,57,58,59,60,61,62,63 + interrupt_handlers: -h_start: - handler 0 IDT_ITEMS -h_end: - -.data -.global interrupt_handler_size - -interrupt_handler_size: .long (h_end - h_start) / IDT_ITEMS +.irp cnt, LIST_0_63 + handler \cnt +.endr + +/** Print Unicode character to EGA display. + * + * If CONFIG_EGA is undefined or CONFIG_FB is defined + * then this function does nothing. + * + * Since the EGA can only display Extended ASCII (usually + * ISO Latin 1) characters, some of the Unicode characters + * can be displayed in a wrong way. Only newline and backspace + * are interpreted, all other characters (even unprintable) are + * printed verbatim. + * + * @param %ebp+0x08 Unicode character to be printed. + * + */ +early_putchar: + +#if ((defined(CONFIG_EGA)) && (!defined(CONFIG_FB))) + + /* Prologue, save preserved registers */ + pushl %ebp + movl %esp, %ebp + pushl %ebx + pushl %esi + pushl %edi + + movl $(PA2KA(0xb8000)), %edi /* base of EGA text mode memory */ + xorl %eax, %eax + + /* Read bits 8 - 15 of the cursor address */ + movw $0x3d4, %dx + movb $0xe, %al + outb %al, %dx + + movw $0x3d5, %dx + inb %dx, %al + shl $8, %ax + + /* Read bits 0 - 7 of the cursor address */ + movw $0x3d4, %dx + movb $0xf, %al + outb %al, %dx + + movw $0x3d5, %dx + inb %dx, %al + + /* Sanity check for the cursor on screen */ + cmp $2000, %ax + jb early_putchar_cursor_ok + + movw $1998, %ax + + early_putchar_cursor_ok: + + movw %ax, %bx + shl $1, %eax + addl %eax, %edi + + movl 0x08(%ebp), %eax + + cmp $0x0a, %al + jne early_putchar_backspace + + /* Interpret newline */ + + movw %bx, %ax /* %bx -> %dx:%ax */ + xorw %dx, %dx + + movw $80, %cx + idivw %cx, %ax /* %dx = %bx % 80 */ + + /* %bx <- %bx + 80 - (%bx % 80) */ + addw %cx, %bx + subw %dx, %bx + + jmp early_putchar_skip + + early_putchar_backspace: + + cmp $0x08, %al + jne early_putchar_print + + /* Interpret backspace */ + + cmp $0x0000, %bx + je early_putchar_skip + + dec %bx + jmp early_putchar_skip + + early_putchar_print: + + /* Print character */ + + movb $0x0e, %ah /* black background, yellow foreground */ + stosw + inc %bx + + early_putchar_skip: + + /* Sanity check for the cursor on the last line */ + cmp $2000, %bx + jb early_putchar_no_scroll + + /* Scroll the screen (24 rows) */ + movl $(PA2KA(0xb80a0)), %esi + movl $(PA2KA(0xb8000)), %edi + movl $960, %ecx + rep movsl + + /* Clear the 24th row */ + xorl %eax, %eax + movl $40, %ecx + rep stosl + + /* Go to row 24 */ + movw $1920, %bx + + early_putchar_no_scroll: + + /* Write bits 8 - 15 of the cursor address */ + movw $0x3d4, %dx + movb $0xe, %al + outb %al, %dx + + movw $0x3d5, %dx + movb %bh, %al + outb %al, %dx + + /* Write bits 0 - 7 of the cursor address */ + movw $0x3d4, %dx + movb $0xf, %al + outb %al, %dx + + movw $0x3d5, %dx + movb %bl, %al + outb %al, %dx + + /* Epilogue, restore preserved registers */ + popl %edi + popl %esi + popl %ebx + leave + +#endif + + ret + Index: kernel/arch/ia32/src/bios/bios.c =================================================================== --- kernel/arch/ia32/src/bios/bios.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/src/bios/bios.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup ia32 +/** @addtogroup ia32 * @{ */ Index: kernel/arch/ia32/src/boot/boot.S =================================================================== --- kernel/arch/ia32/src/boot/boot.S (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/src/boot/boot.S (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -1,30 +1,30 @@ -# -# Copyright (c) 2001-2004 Jakub Jermar -# Copyright (c) 2005-2006 Martin Decky -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# +/* + * Copyright (c) 2001 Jakub Jermar + * Copyright (c) 2005 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ #include @@ -34,9 +34,29 @@ #include -#define START_STACK (BOOT_OFFSET - BOOT_STACK_SIZE) +#define START_STACK (BOOT_OFFSET - BOOT_STACK_SIZE) .section K_TEXT_START, "ax" .code32 + +.macro pm_error msg + movl \msg, %esi + jmp pm_error_halt +.endm + +.macro pm_status msg +#ifdef CONFIG_EGA + pushl %esi + movl \msg, %esi + call pm_early_puts + popl %esi +#endif +.endm + +.macro pm2_status msg + pushl \msg + call early_puts +.endm + .align 4 .global multiboot_image_start @@ -44,5 +64,5 @@ .long MULTIBOOT_HEADER_MAGIC .long MULTIBOOT_HEADER_FLAGS - .long -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS) # checksum + .long -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS) /* checksum */ .long multiboot_header .long unmapped_ktext_start @@ -53,12 +73,17 @@ multiboot_image_start: cld - movl $START_STACK, %esp # initialize stack pointer - lgdt KA2PA(bootstrap_gdtr) # initialize Global Descriptor Table register - + + /* Initialize stack pointer */ + movl $START_STACK, %esp + + /* Initialize Global Descriptor Table register */ + lgdtl KA2PA(bootstrap_gdtr) + + /* Kernel data + stack */ movw $gdtselector(KDATA_DES), %cx movw %cx, %es movw %cx, %fs movw %cx, %gs - movw %cx, %ds # kernel data + stack + movw %cx, %ds movw %cx, %ss @@ -66,10 +91,13 @@ multiboot_meeting_point: - movl %eax, grub_eax # save parameters from GRUB + /* Save GRUB arguments */ + movl %eax, grub_eax movl %ebx, grub_ebx + + pm_status $status_prot movl $(INTEL_CPUID_LEVEL), %eax cpuid - cmp $0x0, %eax # any function > 0? + cmp $0x0, %eax /* any function > 0? */ jbe pse_unsupported @@ -80,26 +108,31 @@ pse_unsupported: - movl $pse_msg, %esi - jmp error_halt + + pm_error $err_pse pse_supported: #include "vesa_prot.inc" - - # map kernel and turn paging on + + /* Map kernel and turn paging on */ call map_kernel - # call arch_pre_main(grub_eax, grub_ebx) + /* Create the first stack frame */ + pushl $0 + movl %esp, %ebp + + pm2_status $status_prot2 + + /* Call arch_pre_main(grub_eax, grub_ebx) */ pushl grub_ebx pushl grub_eax call arch_pre_main - - # Create the first stack frame - pushl $0 - movl %esp, %ebp - + + pm2_status $status_main + + /* Call main_bsp() */ call main_bsp - # not reached + /* Not reached */ cli hlt0: @@ -107,13 +140,15 @@ jmp hlt0 +/** Setup mapping for the kernel. + * + * Setup mapping for both the unmapped and mapped sections + * of the kernel. For simplicity, we map the entire 4G space. + * + */ .global map_kernel map_kernel: - # - # Here we setup mapping for both the unmapped and mapped sections of the kernel. - # For simplicity, we map the entire 4G space. - # movl %cr4, %ecx - orl $(1 << 4), %ecx # turn PSE on - andl $(~(1 << 5)), %ecx # turn PAE off + orl $(1 << 4), %ecx /* PSE on */ + andl $(~(1 << 5)), %ecx /* PAE off */ movl %ecx, %cr4 @@ -126,6 +161,8 @@ movl $((1 << 7) | (1 << 1) | (1 << 0)), %eax orl %ebx, %eax - movl %eax, (%esi, %ecx, 4) # mapping 0x00000000 + %ecx * 4M => 0x00000000 + %ecx * 4M - movl %eax, (%edi, %ecx, 4) # mapping 0x80000000 + %ecx * 4M => 0x00000000 + %ecx * 4M + /* Mapping 0x00000000 + %ecx * 4M => 0x00000000 + %ecx * 4M */ + movl %eax, (%esi, %ecx, 4) + /* Mapping 0x80000000 + %ecx * 4M => 0x00000000 + %ecx * 4M */ + movl %eax, (%edi, %ecx, 4) addl $(4 * 1024 * 1024), %ebx @@ -137,14 +174,25 @@ movl %cr0, %ebx - orl $(1 << 31), %ebx # turn paging on + orl $(1 << 31), %ebx /* paging on */ movl %ebx, %cr0 ret -# Print string from %esi to EGA display (in red) and halt -error_halt: - movl $0xb8000, %edi # base of EGA text mode memory +/** Print string to EGA display (in light red) and halt. + * + * Should be executed from 32 bit protected mode with paging + * turned off. Stack is not required. This routine is used even + * if CONFIG_EGA is not enabled. Since we are going to halt the + * CPU anyway, it is always better to at least try to print + * some hints. + * + * @param %esi NULL-terminated string to print. + * + */ +pm_error_halt: + movl $0xb8000, %edi /* base of EGA text mode memory */ xorl %eax, %eax - movw $0x3d4, %dx # read bits 8 - 15 of the cursor address + /* Read bits 8 - 15 of the cursor address */ + movw $0x3d4, %dx movb $0xe, %al outb %al, %dx @@ -154,5 +202,6 @@ shl $8, %ax - movw $0x3d4, %dx # read bits 0 - 7 of the cursor address + /* Read bits 0 - 7 of the cursor address */ + movw $0x3d4, %dx movb $0xf, %al outb %al, %dx @@ -161,10 +210,11 @@ inb %dx, %al - cmp $1920, %ax - jbe cursor_ok - - movw $1920, %ax # sanity check for the cursor on the last line - - cursor_ok: + /* Sanity check for the cursor on screen */ + cmp $2000, %ax + jb err_cursor_ok + + movw $1998, %ax + + err_cursor_ok: movw %ax, %bx @@ -172,16 +222,40 @@ addl %eax, %edi - movw $0x0c00, %ax # black background, light red foreground - - ploop: + err_ploop: lodsb + cmp $0, %al - je ploop_end + je err_ploop_end + + movb $0x0c, %ah /* black background, light red foreground */ stosw + + /* Sanity check for the cursor on the last line */ inc %bx - jmp ploop - ploop_end: - - movw $0x3d4, %dx # write bits 8 - 15 of the cursor address + cmp $2000, %bx + jb err_ploop + + /* Scroll the screen (24 rows) */ + movl %esi, %edx + movl $0xb80a0, %esi + movl $0xb8000, %edi + movl $960, %ecx + rep movsl + + /* Clear the 24th row */ + xorl %eax, %eax + movl $40, %ecx + rep stosl + + /* Go to row 24 */ + movl %edx, %esi + movl $0xb8f00, %edi + movw $1920, %bx + + jmp err_ploop + err_ploop_end: + + /* Write bits 8 - 15 of the cursor address */ + movw $0x3d4, %dx movb $0xe, %al outb %al, %dx @@ -191,5 +265,6 @@ outb %al, %dx - movw $0x3d4, %dx # write bits 0 - 7 of the cursor address + /* Write bits 0 - 7 of the cursor address */ + movw $0x3d4, %dx movb $0xf, %al outb %al, %dx @@ -204,4 +279,232 @@ jmp hlt1 +/** Print string to EGA display (in light green). + * + * Should be called from 32 bit protected mode with paging + * turned off. A stack space of at least 24 bytes is required, + * but the function does not establish a stack frame. + * + * Macros such as pm_status take care that this function + * is used only when CONFIG_EGA is enabled. + * + * @param %esi NULL-terminated string to print. + * + */ +pm_early_puts: + pushl %eax + pushl %ebx + pushl %ecx + pushl %edx + pushl %edi + + movl $0xb8000, %edi /* base of EGA text mode memory */ + xorl %eax, %eax + + /* Read bits 8 - 15 of the cursor address */ + movw $0x3d4, %dx + movb $0xe, %al + outb %al, %dx + + movw $0x3d5, %dx + inb %dx, %al + shl $8, %ax + + /* Read bits 0 - 7 of the cursor address */ + movw $0x3d4, %dx + movb $0xf, %al + outb %al, %dx + + movw $0x3d5, %dx + inb %dx, %al + + /* Sanity check for the cursor on screen */ + cmp $2000, %ax + jb pm_puts_cursor_ok + + movw $1998, %ax + + pm_puts_cursor_ok: + + movw %ax, %bx + shl $1, %eax + addl %eax, %edi + + pm_puts_ploop: + lodsb + + cmp $0, %al + je pm_puts_ploop_end + + movb $0x0a, %ah /* black background, light green foreground */ + stosw + + /* Sanity check for the cursor on the last line */ + inc %bx + cmp $2000, %bx + jb pm_puts_ploop + + /* Scroll the screen (24 rows) */ + movl %esi, %edx + movl $0xb80a0, %esi + movl $0xb8000, %edi + movl $960, %ecx + rep movsl + + /* Clear the 24th row */ + xorl %eax, %eax + movl $40, %ecx + rep stosl + + /* Go to row 24 */ + movl %edx, %esi + movl $0xb8f00, %edi + movw $1920, %bx + + jmp pm_puts_ploop + pm_puts_ploop_end: + + /* Write bits 8 - 15 of the cursor address */ + movw $0x3d4, %dx + movb $0xe, %al + outb %al, %dx + + movw $0x3d5, %dx + movb %bh, %al + outb %al, %dx + + /* Write bits 0 - 7 of the cursor address */ + movw $0x3d4, %dx + movb $0xf, %al + outb %al, %dx + + movw $0x3d5, %dx + movb %bl, %al + outb %al, %dx + + popl %edi + popl %edx + popl %ecx + popl %ebx + popl %eax + + ret + +/** Print string to EGA display. + * + * Should be called from 32 bit protected mode (with paging + * enabled and stack established). This function is ABI compliant. + * + * If CONFIG_EGA is undefined or CONFIG_FB is defined + * then this function does nothing. + * + * @param %ebp+0x08 NULL-terminated string to print. + * + */ +early_puts: + +#if ((defined(CONFIG_EGA)) && (!defined(CONFIG_FB))) + + /* Prologue, save preserved registers */ + pushl %ebp + movl %esp, %ebp + pushl %ebx + pushl %esi + pushl %edi + + movl 0x08(%ebp), %esi + movl $(PA2KA(0xb8000)), %edi /* base of EGA text mode memory */ + xorl %eax, %eax + + /* Read bits 8 - 15 of the cursor address */ + movw $0x3d4, %dx + movb $0xe, %al + outb %al, %dx + + movw $0x3d5, %dx + inb %dx, %al + shl $8, %ax + + /* Read bits 0 - 7 of the cursor address */ + movw $0x3d4, %dx + movb $0xf, %al + outb %al, %dx + + movw $0x3d5, %dx + inb %dx, %al + + /* Sanity check for the cursor on screen */ + cmp $2000, %ax + jb early_puts_cursor_ok + + movw $1998, %ax + + early_puts_cursor_ok: + + movw %ax, %bx + shl $1, %eax + addl %eax, %edi + + early_puts_ploop: + lodsb + + cmp $0, %al + je early_puts_ploop_end + + movb $0x0e, %ah /* black background, yellow foreground */ + stosw + + /* Sanity check for the cursor on the last line */ + inc %bx + cmp $2000, %bx + jb early_puts_ploop + + /* Scroll the screen (24 rows) */ + movl %esi, %edx + movl $(PA2KA(0xb80a0)), %esi + movl $(PA2KA(0xb8000)), %edi + movl $960, %ecx + rep movsl + + /* Clear the 24th row */ + xorl %eax, %eax + movl $40, %ecx + rep stosl + + /* Go to row 24 */ + movl %edx, %esi + movl $(PA2KA(0xb8f00)), %edi + movw $1920, %bx + + jmp early_puts_ploop + early_puts_ploop_end: + + /* Write bits 8 - 15 of the cursor address */ + movw $0x3d4, %dx + movb $0xe, %al + outb %al, %dx + + movw $0x3d5, %dx + movb %bh, %al + outb %al, %dx + + /* Write bits 0 - 7 of the cursor address */ + movw $0x3d4, %dx + movb $0xf, %al + outb %al, %dx + + movw $0x3d5, %dx + movb %bl, %al + outb %al, %dx + + /* Epilogue, restore preserved registers */ + popl %edi + popl %esi + popl %ebx + leave + +#endif + + ret + #include "vesa_real.inc" @@ -218,5 +521,17 @@ .long 0 -pse_msg: +err_pse: .asciz "Page Size Extension not supported. System halted." +status_prot: + .asciz "[prot] " +status_vesa_copy: + .asciz "[vesa_copy] " +status_grub_cmdline: + .asciz "[grub_cmdline] " +status_vesa_real: + .asciz "[vesa_real] " +status_prot2: + .asciz "[prot2] " +status_main: + .asciz "[main] " Index: kernel/arch/ia32/src/boot/vesa_prot.inc =================================================================== --- kernel/arch/ia32/src/boot/vesa_prot.inc (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/src/boot/vesa_prot.inc (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -5,5 +5,7 @@ #define MBINFO_OFFSET_CMDLINE 16 - # copy real mode VESA initialization code + /* Copy real mode VESA initialization code */ + + pm_status $status_vesa_copy mov $vesa_init, %esi @@ -12,5 +14,7 @@ rep movsb - # check for GRUB command line + /* Check for GRUB command line */ + + pm_status $status_grub_cmdline mov grub_eax, %eax @@ -23,5 +27,5 @@ jnc no_cmdline - # skip the kernel path in command line + /* Skip the kernel path in command line */ mov MBINFO_OFFSET_CMDLINE(%ebx), %esi @@ -52,5 +56,5 @@ space_loop_done: - # copy at most 23 characters from command line + /* Copy at most 23 characters from command line */ mov $VESA_INIT_SEGMENT << 4, %edi @@ -68,5 +72,5 @@ cmd_loop_done: - # zero termination + /* Zero termination */ xor %eax, %eax @@ -75,5 +79,7 @@ no_cmdline: - # jump to the real mode + /* Jump to the real mode */ + + pm_status $status_vesa_real mov $VESA_INIT_SEGMENT << 4, %edi @@ -81,5 +87,5 @@ vesa_meeting_point: - # returned back to protected mode + /* Returned back to protected mode */ mov %ax, KA2PA(vesa_scanline) Index: kernel/arch/ia32/src/boot/vesa_real.inc =================================================================== --- kernel/arch/ia32/src/boot/vesa_real.inc (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/src/boot/vesa_real.inc (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -31,5 +31,5 @@ vesa_init: jmp $gdtselector(VESA_INIT_DES), $vesa_init_real - vesa_init - + .code16 vesa_init_real: @@ -55,5 +55,5 @@ pushl %eax - # parse default mode string + /* Parse default mode string */ mov $default_mode - vesa_init, %di @@ -65,5 +65,5 @@ mov (%di), %al - # check for digit + /* Check for digit */ cmp $'0', %al @@ -75,5 +75,5 @@ sub $'0', %al - # multiply default_width by 10 and add digit + /* Multiply default_width by 10 and add digit */ mov default_width - vesa_init, %bx @@ -96,5 +96,5 @@ mov (%di), %al - # check for digit + /* Check for digit */ cmp $'0', %al @@ -106,5 +106,5 @@ sub $'0', %al - # multiply default_height by 10 and add digit + /* Multiply default_height by 10 and add digit */ mov default_height - vesa_init, %bx @@ -127,5 +127,5 @@ mov (%di), %al - # check for digit + /* Check for digit */ cmp $'0', %al @@ -137,5 +137,5 @@ sub $'0', %al - # multiply default_bpp by 10 and add digit + /* Multiply default_bpp by 10 and add digit */ mov default_bpp - vesa_init, %bx @@ -167,5 +167,6 @@ next_mode: - # try next mode + /* Try next mode */ + mov %gs:(%si), %cx cmp $VESA_END_OF_MODES, %cx @@ -186,5 +187,8 @@ jne no_mode - # check for proper attributes (supported, color, graphics, linear framebuffer) + /* + * Check for proper attributes (supported, + * color, graphics, linear framebuffer). + */ mov VESA_MODE_ATTRIBUTES_OFFSET(%di), %ax @@ -193,5 +197,5 @@ jne next_mode - # check for proper resolution + /* Check for proper resolution */ mov default_width - vesa_init, %ax @@ -203,5 +207,5 @@ jne next_mode - # check for proper bpp + /* Check for proper bpp */ mov default_bpp - vesa_init, %al @@ -213,5 +217,5 @@ jne next_mode - # for 24 bpp modes accept also 32 bit bpp + /* For 24 bpp modes accept also 32 bit bpp */ mov $32, %al @@ -230,5 +234,5 @@ jnz no_mode - # set 3:2:3 VGA palette + /* Set 3:2:3 VGA palette */ mov VESA_MODE_BPP_OFFSET(%di), %al @@ -241,8 +245,10 @@ mov $0x100, %ecx - bt $5, %ax # test if VGA compatible registers are present + /* Test if VGA compatible registers are present */ + bt $5, %ax jnc vga_compat - # try VESA routine to set palette + /* Use VESA routine to set the palette */ + mov $VESA_SET_PALETTE, %ax xor %bl, %bl @@ -254,14 +260,16 @@ vga_compat: - # try VGA registers to set palette - movw $0x3c6, %dx # set palette mask + + /* Use VGA registers to set the palette */ + + movw $0x3c6, %dx /* set palette mask */ movb $0xff, %al outb %al, %dx - movw $0x3c8, %dx # first index to set + movw $0x3c8, %dx /* first index to set */ xor %al, %al outb %al, %dx - movw $0x3c9, %dx # data port + movw $0x3c9, %dx /* data port */ vga_loop: @@ -284,10 +292,12 @@ vga_not_set: - # store mode parameters - # eax = bpp[8] scanline[16] - # ebx = width[16] height[16] - # edx = red_mask[8] red_pos[8] green_mask[8] green_pos[8] - # esi = blue_mask[8] blue_pos[8] - # edi = linear frame buffer + /* + * Store mode parameters: + * eax = bpp[8] scanline[16] + * ebx = width[16] height[16] + * edx = red_mask[8] red_pos[8] green_mask[8] green_pos[8] + * esi = blue_mask[8] blue_pos[8] + * edi = linear frame buffer + */ mov VESA_MODE_BPP_OFFSET(%di), %al @@ -328,5 +338,7 @@ no_mode: - # no prefered mode found + + /* No prefered mode found */ + mov $0x111, %cx push %di @@ -339,13 +351,15 @@ cmp $VESA_OK, %al jnz text_mode - jz set_mode # force relative jump + jz set_mode /* force relative jump */ text_mode: - # reset to EGA text mode (because of problems with VESA) + + /* Reset to EGA text mode (because of problems with VESA) */ + mov $0x0003, %ax int $0x10 mov $0xffffffff, %edi xor %ax, %ax - jz vesa_leave_real # force relative jump + jz vesa_leave_real /* force relative jump */ vga323: Index: kernel/arch/ia32/src/boot/vesa_ret.inc =================================================================== --- kernel/arch/ia32/src/boot/vesa_ret.inc (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/src/boot/vesa_ret.inc (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -1,12 +1,16 @@ .code32 vesa_init_protected: + cld + + /* Initialize stack pointer */ + movl $START_STACK, %esp + + /* Kernel data + stack */ movw $gdtselector(KDATA_DES), %cx movw %cx, %es movw %cx, %fs movw %cx, %gs - movw %cx, %ds # kernel data + stack + movw %cx, %ds movw %cx, %ss - movl $START_STACK, %esp # initialize stack pointer - jmpl $gdtselector(KTEXT_DES), $vesa_meeting_point Index: kernel/arch/ia32/src/debug/panic.s =================================================================== --- kernel/arch/ia32/src/debug/panic.s (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ (revision ) @@ -1,34 +1,0 @@ -# -# Copyright (c) 2001-2004 Jakub Jermar -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -.text -.global panic_printf - -panic_printf: - movl $halt, (%esp) # fake stack to make printf return to halt - jmp printf Index: kernel/arch/ia32/src/ia32.c =================================================================== --- kernel/arch/ia32/src/ia32.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/src/ia32.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -139,5 +139,5 @@ { #ifdef CONFIG_SMP - if (config.cpu_active > 1) { + if (config.cpu_active > 1) { l_apic_init(); l_apic_debug(); Index: kernel/arch/ia32/src/interrupt.c =================================================================== --- kernel/arch/ia32/src/interrupt.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/src/interrupt.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -63,21 +63,23 @@ void (* eoi_function)(void) = NULL; -void decode_istate(istate_t *istate) -{ - const char *symbol = symtab_fmt_name_lookup(istate->eip); - - if (CPU) - printf("----------------EXCEPTION OCCURED (cpu%u)----------------\n", CPU->id); - else - printf("----------------EXCEPTION OCCURED----------------\n"); - - printf("%%eip: %#lx (%s)\n", istate->eip, symbol); - printf("ERROR_WORD=%#lx\n", istate->error_word); - printf("%%cs=%#lx,flags=%#lx\n", istate->cs, istate->eflags); - printf("%%eax=%#lx, %%ecx=%#lx, %%edx=%#lx, %%esp=%p\n", istate->eax, istate->ecx, istate->edx, &istate->stack[0]); - printf("stack: %#lx, %#lx, %#lx, %#lx\n", istate->stack[0], istate->stack[1], istate->stack[2], istate->stack[3]); - printf(" %#lx, %#lx, %#lx, %#lx\n", istate->stack[4], istate->stack[5], istate->stack[6], istate->stack[7]); - - stack_trace_istate(istate); +void istate_decode(istate_t *istate) +{ + printf("error_word=%p\n", istate->error_word); + printf("eflags=%p\n", istate->eflags); + + printf("cs =%p\tds =%p\tes =%p\n", istate->cs, istate->ds, istate->es); + printf("fs =%p\tgs =%p", istate->fs, istate->gs); + if (istate_from_uspace(istate)) + printf("\tss =%p\n", istate->ss); + else + printf("\n"); + + printf("eax=%p\tebx=%p\tecx=%p\n", istate->eax, istate->ebx, + istate->ecx); + printf("edx=%p\tedi=%p\tesi=%p\n", istate->edx, istate->edi, + istate->esi); + printf("ebp=%p\tesp=%p\teip=%p\n", istate->ebp, + istate_from_uspace(istate) ? istate->esp : (uintptr_t) &istate->esp, + istate->eip); } @@ -94,7 +96,5 @@ { fault_if_from_uspace(istate, "Unserviced interrupt: %u.", n); - - decode_istate(istate); - panic("Unserviced interrupt: %u.", n); + panic_badtrap(istate, n, "Unserviced interrupt: %u.", n); } @@ -102,7 +102,5 @@ { fault_if_from_uspace(istate, "Divide error."); - - decode_istate(istate); - panic("Divide error."); + panic_badtrap(istate, n, "Divide error."); } @@ -128,7 +126,5 @@ fault_if_from_uspace(istate, "General protection fault."); } - - decode_istate(istate); - panic("General protection fault."); + panic_badtrap(istate, n, "General protection fault."); } @@ -136,7 +132,5 @@ { fault_if_from_uspace(istate, "Stack fault."); - - decode_istate(istate); - panic("Stack fault."); + panic_badtrap(istate, n, "Stack fault."); } @@ -149,10 +143,7 @@ ); - fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR: %#zx.", + fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR=%#0.8x.", (unative_t) mxcsr); - - decode_istate(istate); - printf("MXCSR: %#lx\n", mxcsr); - panic("SIMD FP exception(19)."); + panic_badtrap(istate, n, "SIMD FP exception, MXCSR=%#0.8x"); } @@ -164,5 +155,5 @@ #else fault_if_from_uspace(istate, "FPU fault."); - panic("FPU fault."); + panic_badtrap(istate, n, "FPU fault."); #endif } Index: kernel/arch/ia32/src/mm/as.c =================================================================== --- kernel/arch/ia32/src/mm/as.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/src/mm/as.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup ia32mm +/** @addtogroup ia32mm * @{ */ Index: kernel/arch/ia32/src/mm/frame.c =================================================================== --- kernel/arch/ia32/src/mm/frame.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/src/mm/frame.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -47,4 +47,7 @@ #include +#define PHYSMEM_LIMIT32 0x07c000000ull +#define PHYSMEM_LIMIT64 0x200000000ull + size_t hardcoded_unmapped_ktext_size = 0; size_t hardcoded_unmapped_kdata_size = 0; @@ -55,5 +58,5 @@ { unsigned int i; - + for (i = 0; i < e820counter; i++) { uint64_t base = e820table[i].base_address; @@ -61,20 +64,59 @@ #ifdef __32_BITS__ - /* Ignore physical memory above 4 GB */ - if ((base >> 32) != 0) + /* + * XXX FIXME: + * + * Ignore zones which start above PHYSMEM_LIMIT32 + * or clip zones which go beyond PHYSMEM_LIMIT32. + * + * The PHYSMEM_LIMIT32 (2 GB - 64 MB) is a rather + * arbitrary constant which allows to have at + * least 64 MB in the kernel address space to + * map hardware resources. + * + * The kernel uses fixed 1:1 identity mapping + * of the physical memory with 2:2 GB split. + * This is a severe limitation of the current + * kernel memory management. + * + */ + + if (base > PHYSMEM_LIMIT32) continue; - /* Clip regions above 4 GB */ - if (((base + size) >> 32) != 0) - size = 0xffffffff - base; -#endif - - pfn_t pfn; - size_t count; + if (base + size > PHYSMEM_LIMIT32) + size = PHYSMEM_LIMIT32 - base; +#endif + +#ifdef __64_BITS__ + /* + * XXX FIXME: + * + * Ignore zones which start above PHYSMEM_LIMIT64 + * or clip zones which go beyond PHYSMEM_LIMIT64. + * + * The PHYSMEM_LIMIT64 (8 GB) is the size of the + * fixed 1:1 identically mapped physical memory + * accessible during the bootstrap process. + * This is a severe limitation of the current + * kernel memory management. + * + */ + + if (base > PHYSMEM_LIMIT64) + continue; + + if (base + size > PHYSMEM_LIMIT64) + size = PHYSMEM_LIMIT64 - base; +#endif if (e820table[i].type == MEMMAP_MEMORY_AVAILABLE) { - /* To be safe, make available zone possibly smaller */ - pfn = ADDR2PFN(ALIGN_UP(base, FRAME_SIZE)); - count = SIZE2FRAMES(ALIGN_DOWN(size, FRAME_SIZE)); + /* To be safe, make the available zone possibly smaller */ + uint64_t new_base = ALIGN_UP(base, FRAME_SIZE); + uint64_t new_size = ALIGN_DOWN(size - (new_base - base), + FRAME_SIZE); + + pfn_t pfn = ADDR2PFN(new_base); + size_t count = SIZE2FRAMES(new_size); pfn_t conf; @@ -87,22 +129,26 @@ // XXX this has to be removed - if (last_frame < ALIGN_UP(base + size, FRAME_SIZE)) - last_frame = ALIGN_UP(base + size, FRAME_SIZE); + if (last_frame < ALIGN_UP(new_base + new_size, FRAME_SIZE)) + last_frame = ALIGN_UP(new_base + new_size, FRAME_SIZE); } if (e820table[i].type == MEMMAP_MEMORY_RESERVED) { - /* To be safe, make reserved zone possibly larger */ - pfn = ADDR2PFN(ALIGN_DOWN(base, FRAME_SIZE)); - count = SIZE2FRAMES(ALIGN_UP(size, FRAME_SIZE)); - - zone_create(pfn, count, 0, ZONE_RESERVED); + /* To be safe, make the reserved zone possibly larger */ + uint64_t new_base = ALIGN_DOWN(base, FRAME_SIZE); + uint64_t new_size = ALIGN_UP(size + (base - new_base), + FRAME_SIZE); + + zone_create(ADDR2PFN(new_base), SIZE2FRAMES(new_size), 0, + ZONE_RESERVED); } if (e820table[i].type == MEMMAP_MEMORY_ACPI) { - /* To be safe, make firmware zone possibly larger */ - pfn = ADDR2PFN(ALIGN_DOWN(base, (uintptr_t) FRAME_SIZE)); - count = SIZE2FRAMES(ALIGN_UP(size, (uintptr_t) FRAME_SIZE)); - - zone_create(pfn, count, 0, ZONE_FIRMWARE); + /* To be safe, make the firmware zone possibly larger */ + uint64_t new_base = ALIGN_DOWN(base, FRAME_SIZE); + uint64_t new_size = ALIGN_UP(size + (base - new_base), + FRAME_SIZE); + + zone_create(ADDR2PFN(new_base), SIZE2FRAMES(new_size), 0, + ZONE_FIRMWARE); } } @@ -121,10 +167,9 @@ { unsigned int i; - const char *name; + printf("[base ] [size ] [name ]\n"); - printf("Base Size Name\n"); - printf("------------------ ------------------ ---------\n"); - for (i = 0; i < e820counter; i++) { + const char *name; + if (e820table[i].type <= MEMMAP_MEMORY_UNUSABLE) name = e820names[e820table[i].type]; @@ -132,5 +177,5 @@ name = "invalid"; - printf("%#18llx %#18llx %s\n", e820table[i].base_address, + printf("%#018" PRIx64 " %#018" PRIx64" %s\n", e820table[i].base_address, e820table[i].size, name); } @@ -150,5 +195,5 @@ hardcoded_unmapped_kdata_size)); #endif - + init_e820_memory(minconf); Index: kernel/arch/ia32/src/mm/page.c =================================================================== --- kernel/arch/ia32/src/mm/page.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/src/mm/page.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -115,8 +115,5 @@ if (as_page_fault(page, access, istate) == AS_PF_FAULT) { fault_if_from_uspace(istate, "Page fault: %#x.", page); - - decode_istate(istate); - printf("page fault address: %#lx\n", page); - panic("Page fault."); + panic_memtrap(istate, access, page, "Page fault."); } } Index: kernel/arch/ia32/src/mm/tlb.c =================================================================== --- kernel/arch/ia32/src/mm/tlb.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/src/mm/tlb.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup ia32mm +/** @addtogroup ia32mm * @{ */ Index: kernel/arch/ia32/src/pm.c =================================================================== --- kernel/arch/ia32/src/pm.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/src/pm.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -139,10 +139,72 @@ d->access |= DPL_USER; } - - idt_setoffset(d, ((uintptr_t) interrupt_handlers) + - i * interrupt_handler_size); } -} - + + d = &idt[0]; + idt_setoffset(d++, (uintptr_t) &int_0); + idt_setoffset(d++, (uintptr_t) &int_1); + idt_setoffset(d++, (uintptr_t) &int_2); + idt_setoffset(d++, (uintptr_t) &int_3); + idt_setoffset(d++, (uintptr_t) &int_4); + idt_setoffset(d++, (uintptr_t) &int_5); + idt_setoffset(d++, (uintptr_t) &int_6); + idt_setoffset(d++, (uintptr_t) &int_7); + idt_setoffset(d++, (uintptr_t) &int_8); + idt_setoffset(d++, (uintptr_t) &int_9); + idt_setoffset(d++, (uintptr_t) &int_10); + idt_setoffset(d++, (uintptr_t) &int_11); + idt_setoffset(d++, (uintptr_t) &int_12); + idt_setoffset(d++, (uintptr_t) &int_13); + idt_setoffset(d++, (uintptr_t) &int_14); + idt_setoffset(d++, (uintptr_t) &int_15); + idt_setoffset(d++, (uintptr_t) &int_16); + idt_setoffset(d++, (uintptr_t) &int_17); + idt_setoffset(d++, (uintptr_t) &int_18); + idt_setoffset(d++, (uintptr_t) &int_19); + idt_setoffset(d++, (uintptr_t) &int_20); + idt_setoffset(d++, (uintptr_t) &int_21); + idt_setoffset(d++, (uintptr_t) &int_22); + idt_setoffset(d++, (uintptr_t) &int_23); + idt_setoffset(d++, (uintptr_t) &int_24); + idt_setoffset(d++, (uintptr_t) &int_25); + idt_setoffset(d++, (uintptr_t) &int_26); + idt_setoffset(d++, (uintptr_t) &int_27); + idt_setoffset(d++, (uintptr_t) &int_28); + idt_setoffset(d++, (uintptr_t) &int_29); + idt_setoffset(d++, (uintptr_t) &int_30); + idt_setoffset(d++, (uintptr_t) &int_31); + idt_setoffset(d++, (uintptr_t) &int_32); + idt_setoffset(d++, (uintptr_t) &int_33); + idt_setoffset(d++, (uintptr_t) &int_34); + idt_setoffset(d++, (uintptr_t) &int_35); + idt_setoffset(d++, (uintptr_t) &int_36); + idt_setoffset(d++, (uintptr_t) &int_37); + idt_setoffset(d++, (uintptr_t) &int_38); + idt_setoffset(d++, (uintptr_t) &int_39); + idt_setoffset(d++, (uintptr_t) &int_40); + idt_setoffset(d++, (uintptr_t) &int_41); + idt_setoffset(d++, (uintptr_t) &int_42); + idt_setoffset(d++, (uintptr_t) &int_43); + idt_setoffset(d++, (uintptr_t) &int_44); + idt_setoffset(d++, (uintptr_t) &int_45); + idt_setoffset(d++, (uintptr_t) &int_46); + idt_setoffset(d++, (uintptr_t) &int_47); + idt_setoffset(d++, (uintptr_t) &int_48); + idt_setoffset(d++, (uintptr_t) &int_49); + idt_setoffset(d++, (uintptr_t) &int_50); + idt_setoffset(d++, (uintptr_t) &int_51); + idt_setoffset(d++, (uintptr_t) &int_52); + idt_setoffset(d++, (uintptr_t) &int_53); + idt_setoffset(d++, (uintptr_t) &int_54); + idt_setoffset(d++, (uintptr_t) &int_55); + idt_setoffset(d++, (uintptr_t) &int_56); + idt_setoffset(d++, (uintptr_t) &int_57); + idt_setoffset(d++, (uintptr_t) &int_58); + idt_setoffset(d++, (uintptr_t) &int_59); + idt_setoffset(d++, (uintptr_t) &int_60); + idt_setoffset(d++, (uintptr_t) &int_61); + idt_setoffset(d++, (uintptr_t) &int_62); + idt_setoffset(d++, (uintptr_t) &int_63); +} /* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */ Index: kernel/arch/ia32/src/smp/apic.c =================================================================== --- kernel/arch/ia32/src/smp/apic.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/src/smp/apic.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -76,4 +76,6 @@ uint32_t apic_id_mask = 0; +uint8_t bsp_l_apic = 0; + static irq_t l_apic_timer_irq; @@ -154,4 +156,17 @@ } +/** Get Local APIC ID. + * + * @return Local APIC ID. + * + */ +static uint8_t l_apic_id(void) +{ + l_apic_id_t idreg; + + idreg.value = l_apic[L_APIC_ID]; + return idreg.apic_id; +} + /** Initialize APIC on BSP. */ void apic_init(void) @@ -208,4 +223,6 @@ l_apic_init(); l_apic_debug(); + + bsp_l_apic = l_apic_id(); } @@ -460,33 +477,31 @@ { #ifdef LAPIC_VERBOSE - printf("LVT on cpu%" PRIs ", LAPIC ID: %" PRIu8 "\n", CPU->id, l_apic_id()); + printf("LVT on cpu%" PRIs ", LAPIC ID: %" PRIu8 "\n", + CPU->id, l_apic_id()); lvt_tm_t tm; tm.value = l_apic[LVT_Tm]; - printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); + printf("LVT Tm: vector=%" PRIu8 ", %s, %s, %s\n", + tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], + tm_mode_str[tm.mode]); lvt_lint_t lint; lint.value = l_apic[LVT_LINT0]; - printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); - lint.value = l_apic[LVT_LINT1]; - printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); + printf("LVT LINT0: vector=%" PRIu8 ", %s, %s, %s, irr=%u, %s, %s\n", + tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], + intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], + mask_str[lint.masked]); + + lint.value = l_apic[LVT_LINT1]; + printf("LVT LINT1: vector=%" PRIu8 ", %s, %s, %s, irr=%u, %s, %s\n", + tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], + intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], + mask_str[lint.masked]); lvt_error_t error; error.value = l_apic[LVT_Err]; - printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); + printf("LVT Err: vector=%" PRIu8 ", %s, %s\n", error.vector, + delivs_str[error.delivs], mask_str[error.masked]); #endif -} - -/** Get Local APIC ID. - * - * @return Local APIC ID. - * - */ -uint8_t l_apic_id(void) -{ - l_apic_id_t idreg; - - idreg.value = l_apic[L_APIC_ID]; - return idreg.apic_id; } Index: kernel/arch/ia32/src/smp/mps.c =================================================================== --- kernel/arch/ia32/src/smp/mps.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/src/smp/mps.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup ia32 +/** @addtogroup ia32 * @{ */ @@ -52,81 +52,80 @@ */ -#define FS_SIGNATURE 0x5f504d5f -#define CT_SIGNATURE 0x504d4350 - -static int mps_fs_check(uint8_t *base); -static int mps_ct_check(void); - -static int configure_via_ct(void); -static int configure_via_default(uint8_t n); - -static int ct_processor_entry(struct __processor_entry *pr); -static void ct_bus_entry(struct __bus_entry *bus); -static void ct_io_apic_entry(struct __io_apic_entry *ioa); -static void ct_io_intr_entry(struct __io_intr_entry *iointr); -static void ct_l_intr_entry(struct __l_intr_entry *lintr); - -static void ct_extended_entries(void); +#define FS_SIGNATURE 0x5f504d5f +#define CT_SIGNATURE 0x504d4350 static struct mps_fs *fs; static struct mps_ct *ct; -struct __processor_entry *processor_entries = NULL; -struct __bus_entry *bus_entries = NULL; -struct __io_apic_entry *io_apic_entries = NULL; -struct __io_intr_entry *io_intr_entries = NULL; -struct __l_intr_entry *l_intr_entries = NULL; - -unsigned int processor_entry_cnt = 0; -unsigned int bus_entry_cnt = 0; -unsigned int io_apic_entry_cnt = 0; -unsigned int io_intr_entry_cnt = 0; -unsigned int l_intr_entry_cnt = 0; - -/* - * Implementation of IA-32 SMP configuration interface. - */ -static size_t get_cpu_count(void); -static bool is_cpu_enabled(size_t i); -static bool is_bsp(size_t i); -static uint8_t get_cpu_apic_id(size_t i); -static int mps_irq_to_pin(unsigned int irq); - +static struct __processor_entry *processor_entries = NULL; +static struct __bus_entry *bus_entries = NULL; +static struct __io_apic_entry *io_apic_entries = NULL; +static struct __io_intr_entry *io_intr_entries = NULL; +static struct __l_intr_entry *l_intr_entries = NULL; + +static size_t io_apic_cnt = 0; + +static size_t processor_entry_cnt = 0; +static size_t bus_entry_cnt = 0; +static size_t io_apic_entry_cnt = 0; +static size_t io_intr_entry_cnt = 0; +static size_t l_intr_entry_cnt = 0; + +static uint8_t mps_cpu_apic_id(size_t i) +{ + ASSERT(i < processor_entry_cnt); + + return processor_entries[i].l_apic_id; +} + +static bool mps_cpu_enabled(size_t i) +{ + ASSERT(i < processor_entry_cnt); + + /* + * FIXME: The current local APIC driver limits usable + * CPU IDs to 8. + * + */ + if (i > 7) + return false; + + return (bool) ((processor_entries[i].cpu_flags & 0x01) == 0x01); +} + +static bool mps_cpu_bootstrap(size_t i) +{ + ASSERT(i < processor_entry_cnt); + + return (bool) ((processor_entries[i].cpu_flags & 0x02) == 0x02); +} + +static int mps_irq_to_pin(unsigned int irq) +{ + size_t i; + + for (i = 0; i < io_intr_entry_cnt; i++) { + if (io_intr_entries[i].src_bus_irq == irq && + io_intr_entries[i].intr_type == 0) + return io_intr_entries[i].dst_io_apic_pin; + } + + return -1; +} + +/** Implementation of IA-32 SMP configuration interface. + * + */ struct smp_config_operations mps_config_operations = { - .cpu_count = get_cpu_count, - .cpu_enabled = is_cpu_enabled, - .cpu_bootstrap = is_bsp, - .cpu_apic_id = get_cpu_apic_id, + .cpu_enabled = mps_cpu_enabled, + .cpu_bootstrap = mps_cpu_bootstrap, + .cpu_apic_id = mps_cpu_apic_id, .irq_to_pin = mps_irq_to_pin }; -size_t get_cpu_count(void) -{ - return processor_entry_cnt; -} - -bool is_cpu_enabled(size_t i) -{ - ASSERT(i < processor_entry_cnt); - return (bool) ((processor_entries[i].cpu_flags & 0x01) == 0x01); -} - -bool is_bsp(size_t i) -{ - ASSERT(i < processor_entry_cnt); - return (bool) ((processor_entries[i].cpu_flags & 0x02) == 0x02); -} - -uint8_t get_cpu_apic_id(size_t i) -{ - ASSERT(i < processor_entry_cnt); - return processor_entries[i].l_apic_id; -} - - -/* - * Used to check the integrity of the MP Floating Structure. - */ -int mps_fs_check(uint8_t *base) +/** Check the integrity of the MP Floating Structure. + * + */ +static bool mps_fs_check(uint8_t *base) { unsigned int i; @@ -136,112 +135,240 @@ sum = (uint8_t) (sum + base[i]); - return !sum; -} - -/* - * Used to check the integrity of the MP Configuration Table. - */ -int mps_ct_check(void) + return (sum == 0); +} + +/** Check the integrity of the MP Configuration Table. + * + */ +static bool mps_ct_check(void) { uint8_t *base = (uint8_t *) ct; uint8_t *ext = base + ct->base_table_length; uint8_t sum; - int i; - - /* count the checksum for the base table */ - for (i = 0,sum = 0; i < ct->base_table_length; i++) + uint16_t i; + + /* Compute the checksum for the base table */ + for (i = 0, sum = 0; i < ct->base_table_length; i++) sum = (uint8_t) (sum + base[i]); - + if (sum) - return 0; - - /* count the checksum for the extended table */ + return false; + + /* Compute the checksum for the extended table */ for (i = 0, sum = 0; i < ct->ext_table_length; i++) sum = (uint8_t) (sum + ext[i]); - - return sum == ct->ext_table_checksum; -} - -void mps_init(void) -{ - uint8_t *addr[2] = { NULL, (uint8_t *) PA2KA(0xf0000) }; - unsigned int i, j, length[2] = { 1024, 64 * 1024 }; - - + + return (sum == ct->ext_table_checksum); +} + +static void ct_processor_entry(struct __processor_entry *pr) +{ /* - * Find MP Floating Pointer Structure - * 1a. search first 1K of EBDA - * 1b. if EBDA is undefined, search last 1K of base memory - * 2. search 64K starting at 0xf0000 + * Ignore processors which are not marked enabled. */ - - addr[0] = (uint8_t *) PA2KA(ebda ? ebda : 639 * 1024); - for (i = 0; i < 2; i++) { - for (j = 0; j < length[i]; j += 16) { - if (*((uint32_t *) &addr[i][j]) == - FS_SIGNATURE && mps_fs_check(&addr[i][j])) { - fs = (struct mps_fs *) &addr[i][j]; - goto fs_found; - } + if ((pr->cpu_flags & (1 << 0)) == 0) + return; + + apic_id_mask |= (1 << pr->l_apic_id); +} + +static void ct_bus_entry(struct __bus_entry *bus __attribute__((unused))) +{ +#ifdef MPSCT_VERBOSE + char buf[7]; + + memcpy((void *) buf, (void *) bus->bus_type, 6); + buf[6] = 0; + + printf("MPS: bus=%" PRIu8 " (%s)\n", bus->bus_id, buf); +#endif +} + +static void ct_io_apic_entry(struct __io_apic_entry *ioa) +{ + /* This I/O APIC is marked unusable */ + if ((ioa->io_apic_flags & 1) == 0) + return; + + if (io_apic_cnt++ > 0) { + /* + * Multiple I/O APICs are currently not supported. + */ + return; + } + + io_apic = (uint32_t *) (uintptr_t) ioa->io_apic; +} + +static void ct_io_intr_entry(struct __io_intr_entry *iointr + __attribute__((unused))) +{ +#ifdef MPSCT_VERBOSE + printf("MPS: "); + + switch (iointr->intr_type) { + case 0: + printf("INT"); + break; + case 1: + printf("NMI"); + break; + case 2: + printf("SMI"); + break; + case 3: + printf("ExtINT"); + break; + } + + printf(", "); + + switch (iointr->poel & 3) { + case 0: + printf("bus-like"); + break; + case 1: + printf("active high"); + break; + case 2: + printf("reserved"); + break; + case 3: + printf("active low"); + break; + } + + printf(", "); + + switch ((iointr->poel >> 2) & 3) { + case 0: + printf("bus-like"); + break; + case 1: + printf("edge-triggered"); + break; + case 2: + printf("reserved"); + break; + case 3: + printf("level-triggered"); + break; + } + + printf(", bus=%" PRIu8 " irq=%" PRIu8 " io_apic=%" PRIu8" pin=%" + PRIu8 "\n", iointr->src_bus_id, iointr->src_bus_irq, + iointr->dst_io_apic_id, iointr->dst_io_apic_pin); +#endif +} + +static void ct_l_intr_entry(struct __l_intr_entry *lintr + __attribute__((unused))) +{ +#ifdef MPSCT_VERBOSE + printf("MPS: "); + + switch (lintr->intr_type) { + case 0: + printf("INT"); + break; + case 1: + printf("NMI"); + break; + case 2: + printf("SMI"); + break; + case 3: + printf("ExtINT"); + break; + } + + printf(", "); + + switch (lintr->poel & 3) { + case 0: + printf("bus-like"); + break; + case 1: + printf("active high"); + break; + case 2: + printf("reserved"); + break; + case 3: + printf("active low"); + break; + } + + printf(", "); + + switch ((lintr->poel >> 2) & 3) { + case 0: + printf("bus-like"); + break; + case 1: + printf("edge-triggered"); + break; + case 2: + printf("reserved"); + break; + case 3: + printf("level-triggered"); + break; + } + + printf(", bus=%" PRIu8 " irq=%" PRIu8 " l_apic=%" PRIu8" pin=%" + PRIu8 "\n", lintr->src_bus_id, lintr->src_bus_irq, + lintr->dst_l_apic_id, lintr->dst_l_apic_pin); +#endif +} + +static void ct_extended_entries(void) +{ + uint8_t *ext = (uint8_t *) ct + ct->base_table_length; + uint8_t *cur; + + for (cur = ext; cur < ext + ct->ext_table_length; + cur += cur[CT_EXT_ENTRY_LEN]) { + switch (cur[CT_EXT_ENTRY_TYPE]) { + default: + printf("MPS: Skipping MP Configuration Table extended " + "entry type %" PRIu8 "\n", cur[CT_EXT_ENTRY_TYPE]); } } - - return; - -fs_found: - printf("%p: MPS Floating Pointer Structure\n", fs); - - if (fs->config_type == 0 && fs->configuration_table) { - if (fs->mpfib2 >> 7) { - printf("%s: PIC mode not supported\n", __func__); - return; - } - - ct = (struct mps_ct *)PA2KA((uintptr_t)fs->configuration_table); - config.cpu_count = configure_via_ct(); - } - else - config.cpu_count = configure_via_default(fs->config_type); - - return; -} - -int configure_via_ct(void) -{ - uint8_t *cur; - unsigned int i, cnt; - +} + +static void configure_via_ct(void) +{ if (ct->signature != CT_SIGNATURE) { - printf("%s: bad ct->signature\n", __func__); - return 1; - } + printf("MPS: Wrong ct->signature\n"); + return; + } + if (!mps_ct_check()) { - printf("%s: bad ct checksum\n", __func__); - return 1; - } + printf("MPS: Wrong ct checksum\n"); + return; + } + if (ct->oem_table) { - printf("%s: ct->oem_table not supported\n", __func__); - return 1; - } - - l_apic = (uint32_t *)(uintptr_t)ct->l_apic; - - cnt = 0; - cur = &ct->base_table[0]; + printf("MPS: ct->oem_table not supported\n"); + return; + } + + l_apic = (uint32_t *) (uintptr_t) ct->l_apic; + + uint8_t *cur = &ct->base_table[0]; + uint16_t i; + for (i = 0; i < ct->entry_count; i++) { switch (*cur) { - /* Processor entry */ - case 0: + case 0: /* Processor entry */ processor_entries = processor_entries ? processor_entries : (struct __processor_entry *) cur; processor_entry_cnt++; - cnt += ct_processor_entry((struct __processor_entry *) - cur); + ct_processor_entry((struct __processor_entry *) cur); cur += 20; break; - - /* Bus entry */ - case 1: + case 1: /* Bus entry */ bus_entries = bus_entries ? bus_entries : (struct __bus_entry *) cur; @@ -250,16 +377,12 @@ cur += 8; break; - - /* I/O Apic */ - case 2: + case 2: /* I/O APIC */ io_apic_entries = io_apic_entries ? io_apic_entries : (struct __io_apic_entry *) cur; - io_apic_entry_cnt++; + io_apic_entry_cnt++; ct_io_apic_entry((struct __io_apic_entry *) cur); cur += 8; break; - - /* I/O Interrupt Assignment */ - case 3: + case 3: /* I/O Interrupt Assignment */ io_intr_entries = io_intr_entries ? io_intr_entries : (struct __io_intr_entry *) cur; @@ -268,7 +391,5 @@ cur += 8; break; - - /* Local Interrupt Assignment */ - case 4: + case 4: /* Local Interrupt Assignment */ l_intr_entries = l_intr_entries ? l_intr_entries : (struct __l_intr_entry *) cur; @@ -277,12 +398,10 @@ cur += 8; break; - default: /* * Something is wrong. Fallback to UP mode. */ - - printf("%s: ct badness\n", __func__); - return 1; + printf("MPS: ct badness %" PRIu8 "\n", *cur); + return; } } @@ -292,196 +411,57 @@ */ ct_extended_entries(); - return cnt; -} - -int configure_via_default(uint8_t n __attribute__((unused))) +} + +static void configure_via_default(uint8_t n __attribute__((unused))) { /* * Not yet implemented. */ - printf("%s: not supported\n", __func__); - return 1; -} - - -int ct_processor_entry(struct __processor_entry *pr __attribute__((unused))) -{ + printf("MPS: Default configuration not supported\n"); +} + +void mps_init(void) +{ + uint8_t *addr[2] = { NULL, (uint8_t *) PA2KA(0xf0000) }; + unsigned int i; + unsigned int j; + unsigned int length[2] = { 1024, 64 * 1024 }; + /* - * Ignore processors which are not marked enabled. + * Find MP Floating Pointer Structure + * 1a. search first 1K of EBDA + * 1b. if EBDA is undefined, search last 1K of base memory + * 2. search 64K starting at 0xf0000 */ - if ((pr->cpu_flags & (1 << 0)) == 0) - return 0; - - apic_id_mask |= (1 << pr->l_apic_id); - return 1; -} - -void ct_bus_entry(struct __bus_entry *bus __attribute__((unused))) -{ -#ifdef MPSCT_VERBOSE - char buf[7]; - memcpy((void *) buf, (void *) bus->bus_type, 6); - buf[6] = 0; - printf("bus%d: %s\n", bus->bus_id, buf); -#endif -} - -void ct_io_apic_entry(struct __io_apic_entry *ioa) -{ - static unsigned int io_apic_count = 0; - - /* this ioapic is marked unusable */ - if ((ioa->io_apic_flags & 1) == 0) - return; - - if (io_apic_count++ > 0) { - /* - * Multiple IO APIC's are currently not supported. - */ - return; - } - - io_apic = (uint32_t *)(uintptr_t)ioa->io_apic; -} - -//#define MPSCT_VERBOSE -void ct_io_intr_entry(struct __io_intr_entry *iointr __attribute__((unused))) -{ -#ifdef MPSCT_VERBOSE - switch (iointr->intr_type) { - case 0: - printf("INT"); - break; - case 1: - printf("NMI"); - break; - case 2: - printf("SMI"); - break; - case 3: - printf("ExtINT"); - break; - } - putchar(','); - switch (iointr->poel & 3) { - case 0: - printf("bus-like"); - break; - case 1: - printf("active high"); - break; - case 2: - printf("reserved"); - break; - case 3: - printf("active low"); - break; - } - putchar(','); - switch ((iointr->poel >> 2) & 3) { - case 0: - printf("bus-like"); - break; - case 1: - printf("edge-triggered"); - break; - case 2: - printf("reserved"); - break; - case 3: - printf("level-triggered"); - break; - } - putchar(','); - printf("bus%d,irq%d", iointr->src_bus_id, iointr->src_bus_irq); - putchar(','); - printf("io_apic%d,pin%d", iointr->dst_io_apic_id, - iointr->dst_io_apic_pin); - putchar('\n'); -#endif -} - -void ct_l_intr_entry(struct __l_intr_entry *lintr __attribute__((unused))) -{ -#ifdef MPSCT_VERBOSE - switch (lintr->intr_type) { - case 0: - printf("INT"); - break; - case 1: - printf("NMI"); - break; - case 2: - printf("SMI"); - break; - case 3: - printf("ExtINT"); - break; - } - putchar(','); - switch (lintr->poel & 3) { - case 0: - printf("bus-like"); - break; - case 1: - printf("active high"); - break; - case 2: - printf("reserved"); - break; - case 3: - printf("active low"); - break; - } - putchar(','); - switch ((lintr->poel >> 2) & 3) { - case 0: - printf("bus-like"); - break; - case 1: - printf("edge-triggered"); - break; - case 2: - printf("reserved"); - break; - case 3: - printf("level-triggered"); - break; - } - putchar(','); - printf("bus%d,irq%d", lintr->src_bus_id, lintr->src_bus_irq); - putchar(','); - printf("l_apic%d,pin%d", lintr->dst_l_apic_id, lintr->dst_l_apic_pin); - putchar('\n'); -#endif -} - -void ct_extended_entries(void) -{ - uint8_t *ext = (uint8_t *) ct + ct->base_table_length; - uint8_t *cur; - - for (cur = ext; cur < ext + ct->ext_table_length; - cur += cur[CT_EXT_ENTRY_LEN]) { - switch (cur[CT_EXT_ENTRY_TYPE]) { - default: - printf("%p: skipping MP Configuration Table extended " - "entry type %d\n", cur, cur[CT_EXT_ENTRY_TYPE]); - break; + + addr[0] = (uint8_t *) PA2KA(ebda ? ebda : 639 * 1024); + for (i = 0; i < 2; i++) { + for (j = 0; j < length[i]; j += 16) { + if ((*((uint32_t *) &addr[i][j]) == + FS_SIGNATURE) && (mps_fs_check(&addr[i][j]))) { + fs = (struct mps_fs *) &addr[i][j]; + goto fs_found; + } } } -} - -int mps_irq_to_pin(unsigned int irq) -{ - unsigned int i; - - for (i = 0; i < io_intr_entry_cnt; i++) { - if (io_intr_entries[i].src_bus_irq == irq && - io_intr_entries[i].intr_type == 0) - return io_intr_entries[i].dst_io_apic_pin; - } - - return -1; + + return; + +fs_found: + printf("%p: MPS Floating Pointer Structure\n", fs); + + if ((fs->config_type == 0) && (fs->configuration_table)) { + if (fs->mpfib2 >> 7) { + printf("MPS: PIC mode not supported\n"); + return; + } + + ct = (struct mps_ct *) PA2KA((uintptr_t) fs->configuration_table); + configure_via_ct(); + } else + configure_via_default(fs->config_type); + + if (processor_entry_cnt > 0) + config.cpu_count = processor_entry_cnt; } Index: kernel/arch/ia32/src/smp/smp.c =================================================================== --- kernel/arch/ia32/src/smp/smp.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia32/src/smp/smp.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -62,35 +62,17 @@ void smp_init(void) { - uintptr_t l_apic_address, io_apic_address; - if (acpi_madt) { acpi_madt_parse(); ops = &madt_config_operations; } + if (config.cpu_count == 1) { mps_init(); ops = &mps_config_operations; } - - l_apic_address = (uintptr_t) frame_alloc(ONE_FRAME, - FRAME_ATOMIC | FRAME_KA); - if (!l_apic_address) - panic("Cannot allocate address for l_apic."); - - io_apic_address = (uintptr_t) frame_alloc(ONE_FRAME, - FRAME_ATOMIC | FRAME_KA); - if (!io_apic_address) - panic("Cannot allocate address for io_apic."); - + if (config.cpu_count > 1) { - page_table_lock(AS_KERNEL, true); - page_mapping_insert(AS_KERNEL, l_apic_address, - (uintptr_t) l_apic, PAGE_NOT_CACHEABLE | PAGE_WRITE); - page_mapping_insert(AS_KERNEL, io_apic_address, - (uintptr_t) io_apic, PAGE_NOT_CACHEABLE | PAGE_WRITE); - page_table_unlock(AS_KERNEL, true); - - l_apic = (uint32_t *) l_apic_address; - io_apic = (uint32_t *) io_apic_address; + l_apic = (uint32_t *) hw_map((uintptr_t) l_apic, PAGE_SIZE); + io_apic = (uint32_t *) hw_map((uintptr_t) io_apic, PAGE_SIZE); } } @@ -108,16 +90,16 @@ ASSERT(ops != NULL); - + /* * We need to access data in frame 0. * We boldly make use of kernel address space mapping. */ - + /* * Set the warm-reset vector to the real-mode address of 4K-aligned ap_boot() */ *((uint16_t *) (PA2KA(0x467 + 0))) = - (uint16_t) (((uintptr_t) ap_boot) >> 4); /* segment */ - *((uint16_t *) (PA2KA(0x467 + 2))) = 0; /* offset */ + (uint16_t) (((uintptr_t) ap_boot) >> 4); /* segment */ + *((uint16_t *) (PA2KA(0x467 + 2))) = 0; /* offset */ /* @@ -125,15 +107,11 @@ * BIOS will not do the POST after the INIT signal. */ - pio_write_8((ioport8_t *)0x70, 0xf); - pio_write_8((ioport8_t *)0x71, 0xa); - + pio_write_8((ioport8_t *) 0x70, 0xf); + pio_write_8((ioport8_t *) 0x71, 0xa); + pic_disable_irqs(0xffff); apic_init(); - uint8_t apic = l_apic_id(); - - for (i = 0; i < ops->cpu_count(); i++) { - descriptor_t *gdt_new; - + for (i = 0; i < config.cpu_count; i++) { /* * Skip processors marked unusable. @@ -141,5 +119,5 @@ if (!ops->cpu_enabled(i)) continue; - + /* * The bootstrap processor is already up. @@ -147,8 +125,8 @@ if (ops->cpu_bootstrap(i)) continue; - - if (ops->cpu_apic_id(i) == apic) { - printf("%s: bad processor entry #%u, will not send IPI " - "to myself\n", __FUNCTION__, i); + + if (ops->cpu_apic_id(i) == bsp_l_apic) { + printf("kmp: bad processor entry #%u, will not send IPI " + "to myself\n", i); continue; } @@ -162,9 +140,10 @@ * the memory subsystem */ - gdt_new = (descriptor_t *) malloc(GDT_ITEMS * - sizeof(descriptor_t), FRAME_ATOMIC); + descriptor_t *gdt_new = + (descriptor_t *) malloc(GDT_ITEMS * sizeof(descriptor_t), + FRAME_ATOMIC); if (!gdt_new) panic("Cannot allocate memory for GDT."); - + memcpy(gdt_new, gdt, GDT_ITEMS * sizeof(descriptor_t)); memsetb(&gdt_new[TSS_DES], sizeof(descriptor_t), 0); @@ -172,5 +151,5 @@ protected_ap_gdtr.base = KA2PA((uintptr_t) gdt_new); gdtr.base = (uintptr_t) gdt_new; - + if (l_apic_send_init_ipi(ops->cpu_apic_id(i))) { /* @@ -181,8 +160,6 @@ if (waitq_sleep_timeout(&ap_completion_wq, 1000000, SYNCH_FLAGS_NONE) == ESYNCH_TIMEOUT) { - unsigned int cpu = (config.cpu_active > i) ? - config.cpu_active : i; printf("%s: waiting for cpu%u (APIC ID = %d) " - "timed out\n", __FUNCTION__, cpu, + "timed out\n", __FUNCTION__, i, ops->cpu_apic_id(i)); } Index: kernel/arch/ia64/include/asm.h =================================================================== --- kernel/arch/ia64/include/asm.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia64/include/asm.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -40,8 +40,9 @@ #include #include +#include #define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL -static inline void pio_write_8(ioport8_t *port, uint8_t v) +NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v) { uintptr_t prt = (uintptr_t) port; @@ -56,5 +57,5 @@ } -static inline void pio_write_16(ioport16_t *port, uint16_t v) +NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v) { uintptr_t prt = (uintptr_t) port; @@ -69,5 +70,5 @@ } -static inline void pio_write_32(ioport32_t *port, uint32_t v) +NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v) { uintptr_t prt = (uintptr_t) port; @@ -82,5 +83,5 @@ } -static inline uint8_t pio_read_8(ioport8_t *port) +NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port) { uintptr_t prt = (uintptr_t) port; @@ -95,5 +96,5 @@ } -static inline uint16_t pio_read_16(ioport16_t *port) +NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port) { uintptr_t prt = (uintptr_t) port; @@ -108,5 +109,5 @@ } -static inline uint32_t pio_read_32(ioport32_t *port) +NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port) { uintptr_t prt = (uintptr_t) port; @@ -126,21 +127,26 @@ * The stack is assumed to be STACK_SIZE long. * The stack must start on page boundary. - */ -static inline uintptr_t get_stack_base(void) -{ - uint64_t v; - - /* I'm not sure why but this code bad inlines in scheduler, - so THE shifts about 16B and causes kernel panic - - asm volatile ( - "and %[value] = %[mask], r12" - : [value] "=r" (v) - : [mask] "r" (~(STACK_SIZE - 1)) - ); - return v; - - This code have the same meaning but inlines well. - */ + * + */ +NO_TRACE static inline uintptr_t get_stack_base(void) +{ + uint64_t v; + + /* + * I'm not sure why but this code inlines badly + * in scheduler, resulting in THE shifting about + * 16B and causing kernel panic. + * + * asm volatile ( + * "and %[value] = %[mask], r12" + * : [value] "=r" (v) + * : [mask] "r" (~(STACK_SIZE - 1)) + * ); + * return v; + * + * The following code has the same semantics but + * inlines correctly. + * + */ asm volatile ( @@ -155,6 +161,7 @@ * * @return PSR. - */ -static inline uint64_t psr_read(void) + * + */ +NO_TRACE static inline uint64_t psr_read(void) { uint64_t v; @@ -171,6 +178,7 @@ * * @return Return location of interruption vector table. - */ -static inline uint64_t iva_read(void) + * + */ +NO_TRACE static inline uint64_t iva_read(void) { uint64_t v; @@ -187,6 +195,7 @@ * * @param v New location of interruption vector table. - */ -static inline void iva_write(uint64_t v) + * + */ +NO_TRACE static inline void iva_write(uint64_t v) { asm volatile ( @@ -196,10 +205,11 @@ } - /** Read IVR (External Interrupt Vector Register). * - * @return Highest priority, pending, unmasked external interrupt vector. - */ -static inline uint64_t ivr_read(void) + * @return Highest priority, pending, unmasked external + * interrupt vector. + * + */ +NO_TRACE static inline uint64_t ivr_read(void) { uint64_t v; @@ -213,5 +223,5 @@ } -static inline uint64_t cr64_read(void) +NO_TRACE static inline uint64_t cr64_read(void) { uint64_t v; @@ -225,10 +235,10 @@ } - /** Write ITC (Interval Timer Counter) register. * * @param v New counter value. - */ -static inline void itc_write(uint64_t v) + * + */ +NO_TRACE static inline void itc_write(uint64_t v) { asm volatile ( @@ -241,6 +251,7 @@ * * @return Current counter value. - */ -static inline uint64_t itc_read(void) + * + */ +NO_TRACE static inline uint64_t itc_read(void) { uint64_t v; @@ -257,6 +268,7 @@ * * @param v New match value. - */ -static inline void itm_write(uint64_t v) + * + */ +NO_TRACE static inline void itm_write(uint64_t v) { asm volatile ( @@ -269,6 +281,7 @@ * * @return Match value. - */ -static inline uint64_t itm_read(void) + * + */ +NO_TRACE static inline uint64_t itm_read(void) { uint64_t v; @@ -285,6 +298,7 @@ * * @return Current vector and mask bit. - */ -static inline uint64_t itv_read(void) + * + */ +NO_TRACE static inline uint64_t itv_read(void) { uint64_t v; @@ -301,6 +315,7 @@ * * @param v New vector and mask bit. - */ -static inline void itv_write(uint64_t v) + * + */ +NO_TRACE static inline void itv_write(uint64_t v) { asm volatile ( @@ -313,6 +328,7 @@ * * @param v This value is ignored. - */ -static inline void eoi_write(uint64_t v) + * + */ +NO_TRACE static inline void eoi_write(uint64_t v) { asm volatile ( @@ -325,6 +341,7 @@ * * @return Current value of TPR. - */ -static inline uint64_t tpr_read(void) + * + */ +NO_TRACE static inline uint64_t tpr_read(void) { uint64_t v; @@ -341,6 +358,7 @@ * * @param v New value of TPR. - */ -static inline void tpr_write(uint64_t v) + * + */ +NO_TRACE static inline void tpr_write(uint64_t v) { asm volatile ( @@ -356,6 +374,7 @@ * * @return Old interrupt priority level. - */ -static ipl_t interrupts_disable(void) + * + */ +NO_TRACE static ipl_t interrupts_disable(void) { uint64_t v; @@ -377,6 +396,7 @@ * * @return Old interrupt priority level. - */ -static ipl_t interrupts_enable(void) + * + */ +NO_TRACE static ipl_t interrupts_enable(void) { uint64_t v; @@ -399,6 +419,7 @@ * * @param ipl Saved interrupt priority level. - */ -static inline void interrupts_restore(ipl_t ipl) + * + */ +NO_TRACE static inline void interrupts_restore(ipl_t ipl) { if (ipl & PSR_I_MASK) @@ -411,6 +432,7 @@ * * @return PSR. - */ -static inline ipl_t interrupts_read(void) + * + */ +NO_TRACE static inline ipl_t interrupts_read(void) { return (ipl_t) psr_read(); @@ -422,5 +444,5 @@ * */ -static inline bool interrupts_disabled(void) +NO_TRACE static inline bool interrupts_disabled(void) { return !(psr_read() & PSR_I_MASK); @@ -428,5 +450,5 @@ /** Disable protection key checking. */ -static inline void pk_disable(void) +NO_TRACE static inline void pk_disable(void) { asm volatile ( Index: kernel/arch/ia64/include/atomic.h =================================================================== --- kernel/arch/ia64/include/atomic.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia64/include/atomic.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -36,5 +36,7 @@ #define KERN_ia64_ATOMIC_H_ -static inline atomic_count_t test_and_set(atomic_t *val) +#include + +NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val) { atomic_count_t v; @@ -50,5 +52,5 @@ } -static inline void atomic_lock_arch(atomic_t *val) +NO_TRACE static inline void atomic_lock_arch(atomic_t *val) { do { @@ -57,5 +59,5 @@ } -static inline void atomic_inc(atomic_t *val) +NO_TRACE static inline void atomic_inc(atomic_t *val) { atomic_count_t v; @@ -68,5 +70,5 @@ } -static inline void atomic_dec(atomic_t *val) +NO_TRACE static inline void atomic_dec(atomic_t *val) { atomic_count_t v; @@ -79,5 +81,5 @@ } -static inline atomic_count_t atomic_preinc(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_preinc(atomic_t *val) { atomic_count_t v; @@ -92,5 +94,5 @@ } -static inline atomic_count_t atomic_predec(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_predec(atomic_t *val) { atomic_count_t v; @@ -105,5 +107,5 @@ } -static inline atomic_count_t atomic_postinc(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val) { atomic_count_t v; @@ -118,5 +120,5 @@ } -static inline atomic_count_t atomic_postdec(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val) { atomic_count_t v; Index: kernel/arch/ia64/include/cpu.h =================================================================== --- kernel/arch/ia64/include/cpu.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia64/include/cpu.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -40,7 +40,13 @@ #include #include +#include -#define FAMILY_ITANIUM 0x7 -#define FAMILY_ITANIUM2 0x1f +#define FAMILY_ITANIUM 0x7 +#define FAMILY_ITANIUM2 0x1f + +#define CR64_ID_SHIFT 24 +#define CR64_ID_MASK 0xff000000 +#define CR64_EID_SHIFT 16 +#define CR64_EID_MASK 0xff0000 typedef struct { @@ -55,38 +61,35 @@ * * @return Value of CPUID[n] register. + * */ -static inline uint64_t cpuid_read(int n) +NO_TRACE static inline uint64_t cpuid_read(int n) { uint64_t v; - asm volatile ("mov %0 = cpuid[%1]\n" : "=r" (v) : "r" (n)); + asm volatile ( + "mov %[v] = cpuid[%[r]]\n" + : [v] "=r" (v) + : [r] "r" (n) + ); return v; } - -#define CR64_ID_SHIFT 24 -#define CR64_ID_MASK 0xff000000 -#define CR64_EID_SHIFT 16 -#define CR64_EID_MASK 0xff0000 - -static inline int ia64_get_cpu_id(void) +NO_TRACE static inline int ia64_get_cpu_id(void) { - uint64_t cr64=cr64_read(); - return ((CR64_ID_MASK)&cr64)>>CR64_ID_SHIFT; + uint64_t cr64 = cr64_read(); + return ((CR64_ID_MASK) &cr64) >> CR64_ID_SHIFT; } -static inline int ia64_get_cpu_eid(void) +NO_TRACE static inline int ia64_get_cpu_eid(void) { - uint64_t cr64=cr64_read(); - return ((CR64_EID_MASK)&cr64)>>CR64_EID_SHIFT; + uint64_t cr64 = cr64_read(); + return ((CR64_EID_MASK) &cr64) >> CR64_EID_SHIFT; } - -static inline void ipi_send_ipi(int id, int eid, int intno) +NO_TRACE static inline void ipi_send_ipi(int id, int eid, int intno) { (bootinfo->sapic)[2 * (id * 256 + eid)] = intno; srlz_d(); - } Index: kernel/arch/ia64/include/cycle.h =================================================================== --- kernel/arch/ia64/include/cycle.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia64/include/cycle.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -36,5 +36,7 @@ #define KERN_ia64_CYCLE_H_ -static inline uint64_t get_cycle(void) +#include + +NO_TRACE static inline uint64_t get_cycle(void) { return 0; Index: kernel/arch/ia64/include/interrupt.h =================================================================== --- kernel/arch/ia64/include/interrupt.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia64/include/interrupt.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -38,4 +38,5 @@ #include #include +#include /** ia64 has 256 INRs. */ @@ -133,5 +134,8 @@ } istate_t; -static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) +extern void *ivt; + +NO_TRACE static inline void istate_set_retaddr(istate_t *istate, + uintptr_t retaddr) { istate->cr_iip = retaddr; @@ -139,29 +143,29 @@ } -static inline unative_t istate_get_pc(istate_t *istate) +NO_TRACE static inline unative_t istate_get_pc(istate_t *istate) { return istate->cr_iip; } -static inline unative_t istate_get_fp(istate_t *istate) +NO_TRACE static inline unative_t istate_get_fp(istate_t *istate) { - return 0; /* FIXME */ + /* FIXME */ + + return 0; } -static inline int istate_from_uspace(istate_t *istate) +NO_TRACE static inline int istate_from_uspace(istate_t *istate) { return (istate->cr_iip) < 0xe000000000000000ULL; } -extern void *ivt; +extern void general_exception(uint64_t, istate_t *); +extern int break_instruction(uint64_t, istate_t *); +extern void universal_handler(uint64_t, istate_t *); +extern void nop_handler(uint64_t, istate_t *); +extern void external_interrupt(uint64_t, istate_t *); +extern void disabled_fp_register(uint64_t, istate_t *); -extern void general_exception(uint64_t vector, istate_t *istate); -extern int break_instruction(uint64_t vector, istate_t *istate); -extern void universal_handler(uint64_t vector, istate_t *istate); -extern void nop_handler(uint64_t vector, istate_t *istate); -extern void external_interrupt(uint64_t vector, istate_t *istate); -extern void disabled_fp_register(uint64_t vector, istate_t *istate); - -extern void trap_virtual_enable_irqs(uint16_t irqmask); +extern void trap_virtual_enable_irqs(uint16_t); #endif Index: kernel/arch/ia64/include/mm/page.h =================================================================== --- kernel/arch/ia64/include/mm/page.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia64/include/mm/page.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -208,5 +208,5 @@ * @return Address of the head of VHPT collision chain. */ -static inline uint64_t thash(uint64_t va) +NO_TRACE static inline uint64_t thash(uint64_t va) { uint64_t ret; @@ -230,5 +230,5 @@ * @return The unique tag for VPN and RID in the collision chain returned by thash(). */ -static inline uint64_t ttag(uint64_t va) +NO_TRACE static inline uint64_t ttag(uint64_t va) { uint64_t ret; @@ -249,5 +249,5 @@ * @return Current contents of rr[i]. */ -static inline uint64_t rr_read(size_t i) +NO_TRACE static inline uint64_t rr_read(size_t i) { uint64_t ret; @@ -269,5 +269,5 @@ * @param v Value to be written to rr[i]. */ -static inline void rr_write(size_t i, uint64_t v) +NO_TRACE static inline void rr_write(size_t i, uint64_t v) { ASSERT(i < REGION_REGISTERS); @@ -284,5 +284,5 @@ * @return Current value stored in PTA. */ -static inline uint64_t pta_read(void) +NO_TRACE static inline uint64_t pta_read(void) { uint64_t ret; @@ -300,5 +300,5 @@ * @param v New value to be stored in PTA. */ -static inline void pta_write(uint64_t v) +NO_TRACE static inline void pta_write(uint64_t v) { asm volatile ( Index: kernel/arch/ia64/src/asm.S =================================================================== --- kernel/arch/ia64/src/asm.S (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia64/src/asm.S (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -1,43 +1,33 @@ -# -# Copyright (c) 2005 Jakub Jermar -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ #include .text - -/** Copy memory from/to userspace. - * - * This memcpy() has been taken from the assembler output of - * the generic _memcpy() and modified to have the failover part. - * - * @param in0 Destination address. - * @param in1 Source address. - * @param in2 Number of byte to copy. - */ .global memcpy .global memcpy_from_uspace @@ -45,9 +35,20 @@ .global memcpy_from_uspace_failover_address .global memcpy_to_uspace_failover_address + +/** Copy memory from/to userspace. + * + * This memcpy() has been taken from the assembler output of + * the generic _memcpy() and modified to have the failover part. + * + * @param in0 Destination address. + * @param in1 Source address. + * @param in2 Number of byte to copy. + * + */ memcpy: memcpy_from_uspace: memcpy_to_uspace: alloc loc0 = ar.pfs, 3, 1, 0, 0 - + adds r14 = 7, in1 mov r2 = ar.lc @@ -55,71 +56,86 @@ and r14 = -8, r14 ;; cmp.ne p6, p7 = r14, in1 -(p7) br.cond.dpnt 3f ;; -0: - cmp.ne p6, p7 = 0, in2 -(p7) br.cond.dpnt 2f ;; -(p6) adds r14 = -1, in2 -(p6) mov r16 = r0 -(p6) mov r17 = r0 ;; -(p6) mov ar.lc = r14 -1: - add r14 = r16, in1 - add r15 = r16, in0 - adds r17 = 1, r17 ;; - ld1 r14 = [r14] - mov r16 = r17 ;; - st1 [r15] = r14 - br.cloop.sptk.few 1b ;; -2: - mov ar.lc = r2 - mov ar.pfs = loc0 - br.ret.sptk.many rp -3: - adds r14 = 7, in0 ;; - and r14 = -8, r14 ;; - cmp.eq p6, p7 = r14, in0 -(p7) br.cond.dptk 0b - shr.u r18 = in2, 3 ;; - cmp.ne p6, p7 = 0, r18 -(p7) br.cond.dpnt 5f ;; -(p6) adds r14 = -1, r18 -(p6) mov r16 = r0 -(p6) mov r17 = r0 ;; -(p6) mov ar.lc = r14 -4: - shladd r14 = r16, 3, r0 - adds r16 = 1, r17 ;; - add r15 = in1, r14 - add r14 = in0, r14 - mov r17 = r16 ;; - ld8 r15 = [r15] ;; - st8 [r14] = r15 - br.cloop.sptk.few 4b -5: - and r15 = 7, in2 - shladd r14 = r18, 3, r0 - mov r16 = r0 - mov r18 = r0 ;; - cmp.eq p6, p7 = 0, r15 - add in0 = r14, in0 - adds r15 = -1, r15 - add r17 = r14, in1 -(p6) br.cond.dpnt 2b ;; - mov ar.lc = r15 -6: - add r14 = r16, r17 - add r15 = r16, in0 - adds r16 = 1, r18 ;; - ld1 r14 = [r14] - mov r18 = r16 ;; - st1 [r15] = r14 - br.cloop.sptk.few 6b ;; - mov ar.lc = r2 - mov ar.pfs = loc0 - br.ret.sptk.many rp - + (p7) br.cond.dpnt 3f ;; + + 0: + + cmp.ne p6, p7 = 0, in2 + (p7) br.cond.dpnt 2f ;; + (p6) adds r14 = -1, in2 + (p6) mov r16 = r0 + (p6) mov r17 = r0 ;; + (p6) mov ar.lc = r14 + + 1: + + add r14 = r16, in1 + add r15 = r16, in0 + adds r17 = 1, r17 ;; + ld1 r14 = [r14] + mov r16 = r17 ;; + st1 [r15] = r14 + br.cloop.sptk.few 1b ;; + + 2: + + mov ar.lc = r2 + mov ar.pfs = loc0 + br.ret.sptk.many rp + + 3: + + adds r14 = 7, in0 ;; + and r14 = -8, r14 ;; + cmp.eq p6, p7 = r14, in0 + (p7) br.cond.dptk 0b + shr.u r18 = in2, 3 ;; + cmp.ne p6, p7 = 0, r18 + (p7) br.cond.dpnt 5f ;; + (p6) adds r14 = -1, r18 + (p6) mov r16 = r0 + (p6) mov r17 = r0 ;; + (p6) mov ar.lc = r14 + + 4: + + shladd r14 = r16, 3, r0 + adds r16 = 1, r17 ;; + add r15 = in1, r14 + add r14 = in0, r14 + mov r17 = r16 ;; + ld8 r15 = [r15] ;; + st8 [r14] = r15 + br.cloop.sptk.few 4b + + 5: + + and r15 = 7, in2 + shladd r14 = r18, 3, r0 + mov r16 = r0 + mov r18 = r0 ;; + cmp.eq p6, p7 = 0, r15 + add in0 = r14, in0 + adds r15 = -1, r15 + add r17 = r14, in1 + (p6) br.cond.dpnt 2b ;; + mov ar.lc = r15 + + 6: + + add r14 = r16, r17 + add r15 = r16, in0 + adds r16 = 1, r18 ;; + ld1 r14 = [r14] + mov r18 = r16 ;; + st1 [r15] = r14 + br.cloop.sptk.few 6b ;; + mov ar.lc = r2 + mov ar.pfs = loc0 + br.ret.sptk.many rp + memcpy_from_uspace_failover_address: memcpy_to_uspace_failover_address: - mov r8 = r0 /* return 0 on failure */ + /* Return 0 on failure */ + mov r8 = r0 mov ar.pfs = loc0 br.ret.sptk.many rp @@ -136,11 +152,4 @@ cpu_halt: br cpu_halt - -.global panic_printf -panic_printf: - { - br.call.sptk.many b0=printf - } - br halt /** Switch to userspace - low level code. @@ -152,9 +161,12 @@ * @param in4 Value to be stored in IPSR. * @param in5 Value to be stored in RSC. + * */ .global switch_to_userspace switch_to_userspace: alloc loc0 = ar.pfs, 6, 3, 0, 0 - rsm (PSR_IC_MASK | PSR_I_MASK) /* disable interruption collection and interrupts */ + + /* Disable interruption collection and interrupts */ + rsm (PSR_IC_MASK | PSR_I_MASK) srlz.d ;; srlz.i ;; @@ -163,5 +175,5 @@ mov cr.iip = in0 mov r12 = in1 - + xor r1 = r1, r1 @@ -172,12 +184,12 @@ movl loc2 = PFM_MASK ;; and loc1 = loc2, loc1 ;; - mov cr.ifs = loc1 ;; /* prevent decrementing BSP by rfi */ - + mov cr.ifs = loc1 ;; /* prevent decrementing BSP by rfi */ + invala mov loc1 = ar.rsc ;; - and loc1 = ~3, loc1 ;; - mov ar.rsc = loc1 ;; /* put RSE into enforced lazy mode */ - + and loc1 = ~3, loc1 ;; + mov ar.rsc = loc1 ;; /* put RSE into enforced lazy mode */ + flushrs ;; @@ -188,2 +200,6 @@ rfi ;; + +.global early_putchar +early_putchar: + br.ret.sptk.many b0 Index: kernel/arch/ia64/src/interrupt.c =================================================================== --- kernel/arch/ia64/src/interrupt.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia64/src/interrupt.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -133,8 +133,6 @@ } -static void dump_interrupted_context(istate_t *istate) -{ - putchar('\n'); - printf("Interrupted context dump:\n"); +void istate_decode(istate_t *istate) +{ printf("ar.bsp=%p\tar.bspstore=%p\n", istate->ar_bsp, istate->ar_bspstore); @@ -183,7 +181,5 @@ fault_if_from_uspace(istate, "General Exception (%s).", desc); - - dump_interrupted_context(istate); - panic("General Exception (%s).", desc); + panic_badtrap(istate, vector, "General Exception (%s).", desc); } @@ -195,7 +191,6 @@ fault_if_from_uspace(istate, "Interruption: %#hx (%s).", (uint16_t) vector, vector_to_string(vector)); - dump_interrupted_context(istate); - panic("Interruption: %#hx (%s).", (uint16_t) vector, - vector_to_string(vector)); + panic_badtrap(istate, vector, "Interruption: %#hx (%s).", + (uint16_t) vector, vector_to_string(vector)); #endif } @@ -226,7 +221,6 @@ fault_if_from_uspace(istate, "Interruption: %#hx (%s).", (uint16_t) vector, vector_to_string(vector)); - dump_interrupted_context(istate); - panic("Interruption: %#hx (%s).", (uint16_t) vector, - vector_to_string(vector)); + panic_badtrap(istate, vector, "Interruption: %#hx (%s).", + (uint16_t) vector, vector_to_string(vector)); } Index: kernel/arch/ia64/src/mm/tlb.c =================================================================== --- kernel/arch/ia64/src/mm/tlb.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia64/src/mm/tlb.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -500,6 +500,6 @@ if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { fault_if_from_uspace(istate, "Page fault at %p.", va); - panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid, - istate->cr_iip); + panic_memtrap(istate, PF_ACCESS_EXEC, va, + "Page fault."); } } @@ -622,6 +622,6 @@ if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { fault_if_from_uspace(istate, "Page fault at %p.", va); - panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid, - istate->cr_iip); + panic_memtrap(istate, PF_ACCESS_READ, va, + "Page fault."); } } @@ -671,6 +671,6 @@ if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { fault_if_from_uspace(istate, "Page fault at %p.", va); - panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid, - istate->cr_iip); + panic_memtrap(istate, PF_ACCESS_WRITE, va, + "Page fault."); } } @@ -708,6 +708,6 @@ if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { fault_if_from_uspace(istate, "Page fault at %p.", va); - panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid, - istate->cr_iip); + panic_memtrap(istate, PF_ACCESS_EXEC, va, + "Page fault."); } } @@ -745,6 +745,6 @@ if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { fault_if_from_uspace(istate, "Page fault at %p.", va); - panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid, - istate->cr_iip); + panic_memtrap(istate, PF_ACCESS_READ, va, + "Page fault."); } } @@ -778,6 +778,5 @@ if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { fault_if_from_uspace(istate, "Page fault at %p.", va); - panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid, - istate->cr_iip); + panic_memtrap(istate, PF_ACCESS_WRITE, va, "Page fault."); } page_table_unlock(AS, true); @@ -819,5 +818,6 @@ if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { fault_if_from_uspace(istate, "Page fault at %p.", va); - panic("%s: va=%p, rid=%d.", __func__, va, rid); + panic_memtrap(istate, PF_ACCESS_READ, va, + "Page fault."); } } Index: kernel/arch/ia64/src/start.S =================================================================== --- kernel/arch/ia64/src/start.S (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ia64/src/start.S (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -47,4 +47,13 @@ stack0: + +# +# Kernel entry point. +# +# This is where we are passed control from the boot code. +# Register contents: +# +# r2 Address of the boot code's bootinfo structure. +# kernel_image_start: .auto @@ -157,16 +166,19 @@ loadrs - # Initialize memory stack to some sane value - movl r12 = stack0 ;; - add r12 = -16, r12 /* allocate a scratch area on the stack */ + # + # Initialize memory stack to some sane value and allocate a scratch are + # on it. + # + movl sp = stack0 ;; + add sp = -16, sp # Initialize gp (Global Pointer) register + movl gp = kernel_image_start + + # + # Initialize bootinfo on BSP. + # movl r20 = (VRN_KERNEL << VRN_SHIFT) ;; - or r20 = r20, r1 ;; - movl r1 = kernel_image_start - - /* - * Initialize bootinfo on BSP. - */ + or r20 = r20, r2 ;; addl r21 = @gprel(bootinfo), gp ;; st8 [r21] = r20 Index: kernel/arch/mips32/Makefile.inc =================================================================== --- kernel/arch/mips32/Makefile.inc (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/mips32/Makefile.inc (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -54,5 +54,4 @@ arch/$(KARCH)/src/start.S \ arch/$(KARCH)/src/context.S \ - arch/$(KARCH)/src/panic.S \ arch/$(KARCH)/src/mips32.c \ arch/$(KARCH)/src/asm.S \ Index: kernel/arch/mips32/include/asm.h =================================================================== --- kernel/arch/mips32/include/asm.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/mips32/include/asm.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -38,9 +38,16 @@ #include #include +#include -static inline void cpu_sleep(void) +NO_TRACE static inline void cpu_sleep(void) { - /* Most of the simulators do not support */ -/* asm volatile ("wait"); */ + /* + * Unfortunatelly most of the simulators do not support + * + * asm volatile ( + * "wait" + * ); + * + */ } @@ -52,5 +59,5 @@ * */ -static inline uintptr_t get_stack_base(void) +NO_TRACE static inline uintptr_t get_stack_base(void) { uintptr_t base; @@ -65,44 +72,43 @@ } -extern void cpu_halt(void) __attribute__((noreturn)); -extern void asm_delay_loop(uint32_t t); -extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg, - uintptr_t entry); - -extern ipl_t interrupts_disable(void); -extern ipl_t interrupts_enable(void); -extern void interrupts_restore(ipl_t ipl); -extern ipl_t interrupts_read(void); -extern bool interrupts_disabled(void); - -static inline void pio_write_8(ioport8_t *port, uint8_t v) +NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v) { *port = v; } -static inline void pio_write_16(ioport16_t *port, uint16_t v) +NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v) { *port = v; } -static inline void pio_write_32(ioport32_t *port, uint32_t v) +NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v) { *port = v; } -static inline uint8_t pio_read_8(ioport8_t *port) +NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port) { return *port; } -static inline uint16_t pio_read_16(ioport16_t *port) +NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port) { return *port; } -static inline uint32_t pio_read_32(ioport32_t *port) +NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port) { return *port; } + +extern void cpu_halt(void) __attribute__((noreturn)); +extern void asm_delay_loop(uint32_t); +extern void userspace_asm(uintptr_t, uintptr_t, uintptr_t); + +extern ipl_t interrupts_disable(void); +extern ipl_t interrupts_enable(void); +extern void interrupts_restore(ipl_t); +extern ipl_t interrupts_read(void); +extern bool interrupts_disabled(void); #endif Index: kernel/arch/mips32/include/atomic.h =================================================================== --- kernel/arch/mips32/include/atomic.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/mips32/include/atomic.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -36,4 +36,6 @@ #define KERN_mips32_ATOMIC_H_ +#include + #define atomic_inc(x) ((void) atomic_add(x, 1)) #define atomic_dec(x) ((void) atomic_add(x, -1)) @@ -53,5 +55,6 @@ * */ -static inline atomic_count_t atomic_add(atomic_t *val, atomic_count_t i) +NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val, + atomic_count_t i) { atomic_count_t tmp; @@ -76,5 +79,5 @@ } -static inline atomic_count_t test_and_set(atomic_t *val) +NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val) { atomic_count_t tmp; @@ -98,5 +101,5 @@ } -static inline void atomic_lock_arch(atomic_t *val) +NO_TRACE static inline void atomic_lock_arch(atomic_t *val) { do { Index: kernel/arch/mips32/include/barrier.h =================================================================== --- kernel/arch/mips32/include/barrier.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/mips32/include/barrier.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup mips32 +/** @addtogroup mips32 * @{ */ @@ -39,10 +39,10 @@ * TODO: implement true MIPS memory barriers for macros below. */ -#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") -#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") +#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") +#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") -#define memory_barrier() asm volatile ("" ::: "memory") -#define read_barrier() asm volatile ("" ::: "memory") -#define write_barrier() asm volatile ("" ::: "memory") +#define memory_barrier() asm volatile ("" ::: "memory") +#define read_barrier() asm volatile ("" ::: "memory") +#define write_barrier() asm volatile ("" ::: "memory") #define smc_coherence(a) Index: kernel/arch/mips32/include/cycle.h =================================================================== --- kernel/arch/mips32/include/cycle.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/mips32/include/cycle.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -38,6 +38,7 @@ #include #include +#include -static inline uint64_t get_cycle(void) +NO_TRACE static inline uint64_t get_cycle(void) { return ((uint64_t) count_hi << 32) + ((uint64_t) cp0_count_read()); Index: kernel/arch/mips32/include/exception.h =================================================================== --- kernel/arch/mips32/include/exception.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/mips32/include/exception.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup mips32 +/** @addtogroup mips32 * @{ */ @@ -38,23 +38,24 @@ #include #include +#include -#define EXC_Int 0 -#define EXC_Mod 1 -#define EXC_TLBL 2 -#define EXC_TLBS 3 -#define EXC_AdEL 4 -#define EXC_AdES 5 -#define EXC_IBE 6 -#define EXC_DBE 7 -#define EXC_Sys 8 -#define EXC_Bp 9 -#define EXC_RI 10 -#define EXC_CpU 11 -#define EXC_Ov 12 -#define EXC_Tr 13 -#define EXC_VCEI 14 -#define EXC_FPE 15 -#define EXC_WATCH 23 -#define EXC_VCED 31 +#define EXC_Int 0 +#define EXC_Mod 1 +#define EXC_TLBL 2 +#define EXC_TLBS 3 +#define EXC_AdEL 4 +#define EXC_AdES 5 +#define EXC_IBE 6 +#define EXC_DBE 7 +#define EXC_Sys 8 +#define EXC_Bp 9 +#define EXC_RI 10 +#define EXC_CpU 11 +#define EXC_Ov 12 +#define EXC_Tr 13 +#define EXC_VCEI 14 +#define EXC_FPE 15 +#define EXC_WATCH 23 +#define EXC_VCED 31 typedef struct istate { @@ -82,11 +83,12 @@ uint32_t lo; uint32_t hi; - - uint32_t status; /* cp0_status */ - uint32_t epc; /* cp0_epc */ - uint32_t k1; /* We use it as thread-local pointer */ + + uint32_t status; /* cp0_status */ + uint32_t epc; /* cp0_epc */ + uint32_t k1; /* We use it as thread-local pointer */ } istate_t; -static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) +NO_TRACE static inline void istate_set_retaddr(istate_t *istate, + uintptr_t retaddr) { istate->epc = retaddr; @@ -94,15 +96,19 @@ /** Return true if exception happened while in userspace */ -static inline int istate_from_uspace(istate_t *istate) +NO_TRACE static inline int istate_from_uspace(istate_t *istate) { return istate->status & cp0_status_um_bit; } -static inline unative_t istate_get_pc(istate_t *istate) + +NO_TRACE static inline unative_t istate_get_pc(istate_t *istate) { return istate->epc; } -static inline unative_t istate_get_fp(istate_t *istate) + +NO_TRACE static inline unative_t istate_get_fp(istate_t *istate) { - return 0; /* FIXME */ + /* FIXME */ + + return 0; } Index: kernel/arch/mips32/include/faddr.h =================================================================== --- kernel/arch/mips32/include/faddr.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/mips32/include/faddr.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup mips32 +/** @addtogroup mips32 * @{ */ @@ -38,5 +38,5 @@ #include -#define FADDR(fptr) ((uintptr_t) (fptr)) +#define FADDR(fptr) ((uintptr_t) (fptr)) #endif Index: kernel/arch/mips32/include/mm/page.h =================================================================== --- kernel/arch/mips32/include/mm/page.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/mips32/include/mm/page.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -37,4 +37,5 @@ #include +#include #define PAGE_WIDTH FRAME_WIDTH @@ -155,5 +156,5 @@ -static inline unsigned int get_pt_flags(pte_t *pt, size_t i) +NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i) { pte_t *p = &pt[i]; @@ -168,5 +169,5 @@ } -static inline void set_pt_flags(pte_t *pt, size_t i, int flags) +NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags) { pte_t *p = &pt[i]; Index: kernel/arch/mips32/include/mm/tlb.h =================================================================== --- kernel/arch/mips32/include/mm/tlb.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/mips32/include/mm/tlb.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -39,4 +39,5 @@ #include #include +#include #define TLB_ENTRY_COUNT 48 @@ -126,5 +127,5 @@ * Probe TLB for Matching Entry. */ -static inline void tlbp(void) +NO_TRACE static inline void tlbp(void) { asm volatile ("tlbp\n\t"); @@ -136,5 +137,5 @@ * Read Indexed TLB Entry. */ -static inline void tlbr(void) +NO_TRACE static inline void tlbr(void) { asm volatile ("tlbr\n\t"); @@ -145,5 +146,5 @@ * Write Indexed TLB Entry. */ -static inline void tlbwi(void) +NO_TRACE static inline void tlbwi(void) { asm volatile ("tlbwi\n\t"); @@ -154,5 +155,5 @@ * Write Random TLB Entry. */ -static inline void tlbwr(void) +NO_TRACE static inline void tlbwr(void) { asm volatile ("tlbwr\n\t"); Index: kernel/arch/mips32/src/asm.S =================================================================== --- kernel/arch/mips32/src/asm.S (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/mips32/src/asm.S (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -1,29 +1,29 @@ -# -# Copyright (c) 2003-2004 Jakub Jermar -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# +/* + * Copyright (c) 2003 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ #include @@ -57,5 +57,4 @@ nop - .global memsetb memsetb: @@ -63,10 +62,8 @@ nop - .global memsetw memsetw: j _memsetw nop - .global memcpy @@ -78,8 +75,8 @@ memcpy_from_uspace: memcpy_to_uspace: - move $t2, $a0 # save dst + move $t2, $a0 /* save dst */ addiu $v0, $a1, 3 - li $v1, -4 # 0xfffffffffffffffc + li $v1, -4 /* 0xfffffffffffffffc */ and $v0, $v0, $v1 beq $a1, $v0, 3f @@ -149,6 +146,4 @@ move $v0, $zero - - .macro fpu_gp_save reg ctx mfc1 $t0, $\reg @@ -164,5 +159,5 @@ cfc1 $t0, $1 sw $t0, (\reg + 32) * 4(\ctx) -.endm +.endm .macro fpu_ct_restore reg ctx @@ -170,5 +165,4 @@ ctc1 $t0, $\reg .endm - .global fpu_context_save @@ -313,2 +307,7 @@ j $ra nop + +.global early_putchar +early_putchar: + j $ra + nop Index: kernel/arch/mips32/src/debugger.c =================================================================== --- kernel/arch/mips32/src/debugger.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/mips32/src/debugger.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -260,6 +260,5 @@ unsigned int i; - printf("# Count Address INPROG ONESHOT FUNCCALL In symbol\n"); - printf("-- ----- ---------- ------ ------- -------- ---------\n"); + printf("[nr] [count] [address ] [inprog] [oneshot] [funccall] [in symbol\n"); for (i = 0; i < BKPOINTS_MAX; i++) { @@ -268,5 +267,5 @@ breakpoints[i].address); - printf("%-2u %-5d %#10zx %-6s %-7s %-8s %s\n", i, + printf("%-4u %7" PRIs " %p %-8s %-9s %-10s %s\n", i, breakpoints[i].counter, breakpoints[i].address, ((breakpoints[i].flags & BKPOINT_INPROG) ? "true" : Index: kernel/arch/mips32/src/exception.c =================================================================== --- kernel/arch/mips32/src/exception.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/mips32/src/exception.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -72,9 +72,16 @@ }; -static void print_regdump(istate_t *istate) -{ - printf("PC: %#x(%s) RA: %#x(%s), SP(%p)\n", istate->epc, - symtab_fmt_name_lookup(istate->epc), istate->ra, - symtab_fmt_name_lookup(istate->ra), istate->sp); +void istate_decode(istate_t *istate) +{ + printf("at=%p\tv0=%p\tv1=%p\n", istate->at, istate->v0, istate->v1); + printf("a0=%p\ta1=%p\ta2=%p\n", istate->a0, istate->a1, istate->a2); + printf("a3=%p\tt0=%p\tt1=%p\n", istate->a3, istate->t0, istate->t1); + printf("t2=%p\tt3=%p\tt4=%p\n", istate->t2, istate->t3, istate->t4); + printf("t5=%p\tt6=%p\tt7=%p\n", istate->t5, istate->t6, istate->t7); + printf("t8=%p\tt9=%p\tgp=%p\n", istate->t8, istate->t9, istate->gp); + printf("sp=%p\tra=%p\t\n", istate->sp, istate->ra); + printf("lo=%p\thi=%p\t\n", istate->lo, istate->hi); + printf("cp0_status=%p\tcp0_epc=%p\tk1=%p\n", + istate->status, istate->epc, istate->k1); } @@ -82,7 +89,5 @@ { fault_if_from_uspace(istate, "Unhandled exception %s.", exctable[n]); - - print_regdump(istate); - panic("Unhandled exception %s.", exctable[n]); + panic_badtrap(istate, n, "Unhandled exception %s.", exctable[n]); } @@ -125,6 +130,8 @@ scheduler_fpu_lazy_request(); else { - fault_if_from_uspace(istate, "Unhandled Coprocessor Unusable Exception."); - panic("Unhandled Coprocessor Unusable Exception."); + fault_if_from_uspace(istate, + "Unhandled Coprocessor Unusable Exception."); + panic_badtrap(istate, n, + "Unhandled Coprocessor Unusable Exception."); } } @@ -162,5 +169,5 @@ static void syscall_exception(unsigned int n, istate_t *istate) { - panic("Syscall is handled through shortcut."); + fault_if_from_uspace(istate, "Syscall is handled through shortcut."); } Index: kernel/arch/mips32/src/mm/frame.c =================================================================== --- kernel/arch/mips32/src/mm/frame.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/mips32/src/mm/frame.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -249,6 +249,5 @@ void physmem_print(void) { - printf("Base Size\n"); - printf("---------- ----------\n"); + printf("[base ] [size ]\n"); size_t i; Index: kernel/arch/mips32/src/mm/tlb.c =================================================================== --- kernel/arch/mips32/src/mm/tlb.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/mips32/src/mm/tlb.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -321,11 +321,8 @@ void tlb_refill_fail(istate_t *istate) { - const char *symbol = symtab_fmt_name_lookup(istate->epc); - const char *sym2 = symtab_fmt_name_lookup(istate->ra); - - fault_if_from_uspace(istate, "TLB Refill Exception on %p.", - cp0_badvaddr_read()); - panic("%x: TLB Refill Exception at %x (%s<-%s).", cp0_badvaddr_read(), - istate->epc, symbol, sym2); + uintptr_t va = cp0_badvaddr_read(); + + fault_if_from_uspace(istate, "TLB Refill Exception on %p.", va); + panic_memtrap(istate, PF_ACCESS_READ, va, "TLB Refill Exception."); } @@ -333,20 +330,16 @@ void tlb_invalid_fail(istate_t *istate) { - const char *symbol = symtab_fmt_name_lookup(istate->epc); - - fault_if_from_uspace(istate, "TLB Invalid Exception on %p.", - cp0_badvaddr_read()); - panic("%x: TLB Invalid Exception at %x (%s).", cp0_badvaddr_read(), - istate->epc, symbol); + uintptr_t va = cp0_badvaddr_read(); + + fault_if_from_uspace(istate, "TLB Invalid Exception on %p.", va); + panic_memtrap(istate, PF_ACCESS_READ, va, "TLB Invalid Exception."); } void tlb_modified_fail(istate_t *istate) { - const char *symbol = symtab_fmt_name_lookup(istate->epc); - - fault_if_from_uspace(istate, "TLB Modified Exception on %p.", - cp0_badvaddr_read()); - panic("%x: TLB Modified Exception at %x (%s).", cp0_badvaddr_read(), - istate->epc, symbol); + uintptr_t va = cp0_badvaddr_read(); + + fault_if_from_uspace(istate, "TLB Modified Exception on %p.", va); + panic_memtrap(istate, PF_ACCESS_WRITE, va, "TLB Modified Exception."); } @@ -455,6 +448,5 @@ hi_save.value = cp0_entry_hi_read(); - printf("# ASID VPN2 MASK G V D C PFN\n"); - printf("-- ---- ------ ---- - - - - ------\n"); + printf("[nr] [asid] [vpn2] [mask] [gvdc] [pfn ]\n"); for (i = 0; i < TLB_ENTRY_COUNT; i++) { @@ -467,8 +459,8 @@ lo1.value = cp0_entry_lo1_read(); - printf("%-2u %-4u %#6x %#4x %1u %1u %1u %1u %#6x\n", + printf("%-4u %-6u %#6x %#6x %1u%1u%1u%1u %#6x\n", i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn); - printf(" %1u %1u %1u %1u %#6x\n", + printf(" %1u%1u%1u%1u %#6x\n", lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn); } Index: kernel/arch/mips32/src/panic.S =================================================================== --- kernel/arch/mips32/src/panic.S (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ (revision ) @@ -1,43 +1,0 @@ -# -# Copyright (c) 2003-2004 Jakub Jermar -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -.text - -.set noat -.set noreorder -.set nomacro - -#include - -.global panic_printf - -/* From printf return directly to halt() */ -panic_printf: - lui $ra, %hi(halt) - j printf - ori $ra, %lo(halt) Index: kernel/arch/ppc32/Makefile.inc =================================================================== --- kernel/arch/ppc32/Makefile.inc (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ppc32/Makefile.inc (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -40,5 +40,4 @@ ARCH_SOURCES = \ arch/$(KARCH)/src/context.S \ - arch/$(KARCH)/src/debug/panic.s \ arch/$(KARCH)/src/debug/stacktrace.c \ arch/$(KARCH)/src/debug/stacktrace_asm.S \ Index: kernel/arch/ppc32/include/asm.h =================================================================== --- kernel/arch/ppc32/include/asm.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ppc32/include/asm.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -40,6 +40,7 @@ #include #include - -static inline uint32_t msr_read(void) +#include + +NO_TRACE static inline uint32_t msr_read(void) { uint32_t msr; @@ -53,5 +54,5 @@ } -static inline void msr_write(uint32_t msr) +NO_TRACE static inline void msr_write(uint32_t msr) { asm volatile ( @@ -61,5 +62,5 @@ } -static inline void sr_set(uint32_t flags, asid_t asid, uint32_t sr) +NO_TRACE static inline void sr_set(uint32_t flags, asid_t asid, uint32_t sr) { asm volatile ( @@ -70,5 +71,5 @@ } -static inline uint32_t sr_get(uint32_t vaddr) +NO_TRACE static inline uint32_t sr_get(uint32_t vaddr) { uint32_t vsid; @@ -83,5 +84,5 @@ } -static inline uint32_t sdr1_get(void) +NO_TRACE static inline uint32_t sdr1_get(void) { uint32_t sdr1; @@ -103,5 +104,5 @@ * */ -static inline ipl_t interrupts_enable(void) +NO_TRACE static inline ipl_t interrupts_enable(void) { ipl_t ipl = msr_read(); @@ -118,5 +119,5 @@ * */ -static inline ipl_t interrupts_disable(void) +NO_TRACE static inline ipl_t interrupts_disable(void) { ipl_t ipl = msr_read(); @@ -132,5 +133,5 @@ * */ -static inline void interrupts_restore(ipl_t ipl) +NO_TRACE static inline void interrupts_restore(ipl_t ipl) { msr_write((msr_read() & (~MSR_EE)) | (ipl & MSR_EE)); @@ -144,5 +145,5 @@ * */ -static inline ipl_t interrupts_read(void) +NO_TRACE static inline ipl_t interrupts_read(void) { return msr_read(); @@ -154,5 +155,5 @@ * */ -static inline bool interrupts_disabled(void) +NO_TRACE static inline bool interrupts_disabled(void) { return ((msr_read() & MSR_EE) == 0); @@ -166,5 +167,5 @@ * */ -static inline uintptr_t get_stack_base(void) +NO_TRACE static inline uintptr_t get_stack_base(void) { uintptr_t base; @@ -179,6 +180,36 @@ } -static inline void cpu_sleep(void) -{ +NO_TRACE static inline void cpu_sleep(void) +{ +} + +NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v) +{ + *port = v; +} + +NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v) +{ + *port = v; +} + +NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v) +{ + *port = v; +} + +NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port) +{ + return *port; +} + +NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port) +{ + return *port; +} + +NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port) +{ + return *port; } @@ -187,34 +218,4 @@ extern void userspace_asm(uintptr_t uspace_uarg, uintptr_t stack, uintptr_t entry); -static inline void pio_write_8(ioport8_t *port, uint8_t v) -{ - *port = v; -} - -static inline void pio_write_16(ioport16_t *port, uint16_t v) -{ - *port = v; -} - -static inline void pio_write_32(ioport32_t *port, uint32_t v) -{ - *port = v; -} - -static inline uint8_t pio_read_8(ioport8_t *port) -{ - return *port; -} - -static inline uint16_t pio_read_16(ioport16_t *port) -{ - return *port; -} - -static inline uint32_t pio_read_32(ioport32_t *port) -{ - return *port; -} - #endif Index: kernel/arch/ppc32/include/atomic.h =================================================================== --- kernel/arch/ppc32/include/atomic.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ppc32/include/atomic.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -36,5 +36,7 @@ #define KERN_ppc32_ATOMIC_H_ -static inline void atomic_inc(atomic_t *val) +#include + +NO_TRACE static inline void atomic_inc(atomic_t *val) { atomic_count_t tmp; @@ -54,5 +56,5 @@ } -static inline void atomic_dec(atomic_t *val) +NO_TRACE static inline void atomic_dec(atomic_t *val) { atomic_count_t tmp; @@ -72,5 +74,5 @@ } -static inline atomic_count_t atomic_postinc(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val) { atomic_inc(val); @@ -78,5 +80,5 @@ } -static inline atomic_count_t atomic_postdec(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val) { atomic_dec(val); @@ -84,5 +86,5 @@ } -static inline atomic_count_t atomic_preinc(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_preinc(atomic_t *val) { atomic_inc(val); @@ -90,5 +92,5 @@ } -static inline atomic_count_t atomic_predec(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_predec(atomic_t *val) { atomic_dec(val); Index: kernel/arch/ppc32/include/barrier.h =================================================================== --- kernel/arch/ppc32/include/barrier.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ppc32/include/barrier.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -36,4 +36,6 @@ #define KERN_ppc32_BARRIER_H_ +#include + #define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") #define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") @@ -58,5 +60,5 @@ */ -static inline void smc_coherence(void *addr) +NO_TRACE static inline void smc_coherence(void *addr) { asm volatile ( @@ -70,5 +72,5 @@ } -static inline void smc_coherence_block(void *addr, unsigned int len) +NO_TRACE static inline void smc_coherence_block(void *addr, unsigned int len) { unsigned int i; Index: kernel/arch/ppc32/include/cpu.h =================================================================== --- kernel/arch/ppc32/include/cpu.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ppc32/include/cpu.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -52,4 +52,5 @@ #include +#include typedef struct { @@ -58,5 +59,5 @@ } __attribute__ ((packed)) cpu_arch_t; -static inline void cpu_version(cpu_arch_t *info) +NO_TRACE static inline void cpu_version(cpu_arch_t *info) { asm volatile ( Index: kernel/arch/ppc32/include/cycle.h =================================================================== --- kernel/arch/ppc32/include/cycle.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ppc32/include/cycle.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -36,5 +36,7 @@ #define KERN_ppc32_CYCLE_H_ -static inline uint64_t get_cycle(void) +#include + +NO_TRACE static inline uint64_t get_cycle(void) { uint32_t lower; Index: kernel/arch/ppc32/include/exception.h =================================================================== --- kernel/arch/ppc32/include/exception.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ppc32/include/exception.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -38,4 +38,5 @@ #include #include +#include typedef struct istate { @@ -81,5 +82,6 @@ } istate_t; -static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) +NO_TRACE static inline void istate_set_retaddr(istate_t *istate, + uintptr_t retaddr) { istate->pc = retaddr; @@ -91,15 +93,15 @@ * */ -static inline int istate_from_uspace(istate_t *istate) +NO_TRACE static inline int istate_from_uspace(istate_t *istate) { return (istate->srr1 & MSR_PR) != 0; } -static inline unative_t istate_get_pc(istate_t *istate) +NO_TRACE static inline unative_t istate_get_pc(istate_t *istate) { return istate->pc; } -static inline unative_t istate_get_fp(istate_t *istate) +NO_TRACE static inline unative_t istate_get_fp(istate_t *istate) { return istate->sp; Index: kernel/arch/ppc32/include/mm/frame.h =================================================================== --- kernel/arch/ppc32/include/mm/frame.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ppc32/include/mm/frame.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -43,8 +43,9 @@ #include +#include extern uintptr_t last_frame; -static inline uint32_t physmem_top(void) +NO_TRACE static inline uint32_t physmem_top(void) { uint32_t physmem; Index: kernel/arch/ppc32/include/mm/page.h =================================================================== --- kernel/arch/ppc32/include/mm/page.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ppc32/include/mm/page.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -37,4 +37,5 @@ #include +#include #define PAGE_WIDTH FRAME_WIDTH @@ -153,5 +154,5 @@ } pte_t; -static inline unsigned int get_pt_flags(pte_t *pt, size_t i) +NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i) { pte_t *entry = &pt[i]; @@ -166,5 +167,5 @@ } -static inline void set_pt_flags(pte_t *pt, size_t i, int flags) +NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags) { pte_t *entry = &pt[i]; Index: kernel/arch/ppc32/include/types.h =================================================================== --- kernel/arch/ppc32/include/types.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ppc32/include/types.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -50,9 +50,9 @@ } fncptr_t; -/**< Formats for uintptr_t, size_t */ +/** Formats for uintptr_t, size_t */ #define PRIp "x" #define PRIs "u" -/**< Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */ +/** Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */ #define PRId8 "d" #define PRId16 "d" Index: kernel/arch/ppc32/src/asm.S =================================================================== --- kernel/arch/ppc32/src/asm.S (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ppc32/src/asm.S (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -1,29 +1,29 @@ -# -# Copyright (c) 2005 Martin Decky -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# +/* + * Copyright (c) 2005 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ #include @@ -42,12 +42,15 @@ .global memcpy_from_uspace_failover_address .global memcpy_to_uspace_failover_address +.global early_putchar userspace_asm: - # r3 = uspace_uarg - # r4 = stack - # r5 = entry - - # disable interrupts + /* + * r3 = uspace_uarg + * r4 = stack + * r5 = entry + */ + + /* Disable interrupts */ mfmsr r31 @@ -55,9 +58,9 @@ mtmsr r31 - # set entry point + /* Set entry point */ mtsrr0 r5 - # set problem state, enable interrupts + /* Set problem state, enable interrupts */ ori r31, r31, MSR_PR @@ -65,13 +68,13 @@ mtsrr1 r31 - # set stack + /* Set stack */ mr sp, r4 - # %r6 is defined to hold pcb_ptr - set it to 0 + /* %r6 is defined to hold pcb_ptr - set it to 0 */ xor r6, r6, r6 - # jump to userspace + /* Jump to userspace */ rfi @@ -79,5 +82,5 @@ iret: - # disable interrupts + /* Disable interrupts */ mfmsr r31 @@ -141,10 +144,10 @@ iret_syscall: - # reset decrementer + /* Reset decrementer */ li r31, 1000 mtdec r31 - # disable interrupts + /* Disable interrupts */ mfmsr r31 @@ -278,5 +281,8 @@ memcpy_from_uspace_failover_address: memcpy_to_uspace_failover_address: - # return zero, failure + /* Return zero, failure */ xor r3, r3, r3 blr + +early_putchar: + blr Index: kernel/arch/ppc32/src/debug/panic.s =================================================================== --- kernel/arch/ppc32/src/debug/panic.s (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ (revision ) @@ -1,38 +1,0 @@ -# -# Copyright (c) 2005 Martin Decky -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -#include - -.text -.global panic_printf - -panic_printf: - lis %r14, halt@ha - addi %r14, %r14, halt@l - mtlr %r14 # fake stack to make printf return to halt - b printf Index: kernel/arch/ppc32/src/interrupt.c =================================================================== --- kernel/arch/ppc32/src/interrupt.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ppc32/src/interrupt.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -50,4 +50,30 @@ :: [dec] "r" (1000) ); +} + +void istate_decode(istate_t *istate) +{ + printf("r0 =%p\tr1 =%p\tr2 =%p\n", istate->r0, istate->sp, istate->r2); + printf("r3 =%p\tr4 =%p\tr5 =%p\n", istate->r3, istate->r4, istate->r5); + printf("r6 =%p\tr7 =%p\tr8 =%p\n", istate->r6, istate->r7, istate->r8); + printf("r9 =%p\tr10=%p\tr11=%p\n", + istate->r9, istate->r10, istate->r11); + printf("r12=%p\tr13=%p\tr14=%p\n", + istate->r12, istate->r13, istate->r14); + printf("r15=%p\tr16=%p\tr17=%p\n", + istate->r15, istate->r16, istate->r17); + printf("r18=%p\tr19=%p\tr20=%p\n", + istate->r18, istate->r19, istate->r20); + printf("r21=%p\tr22=%p\tr23=%p\n", + istate->r21, istate->r22, istate->r23); + printf("r24=%p\tr25=%p\tr26=%p\n", + istate->r24, istate->r25, istate->r26); + printf("r27=%p\tr28=%p\tr29=%p\n", + istate->r27, istate->r28, istate->r29); + printf("r30=%p\tr31=%p\n", istate->r30, istate->r31); + printf("cr =%p\tpc =%p\tlr =%p\n", istate->cr, istate->pc, istate->lr); + printf("ctr=%p\txer=%p\tdar=%p\n", + istate->ctr, istate->xer, istate->dar); + printf("srr1=%p\n", istate->srr1); } Index: kernel/arch/ppc32/src/mm/frame.c =================================================================== --- kernel/arch/ppc32/src/mm/frame.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ppc32/src/mm/frame.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -45,6 +45,5 @@ void physmem_print(void) { - printf("Base Size\n"); - printf("---------- ----------\n"); + printf("[base ] [size ]\n"); size_t i; @@ -61,19 +60,23 @@ for (i = 0; i < memmap.cnt; i++) { - pfn_t start = ADDR2PFN(ALIGN_UP((uintptr_t) memmap.zones[i].start, - FRAME_SIZE)); - size_t size = SIZE2FRAMES(ALIGN_DOWN(memmap.zones[i].size, FRAME_SIZE)); + /* To be safe, make the available zone possibly smaller */ + uintptr_t new_start = ALIGN_UP((uintptr_t) memmap.zones[i].start, + FRAME_SIZE); + size_t new_size = ALIGN_DOWN(memmap.zones[i].size - + (new_start - ((uintptr_t) memmap.zones[i].start)), FRAME_SIZE); + + pfn_t pfn = ADDR2PFN(new_start); + size_t count = SIZE2FRAMES(new_size); pfn_t conf; - if ((minconf < start) || (minconf >= start + size)) - conf = start; + if ((minconf < pfn) || (minconf >= pfn + count)) + conf = pfn; else conf = minconf; - zone_create(start, size, conf, 0); - if (last_frame < ALIGN_UP((uintptr_t) memmap.zones[i].start - + memmap.zones[i].size, FRAME_SIZE)) - last_frame = ALIGN_UP((uintptr_t) memmap.zones[i].start - + memmap.zones[i].size, FRAME_SIZE); + zone_create(pfn, count, conf, 0); + + if (last_frame < ALIGN_UP(new_start + new_size, FRAME_SIZE)) + last_frame = ALIGN_UP(new_start + new_size, FRAME_SIZE); } Index: kernel/arch/ppc32/src/mm/tlb.c =================================================================== --- kernel/arch/ppc32/src/mm/tlb.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/ppc32/src/mm/tlb.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -111,11 +111,7 @@ static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) { - const char *symbol = symtab_fmt_name_lookup(istate->pc); - const char *sym2 = symtab_fmt_name_lookup(istate->lr); - - fault_if_from_uspace(istate, - "PHT Refill Exception on %p.", badvaddr); - panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr, - istate->pc, symbol, sym2); + fault_if_from_uspace(istate, "PHT Refill Exception on %p.", badvaddr); + panic_memtrap(istate, PF_ACCESS_READ, badvaddr, + "PHT Refill Exception."); } Index: kernel/arch/sparc64/Makefile.inc =================================================================== --- kernel/arch/sparc64/Makefile.inc (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/Makefile.inc (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -64,5 +64,4 @@ arch/$(KARCH)/src/asm.S \ arch/$(KARCH)/src/$(USARCH)/asm.S \ - arch/$(KARCH)/src/panic.S \ arch/$(KARCH)/src/console.c \ arch/$(KARCH)/src/context.S \ Index: kernel/arch/sparc64/include/asm.h =================================================================== --- kernel/arch/sparc64/include/asm.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/include/asm.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup sparc64 +/** @addtogroup sparc64 * @{ */ @@ -43,6 +43,7 @@ #include #include - -static inline void pio_write_8(ioport8_t *port, uint8_t v) +#include + +NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v) { *port = v; @@ -50,5 +51,5 @@ } -static inline void pio_write_16(ioport16_t *port, uint16_t v) +NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v) { *port = v; @@ -56,5 +57,5 @@ } -static inline void pio_write_32(ioport32_t *port, uint32_t v) +NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v) { *port = v; @@ -62,31 +63,22 @@ } -static inline uint8_t pio_read_8(ioport8_t *port) -{ - uint8_t rv; - - rv = *port; +NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port) +{ + uint8_t rv = *port; memory_barrier(); - return rv; } -static inline uint16_t pio_read_16(ioport16_t *port) -{ - uint16_t rv; - - rv = *port; +NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port) +{ + uint16_t rv = *port; memory_barrier(); - return rv; } -static inline uint32_t pio_read_32(ioport32_t *port) -{ - uint32_t rv; - - rv = *port; +NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port) +{ + uint32_t rv = *port; memory_barrier(); - return rv; } @@ -95,10 +87,14 @@ * * @return Value of PSTATE register. - */ -static inline uint64_t pstate_read(void) -{ - uint64_t v; - - asm volatile ("rdpr %%pstate, %0\n" : "=r" (v)); + * + */ +NO_TRACE static inline uint64_t pstate_read(void) +{ + uint64_t v; + + asm volatile ( + "rdpr %%pstate, %[v]\n" + : [v] "=r" (v) + ); return v; @@ -108,8 +104,13 @@ * * @param v New value of PSTATE register. - */ -static inline void pstate_write(uint64_t v) -{ - asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0)); + * + */ +NO_TRACE static inline void pstate_write(uint64_t v) +{ + asm volatile ( + "wrpr %[v], %[zero], %%pstate\n" + :: [v] "r" (v), + [zero] "i" (0) + ); } @@ -117,10 +118,14 @@ * * @return Value of TICK_comapre register. - */ -static inline uint64_t tick_compare_read(void) -{ - uint64_t v; - - asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v)); + * + */ +NO_TRACE static inline uint64_t tick_compare_read(void) +{ + uint64_t v; + + asm volatile ( + "rd %%tick_cmpr, %[v]\n" + : [v] "=r" (v) + ); return v; @@ -130,8 +135,13 @@ * * @param v New value of TICK_comapre register. - */ -static inline void tick_compare_write(uint64_t v) -{ - asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0)); + * + */ +NO_TRACE static inline void tick_compare_write(uint64_t v) +{ + asm volatile ( + "wr %[v], %[zero], %%tick_cmpr\n" + :: [v] "r" (v), + [zero] "i" (0) + ); } @@ -139,10 +149,14 @@ * * @return Value of STICK_compare register. - */ -static inline uint64_t stick_compare_read(void) -{ - uint64_t v; - - asm volatile ("rd %%asr25, %0\n" : "=r" (v)); + * + */ +NO_TRACE static inline uint64_t stick_compare_read(void) +{ + uint64_t v; + + asm volatile ( + "rd %%asr25, %[v]\n" + : [v] "=r" (v) + ); return v; @@ -152,8 +166,13 @@ * * @param v New value of STICK_comapre register. - */ -static inline void stick_compare_write(uint64_t v) -{ - asm volatile ("wr %0, %1, %%asr25\n" : : "r" (v), "i" (0)); + * + */ +NO_TRACE static inline void stick_compare_write(uint64_t v) +{ + asm volatile ( + "wr %[v], %[zero], %%asr25\n" + :: [v] "r" (v), + [zero] "i" (0) + ); } @@ -161,10 +180,14 @@ * * @return Value of TICK register. - */ -static inline uint64_t tick_read(void) -{ - uint64_t v; - - asm volatile ("rdpr %%tick, %0\n" : "=r" (v)); + * + */ +NO_TRACE static inline uint64_t tick_read(void) +{ + uint64_t v; + + asm volatile ( + "rdpr %%tick, %[v]\n" + : [v] "=r" (v) + ); return v; @@ -174,8 +197,13 @@ * * @param v New value of TICK register. - */ -static inline void tick_write(uint64_t v) -{ - asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0)); + * + */ +NO_TRACE static inline void tick_write(uint64_t v) +{ + asm volatile ( + "wrpr %[v], %[zero], %%tick\n" + :: [v] "r" (v), + [zero] "i" (0) + ); } @@ -183,10 +211,14 @@ * * @return Value of FPRS register. - */ -static inline uint64_t fprs_read(void) -{ - uint64_t v; - - asm volatile ("rd %%fprs, %0\n" : "=r" (v)); + * + */ +NO_TRACE static inline uint64_t fprs_read(void) +{ + uint64_t v; + + asm volatile ( + "rd %%fprs, %[v]\n" + : [v] "=r" (v) + ); return v; @@ -196,8 +228,13 @@ * * @param v New value of FPRS register. - */ -static inline void fprs_write(uint64_t v) -{ - asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0)); + * + */ +NO_TRACE static inline void fprs_write(uint64_t v) +{ + asm volatile ( + "wr %[v], %[zero], %%fprs\n" + :: [v] "r" (v), + [zero] "i" (0) + ); } @@ -205,11 +242,15 @@ * * @return Value of SOFTINT register. - */ -static inline uint64_t softint_read(void) -{ - uint64_t v; - - asm volatile ("rd %%softint, %0\n" : "=r" (v)); - + * + */ +NO_TRACE static inline uint64_t softint_read(void) +{ + uint64_t v; + + asm volatile ( + "rd %%softint, %[v]\n" + : [v] "=r" (v) + ); + return v; } @@ -218,8 +259,13 @@ * * @param v New value of SOFTINT register. - */ -static inline void softint_write(uint64_t v) -{ - asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0)); + * + */ +NO_TRACE static inline void softint_write(uint64_t v) +{ + asm volatile ( + "wr %[v], %[zero], %%softint\n" + :: [v] "r" (v), + [zero] "i" (0) + ); } @@ -229,8 +275,13 @@ * * @param v New value of CLEAR_SOFTINT register. - */ -static inline void clear_softint_write(uint64_t v) -{ - asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0)); + * + */ +NO_TRACE static inline void clear_softint_write(uint64_t v) +{ + asm volatile ( + "wr %[v], %[zero], %%clear_softint\n" + :: [v] "r" (v), + [zero] "i" (0) + ); } @@ -240,8 +291,13 @@ * * @param v New value of SET_SOFTINT register. - */ -static inline void set_softint_write(uint64_t v) -{ - asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0)); + * + */ +NO_TRACE static inline void set_softint_write(uint64_t v) +{ + asm volatile ( + "wr %[v], %[zero], %%set_softint\n" + :: [v] "r" (v), + [zero] "i" (0) + ); } @@ -252,10 +308,10 @@ * * @return Old interrupt priority level. - */ -static inline ipl_t interrupts_enable(void) { + * + */ +NO_TRACE static inline ipl_t interrupts_enable(void) { pstate_reg_t pstate; - uint64_t value; - - value = pstate_read(); + uint64_t value = pstate_read(); + pstate.value = value; pstate.ie = true; @@ -271,10 +327,10 @@ * * @return Old interrupt priority level. - */ -static inline ipl_t interrupts_disable(void) { + * + */ +NO_TRACE static inline ipl_t interrupts_disable(void) { pstate_reg_t pstate; - uint64_t value; - - value = pstate_read(); + uint64_t value = pstate_read(); + pstate.value = value; pstate.ie = false; @@ -289,6 +345,7 @@ * * @param ipl Saved interrupt priority level. - */ -static inline void interrupts_restore(ipl_t ipl) { + * + */ +NO_TRACE static inline void interrupts_restore(ipl_t ipl) { pstate_reg_t pstate; @@ -303,6 +360,7 @@ * * @return Current interrupt priority level. - */ -static inline ipl_t interrupts_read(void) { + * + */ +NO_TRACE static inline ipl_t interrupts_read(void) { return (ipl_t) pstate_read(); } @@ -313,8 +371,8 @@ * */ -static inline bool interrupts_disabled(void) +NO_TRACE static inline bool interrupts_disabled(void) { pstate_reg_t pstate; - + pstate.value = pstate_read(); return !pstate.ie; @@ -326,10 +384,15 @@ * The stack is assumed to be STACK_SIZE bytes long. * The stack must start on page boundary. - */ -static inline uintptr_t get_stack_base(void) + * + */ +NO_TRACE static inline uintptr_t get_stack_base(void) { uintptr_t unbiased_sp; - asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS)); + asm volatile ( + "add %%sp, %[stack_bias], %[unbiased_sp]\n" + : [unbiased_sp] "=r" (unbiased_sp) + : [stack_bias] "i" (STACK_BIAS) + ); return ALIGN_DOWN(unbiased_sp, STACK_SIZE); @@ -339,10 +402,14 @@ * * @return Value of VER register. - */ -static inline uint64_t ver_read(void) -{ - uint64_t v; - - asm volatile ("rdpr %%ver, %0\n" : "=r" (v)); + * + */ +NO_TRACE static inline uint64_t ver_read(void) +{ + uint64_t v; + + asm volatile ( + "rdpr %%ver, %[v]\n" + : [v] "=r" (v) + ); return v; @@ -352,10 +419,14 @@ * * @return Current value in TPC. - */ -static inline uint64_t tpc_read(void) -{ - uint64_t v; - - asm volatile ("rdpr %%tpc, %0\n" : "=r" (v)); + * + */ +NO_TRACE static inline uint64_t tpc_read(void) +{ + uint64_t v; + + asm volatile ( + "rdpr %%tpc, %[v]\n" + : [v] "=r" (v) + ); return v; @@ -365,10 +436,14 @@ * * @return Current value in TL. - */ -static inline uint64_t tl_read(void) -{ - uint64_t v; - - asm volatile ("rdpr %%tl, %0\n" : "=r" (v)); + * + */ +NO_TRACE static inline uint64_t tl_read(void) +{ + uint64_t v; + + asm volatile ( + "rdpr %%tl, %[v]\n" + : [v] "=r" (v) + ); return v; @@ -378,10 +453,14 @@ * * @return Current value in TBA. - */ -static inline uint64_t tba_read(void) -{ - uint64_t v; - - asm volatile ("rdpr %%tba, %0\n" : "=r" (v)); + * + */ +NO_TRACE static inline uint64_t tba_read(void) +{ + uint64_t v; + + asm volatile ( + "rdpr %%tba, %[v]\n" + : [v] "=r" (v) + ); return v; @@ -391,8 +470,13 @@ * * @param v New value of TBA. - */ -static inline void tba_write(uint64_t v) -{ - asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0)); + * + */ +NO_TRACE static inline void tba_write(uint64_t v) +{ + asm volatile ( + "wrpr %[v], %[zero], %%tba\n" + :: [v] "r" (v), + [zero] "i" (0) + ); } @@ -400,13 +484,20 @@ * * @param asi ASI determining the alternate space. - * @param va Virtual address within the ASI. - * - * @return Value read from the virtual address in the specified address space. - */ -static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va) -{ - uint64_t v; - - asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi)); + * @param va Virtual address within the ASI. + * + * @return Value read from the virtual address in + * the specified address space. + * + */ +NO_TRACE static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va) +{ + uint64_t v; + + asm volatile ( + "ldxa [%[va]] %[asi], %[v]\n" + : [v] "=r" (v) + : [va] "r" (va), + [asi] "i" ((unsigned int) asi) + ); return v; @@ -416,14 +507,21 @@ * * @param asi ASI determining the alternate space. - * @param va Virtual address within the ASI. - * @param v Value to be written. - */ -static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v) -{ - asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory"); + * @param va Virtual address within the ASI. + * @param v Value to be written. + * + */ +NO_TRACE static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v) +{ + asm volatile ( + "stxa %[v], [%[va]] %[asi]\n" + :: [v] "r" (v), + [va] "r" (va), + [asi] "i" ((unsigned int) asi) + : "memory" + ); } /** Flush all valid register windows to memory. */ -static inline void flushw(void) +NO_TRACE static inline void flushw(void) { asm volatile ("flushw\n"); @@ -431,5 +529,5 @@ /** Switch to nucleus by setting TL to 1. */ -static inline void nucleus_enter(void) +NO_TRACE static inline void nucleus_enter(void) { asm volatile ("wrpr %g0, 1, %tl\n"); @@ -437,5 +535,5 @@ /** Switch from nucleus by setting TL to 0. */ -static inline void nucleus_leave(void) +NO_TRACE static inline void nucleus_leave(void) { asm volatile ("wrpr %g0, %g0, %tl\n"); Index: kernel/arch/sparc64/include/atomic.h =================================================================== --- kernel/arch/sparc64/include/atomic.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/include/atomic.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -39,4 +39,5 @@ #include #include +#include /** Atomic add operation. @@ -50,5 +51,6 @@ * */ -static inline atomic_count_t atomic_add(atomic_t *val, atomic_count_t i) +NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val, + atomic_count_t i) { atomic_count_t a; @@ -72,35 +74,35 @@ } -static inline atomic_count_t atomic_preinc(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_preinc(atomic_t *val) { return atomic_add(val, 1) + 1; } -static inline atomic_count_t atomic_postinc(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val) { return atomic_add(val, 1); } -static inline atomic_count_t atomic_predec(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_predec(atomic_t *val) { return atomic_add(val, -1) - 1; } -static inline atomic_count_t atomic_postdec(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val) { return atomic_add(val, -1); } -static inline void atomic_inc(atomic_t *val) +NO_TRACE static inline void atomic_inc(atomic_t *val) { (void) atomic_add(val, 1); } -static inline void atomic_dec(atomic_t *val) +NO_TRACE static inline void atomic_dec(atomic_t *val) { (void) atomic_add(val, -1); } -static inline atomic_count_t test_and_set(atomic_t *val) +NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val) { atomic_count_t v = 1; @@ -117,5 +119,5 @@ } -static inline void atomic_lock_arch(atomic_t *val) +NO_TRACE static inline void atomic_lock_arch(atomic_t *val) { atomic_count_t tmp1 = 1; Index: kernel/arch/sparc64/include/barrier.h =================================================================== --- kernel/arch/sparc64/include/barrier.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/include/barrier.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup sparc64 +/** @addtogroup sparc64 * @{ */ @@ -36,8 +36,14 @@ #define KERN_sparc64_BARRIER_H_ +#include + #ifdef KERNEL + #include + #else + #include + #endif @@ -45,31 +51,47 @@ * Our critical section barriers are prepared for the weakest RMO memory model. */ -#define CS_ENTER_BARRIER() \ - asm volatile ( \ - "membar #LoadLoad | #LoadStore\n" \ - ::: "memory" \ - ) -#define CS_LEAVE_BARRIER() \ - asm volatile ( \ - "membar #StoreStore\n" \ - "membar #LoadStore\n" \ - ::: "memory" \ +#define CS_ENTER_BARRIER() \ + asm volatile ( \ + "membar #LoadLoad | #LoadStore\n" \ + ::: "memory" \ ) -#define memory_barrier() \ - asm volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory") -#define read_barrier() \ - asm volatile ("membar #LoadLoad\n" ::: "memory") -#define write_barrier() \ - asm volatile ("membar #StoreStore\n" ::: "memory") +#define CS_LEAVE_BARRIER() \ + asm volatile ( \ + "membar #StoreStore\n" \ + "membar #LoadStore\n" \ + ::: "memory" \ + ) -#define flush(a) \ - asm volatile ("flush %0\n" :: "r" ((a)) : "memory") +#define memory_barrier() \ + asm volatile ( \ + "membar #LoadLoad | #StoreStore\n" \ + ::: "memory" \ + ) + +#define read_barrier() \ + asm volatile ( \ + "membar #LoadLoad\n" \ + ::: "memory" \ + ) + +#define write_barrier() \ + asm volatile ( \ + "membar #StoreStore\n" \ + ::: "memory" \ + ) + +#define flush(a) \ + asm volatile ( \ + "flush %[reg]\n" \ + :: [reg] "r" ((a)) \ + : "memory" \ + ) /** Flush Instruction pipeline. */ -static inline void flush_pipeline(void) +NO_TRACE static inline void flush_pipeline(void) { uint64_t pc; - + /* * The FLUSH instruction takes address parameter. @@ -80,51 +102,56 @@ * the %pc register will always be in the range mapped by * DTLB. + * */ - - asm volatile ( - "rd %%pc, %0\n" - "flush %0\n" - : "=&r" (pc) + + asm volatile ( + "rd %%pc, %[pc]\n" + "flush %[pc]\n" + : [pc] "=&r" (pc) ); } /** Memory Barrier instruction. */ -static inline void membar(void) +NO_TRACE static inline void membar(void) { - asm volatile ("membar #Sync\n"); + asm volatile ( + "membar #Sync\n" + ); } #if defined (US) -#define smc_coherence(a) \ -{ \ - write_barrier(); \ - flush((a)); \ -} +#define FLUSH_INVAL_MIN 4 -#define FLUSH_INVAL_MIN 4 -#define smc_coherence_block(a, l) \ -{ \ - unsigned long i; \ - write_barrier(); \ - for (i = 0; i < (l); i += FLUSH_INVAL_MIN) \ - flush((void *)(a) + i); \ -} +#define smc_coherence(a) \ + do { \ + write_barrier(); \ + flush((a)); \ + } while (0) + +#define smc_coherence_block(a, l) \ + do { \ + unsigned long i; \ + write_barrier(); \ + \ + for (i = 0; i < (l); i += FLUSH_INVAL_MIN) \ + flush((void *)(a) + i); \ + } while (0) #elif defined (US3) -#define smc_coherence(a) \ -{ \ - write_barrier(); \ - flush_pipeline(); \ -} +#define smc_coherence(a) \ + do { \ + write_barrier(); \ + flush_pipeline(); \ + } while (0) -#define smc_coherence_block(a, l) \ -{ \ - write_barrier(); \ - flush_pipeline(); \ -} +#define smc_coherence_block(a, l) \ + do { \ + write_barrier(); \ + flush_pipeline(); \ + } while (0) -#endif /* defined(US3) */ +#endif /* defined(US3) */ #endif Index: kernel/arch/sparc64/include/cycle.h =================================================================== --- kernel/arch/sparc64/include/cycle.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/include/cycle.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -36,7 +36,8 @@ #define KERN_sparc64_CYCLE_H_ -#include +#include +#include -static inline uint64_t get_cycle(void) +NO_TRACE static inline uint64_t get_cycle(void) { return tick_read(); Index: kernel/arch/sparc64/include/faddr.h =================================================================== --- kernel/arch/sparc64/include/faddr.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/include/faddr.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup sparc64 +/** @addtogroup sparc64 * @{ */ @@ -38,5 +38,5 @@ #include -#define FADDR(fptr) ((uintptr_t) (fptr)) +#define FADDR(fptr) ((uintptr_t) (fptr)) #endif Index: kernel/arch/sparc64/include/interrupt.h =================================================================== --- kernel/arch/sparc64/include/interrupt.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/include/interrupt.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -39,39 +39,43 @@ #include #include +#include -#define IVT_ITEMS 15 -#define IVT_FIRST 1 +#define IVT_ITEMS 15 +#define IVT_FIRST 1 /* This needs to be defined for inter-architecture API portability. */ -#define VECTOR_TLB_SHOOTDOWN_IPI 0 +#define VECTOR_TLB_SHOOTDOWN_IPI 0 enum { IPI_TLB_SHOOTDOWN = VECTOR_TLB_SHOOTDOWN_IPI -}; +}; typedef struct istate { - uint64_t tnpc; - uint64_t tpc; - uint64_t tstate; + uint64_t tnpc; + uint64_t tpc; + uint64_t tstate; } istate_t; -static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) +NO_TRACE static inline void istate_set_retaddr(istate_t *istate, + uintptr_t retaddr) { istate->tpc = retaddr; } -static inline int istate_from_uspace(istate_t *istate) +NO_TRACE static inline int istate_from_uspace(istate_t *istate) { return !(istate->tstate & TSTATE_PRIV_BIT); } -static inline unative_t istate_get_pc(istate_t *istate) +NO_TRACE static inline unative_t istate_get_pc(istate_t *istate) { return istate->tpc; } -static inline unative_t istate_get_fp(istate_t *istate) +NO_TRACE static inline unative_t istate_get_fp(istate_t *istate) { - return 0; /* TODO */ + /* TODO */ + + return 0; } Index: kernel/arch/sparc64/include/mm/as.h =================================================================== --- kernel/arch/sparc64/include/mm/as.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/include/mm/as.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup sparc64mm +/** @addtogroup sparc64mm * @{ */ @@ -37,7 +37,11 @@ #if defined (SUN4U) + #include + #elif defined (SUN4V) + #include + #endif Index: kernel/arch/sparc64/include/mm/frame.h =================================================================== --- kernel/arch/sparc64/include/mm/frame.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/include/mm/frame.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup sparc64mm +/** @addtogroup sparc64mm * @{ */ @@ -37,7 +37,11 @@ #if defined (SUN4U) + #include + #elif defined (SUN4V) + #include + #endif Index: kernel/arch/sparc64/include/mm/sun4u/tlb.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4u/tlb.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/include/mm/sun4u/tlb.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -100,4 +100,5 @@ #include #include +#include #include #include @@ -242,5 +243,5 @@ * Determine the number of entries in the DMMU's small TLB. */ -static inline uint16_t tlb_dsmall_size(void) +NO_TRACE static inline uint16_t tlb_dsmall_size(void) { return 16; @@ -250,5 +251,5 @@ * Determine the number of entries in each DMMU's big TLB. */ -static inline uint16_t tlb_dbig_size(void) +NO_TRACE static inline uint16_t tlb_dbig_size(void) { return 512; @@ -258,5 +259,5 @@ * Determine the number of entries in the IMMU's small TLB. */ -static inline uint16_t tlb_ismall_size(void) +NO_TRACE static inline uint16_t tlb_ismall_size(void) { return 16; @@ -266,5 +267,5 @@ * Determine the number of entries in the IMMU's big TLB. */ -static inline uint16_t tlb_ibig_size(void) +NO_TRACE static inline uint16_t tlb_ibig_size(void) { if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS) @@ -280,5 +281,5 @@ * @return Current value of Primary Context Register. */ -static inline uint64_t mmu_primary_context_read(void) +NO_TRACE static inline uint64_t mmu_primary_context_read(void) { return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); @@ -289,5 +290,5 @@ * @param v New value of Primary Context Register. */ -static inline void mmu_primary_context_write(uint64_t v) +NO_TRACE static inline void mmu_primary_context_write(uint64_t v) { asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); @@ -299,5 +300,5 @@ * @return Current value of Secondary Context Register. */ -static inline uint64_t mmu_secondary_context_read(void) +NO_TRACE static inline uint64_t mmu_secondary_context_read(void) { return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); @@ -308,5 +309,5 @@ * @param v New value of Primary Context Register. */ -static inline void mmu_secondary_context_write(uint64_t v) +NO_TRACE static inline void mmu_secondary_context_write(uint64_t v) { asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); @@ -323,5 +324,5 @@ * Register. */ -static inline uint64_t itlb_data_access_read(size_t entry) +NO_TRACE static inline uint64_t itlb_data_access_read(size_t entry) { itlb_data_access_addr_t reg; @@ -337,5 +338,5 @@ * @param value Value to be written. */ -static inline void itlb_data_access_write(size_t entry, uint64_t value) +NO_TRACE static inline void itlb_data_access_write(size_t entry, uint64_t value) { itlb_data_access_addr_t reg; @@ -354,5 +355,5 @@ * Register. */ -static inline uint64_t dtlb_data_access_read(size_t entry) +NO_TRACE static inline uint64_t dtlb_data_access_read(size_t entry) { dtlb_data_access_addr_t reg; @@ -368,5 +369,5 @@ * @param value Value to be written. */ -static inline void dtlb_data_access_write(size_t entry, uint64_t value) +NO_TRACE static inline void dtlb_data_access_write(size_t entry, uint64_t value) { dtlb_data_access_addr_t reg; @@ -384,5 +385,5 @@ * @return Current value of specified IMMU TLB Tag Read Register. */ -static inline uint64_t itlb_tag_read_read(size_t entry) +NO_TRACE static inline uint64_t itlb_tag_read_read(size_t entry) { itlb_tag_read_addr_t tag; @@ -399,5 +400,5 @@ * @return Current value of specified DMMU TLB Tag Read Register. */ -static inline uint64_t dtlb_tag_read_read(size_t entry) +NO_TRACE static inline uint64_t dtlb_tag_read_read(size_t entry) { dtlb_tag_read_addr_t tag; @@ -419,5 +420,5 @@ * Register. */ -static inline uint64_t itlb_data_access_read(int tlb, size_t entry) +NO_TRACE static inline uint64_t itlb_data_access_read(int tlb, size_t entry) { itlb_data_access_addr_t reg; @@ -434,5 +435,5 @@ * @param value Value to be written. */ -static inline void itlb_data_access_write(int tlb, size_t entry, +NO_TRACE static inline void itlb_data_access_write(int tlb, size_t entry, uint64_t value) { @@ -454,5 +455,5 @@ * Register. */ -static inline uint64_t dtlb_data_access_read(int tlb, size_t entry) +NO_TRACE static inline uint64_t dtlb_data_access_read(int tlb, size_t entry) { dtlb_data_access_addr_t reg; @@ -470,5 +471,5 @@ * @param value Value to be written. */ -static inline void dtlb_data_access_write(int tlb, size_t entry, +NO_TRACE static inline void dtlb_data_access_write(int tlb, size_t entry, uint64_t value) { @@ -489,5 +490,5 @@ * @return Current value of specified IMMU TLB Tag Read Register. */ -static inline uint64_t itlb_tag_read_read(int tlb, size_t entry) +NO_TRACE static inline uint64_t itlb_tag_read_read(int tlb, size_t entry) { itlb_tag_read_addr_t tag; @@ -506,5 +507,5 @@ * @return Current value of specified DMMU TLB Tag Read Register. */ -static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry) +NO_TRACE static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry) { dtlb_tag_read_addr_t tag; @@ -523,5 +524,5 @@ * @param v Value to be written. */ -static inline void itlb_tag_access_write(uint64_t v) +NO_TRACE static inline void itlb_tag_access_write(uint64_t v) { asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); @@ -533,5 +534,5 @@ * @return Current value of IMMU TLB Tag Access Register. */ -static inline uint64_t itlb_tag_access_read(void) +NO_TRACE static inline uint64_t itlb_tag_access_read(void) { return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); @@ -542,5 +543,5 @@ * @param v Value to be written. */ -static inline void dtlb_tag_access_write(uint64_t v) +NO_TRACE static inline void dtlb_tag_access_write(uint64_t v) { asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); @@ -552,5 +553,5 @@ * @return Current value of DMMU TLB Tag Access Register. */ -static inline uint64_t dtlb_tag_access_read(void) +NO_TRACE static inline uint64_t dtlb_tag_access_read(void) { return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); @@ -562,5 +563,5 @@ * @param v Value to be written. */ -static inline void itlb_data_in_write(uint64_t v) +NO_TRACE static inline void itlb_data_in_write(uint64_t v) { asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); @@ -572,5 +573,5 @@ * @param v Value to be written. */ -static inline void dtlb_data_in_write(uint64_t v) +NO_TRACE static inline void dtlb_data_in_write(uint64_t v) { asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); @@ -582,5 +583,5 @@ * @return Current content of I-SFSR register. */ -static inline uint64_t itlb_sfsr_read(void) +NO_TRACE static inline uint64_t itlb_sfsr_read(void) { return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); @@ -591,5 +592,5 @@ * @param v New value of I-SFSR register. */ -static inline void itlb_sfsr_write(uint64_t v) +NO_TRACE static inline void itlb_sfsr_write(uint64_t v) { asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); @@ -601,5 +602,5 @@ * @return Current content of D-SFSR register. */ -static inline uint64_t dtlb_sfsr_read(void) +NO_TRACE static inline uint64_t dtlb_sfsr_read(void) { return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); @@ -610,5 +611,5 @@ * @param v New value of D-SFSR register. */ -static inline void dtlb_sfsr_write(uint64_t v) +NO_TRACE static inline void dtlb_sfsr_write(uint64_t v) { asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); @@ -620,5 +621,5 @@ * @return Current content of D-SFAR register. */ -static inline uint64_t dtlb_sfar_read(void) +NO_TRACE static inline uint64_t dtlb_sfar_read(void) { return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); @@ -633,5 +634,5 @@ * @param page Address which is on the page to be demapped. */ -static inline void itlb_demap(int type, int context_encoding, uintptr_t page) +NO_TRACE static inline void itlb_demap(int type, int context_encoding, uintptr_t page) { tlb_demap_addr_t da; @@ -659,5 +660,5 @@ * @param page Address which is on the page to be demapped. */ -static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) +NO_TRACE static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) { tlb_demap_addr_t da; Index: kernel/arch/sparc64/include/mm/sun4v/tlb.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4v/tlb.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/include/mm/sun4v/tlb.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -43,5 +43,5 @@ #include -#include +#include #include #include @@ -88,32 +88,32 @@ * @return Current value of Primary Context Register. */ -static inline uint64_t mmu_primary_context_read(void) +NO_TRACE static inline uint64_t mmu_primary_context_read(void) { return asi_u64_read(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG); } - + /** Write MMU Primary Context Register. * * @param v New value of Primary Context Register. */ -static inline void mmu_primary_context_write(uint64_t v) +NO_TRACE static inline void mmu_primary_context_write(uint64_t v) { asi_u64_write(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG, v); } - + /** Read MMU Secondary Context Register. * * @return Current value of Secondary Context Register. */ -static inline uint64_t mmu_secondary_context_read(void) +NO_TRACE static inline uint64_t mmu_secondary_context_read(void) { return asi_u64_read(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG); } - + /** Write MMU Secondary Context Register. * * @param v New value of Secondary Context Register. */ -static inline void mmu_secondary_context_write(uint64_t v) +NO_TRACE static inline void mmu_secondary_context_write(uint64_t v) { asi_u64_write(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG, v); @@ -126,5 +126,5 @@ * @param mmu_flag MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both */ -static inline void mmu_demap_ctx(int context, int mmu_flag) { +NO_TRACE static inline void mmu_demap_ctx(int context, int mmu_flag) { __hypercall_fast4(MMU_DEMAP_CTX, 0, 0, context, mmu_flag); } @@ -137,5 +137,5 @@ * @param mmu_flag MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both */ -static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag) { +NO_TRACE static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag) { __hypercall_fast5(MMU_DEMAP_PAGE, 0, 0, vaddr, context, mmu_flag); } Index: kernel/arch/sparc64/include/mm/tlb.h =================================================================== --- kernel/arch/sparc64/include/mm/tlb.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/include/mm/tlb.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup sparc64mm +/** @addtogroup sparc64mm * @{ */ @@ -36,9 +36,12 @@ #define KERN_sparc64_TLB_H_ +#if defined (SUN4U) -#if defined (SUN4U) #include + #elif defined (SUN4V) + #include + #endif Index: kernel/arch/sparc64/include/sun4u/asm.h =================================================================== --- kernel/arch/sparc64/include/sun4u/asm.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/include/sun4u/asm.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup sparc64 +/** @addtogroup sparc64 * @{ */ @@ -36,22 +36,27 @@ #define KERN_sparc64_sun4u_ASM_H_ -extern uint64_t read_from_ag_g7(void); -extern void write_to_ag_g6(uint64_t val); -extern void write_to_ag_g7(uint64_t val); -extern void write_to_ig_g6(uint64_t val); - +#include /** Read Version Register. * * @return Value of VER register. + * */ -static inline uint64_t ver_read(void) +NO_TRACE static inline uint64_t ver_read(void) { uint64_t v; - asm volatile ("rdpr %%ver, %0\n" : "=r" (v)); + asm volatile ( + "rdpr %%ver, %[v]\n" + : [v] "=r" (v) + ); return v; } + +extern uint64_t read_from_ag_g7(void); +extern void write_to_ag_g6(uint64_t); +extern void write_to_ag_g7(uint64_t); +extern void write_to_ig_g6(uint64_t); #endif Index: kernel/arch/sparc64/include/sun4u/cpu.h =================================================================== --- kernel/arch/sparc64/include/sun4u/cpu.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/include/sun4u/cpu.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -36,19 +36,19 @@ #define KERN_sparc64_sun4u_CPU_H_ -#define MANUF_FUJITSU 0x04 -#define MANUF_ULTRASPARC 0x17 /**< UltraSPARC I, UltraSPARC II */ -#define MANUF_SUN 0x3e +#define MANUF_FUJITSU 0x04 +#define MANUF_ULTRASPARC 0x17 /**< UltraSPARC I, UltraSPARC II */ +#define MANUF_SUN 0x3e -#define IMPL_ULTRASPARCI 0x10 -#define IMPL_ULTRASPARCII 0x11 -#define IMPL_ULTRASPARCII_I 0x12 -#define IMPL_ULTRASPARCII_E 0x13 -#define IMPL_ULTRASPARCIII 0x14 -#define IMPL_ULTRASPARCIII_PLUS 0x15 -#define IMPL_ULTRASPARCIII_I 0x16 -#define IMPL_ULTRASPARCIV 0x18 -#define IMPL_ULTRASPARCIV_PLUS 0x19 +#define IMPL_ULTRASPARCI 0x10 +#define IMPL_ULTRASPARCII 0x11 +#define IMPL_ULTRASPARCII_I 0x12 +#define IMPL_ULTRASPARCII_E 0x13 +#define IMPL_ULTRASPARCIII 0x14 +#define IMPL_ULTRASPARCIII_PLUS 0x15 +#define IMPL_ULTRASPARCIII_I 0x16 +#define IMPL_ULTRASPARCIV 0x18 +#define IMPL_ULTRASPARCIV_PLUS 0x19 -#define IMPL_SPARC64V 0x5 +#define IMPL_SPARC64V 0x5 #ifndef __ASM__ @@ -58,4 +58,5 @@ #include #include +#include #ifdef CONFIG_SMP @@ -64,21 +65,21 @@ typedef struct { - uint32_t mid; /**< Processor ID as read from - UPA_CONFIG/FIREPLANE_CONFIG. */ + uint32_t mid; /**< Processor ID as read from + UPA_CONFIG/FIREPLANE_CONFIG. */ ver_reg_t ver; - uint32_t clock_frequency; /**< Processor frequency in Hz. */ - uint64_t next_tick_cmpr; /**< Next clock interrupt should be - generated when the TICK register - matches this value. */ + uint32_t clock_frequency; /**< Processor frequency in Hz. */ + uint64_t next_tick_cmpr; /**< Next clock interrupt should be + generated when the TICK register + matches this value. */ } cpu_arch_t; - -/** - * Reads the module ID (agent ID/CPUID) of the current CPU. +/** Read the module ID (agent ID/CPUID) of the current CPU. + * */ -static inline uint32_t read_mid(void) +NO_TRACE static inline uint32_t read_mid(void) { uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0); icbus_config = icbus_config >> ICBUS_CONFIG_MID_SHIFT; + #if defined (US) return icbus_config & 0x1f; @@ -91,5 +92,5 @@ } -#endif +#endif #endif Index: kernel/arch/sparc64/include/sun4v/asm.h =================================================================== --- kernel/arch/sparc64/include/sun4v/asm.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/include/sun4v/asm.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup sparc64 +/** @addtogroup sparc64 * @{ */ Index: kernel/arch/sparc64/include/sun4v/cpu.h =================================================================== --- kernel/arch/sparc64/include/sun4v/cpu.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/include/sun4v/cpu.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -37,8 +37,8 @@ /** Maximum number of virtual processors. */ -#define MAX_NUM_STRANDS 64 +#define MAX_NUM_STRANDS 64 /** Maximum number of logical processors in a processor core */ -#define MAX_CORE_STRANDS 8 +#define MAX_CORE_STRANDS 8 #ifndef __ASM__ @@ -59,17 +59,13 @@ typedef struct cpu_arch { - uint64_t id; /**< virtual processor ID */ - uint32_t clock_frequency; /**< Processor frequency in Hz. */ - uint64_t next_tick_cmpr; /**< Next clock interrupt should be - generated when the TICK register - matches this value. */ - exec_unit_t *exec_unit; /**< Physical core. */ - unsigned long proposed_nrdy; /**< Proposed No. of ready threads - so that cores are equally balanced. */ + uint64_t id; /**< virtual processor ID */ + uint32_t clock_frequency; /**< Processor frequency in Hz. */ + uint64_t next_tick_cmpr; /**< Next clock interrupt should be + generated when the TICK register + matches this value. */ + exec_unit_t *exec_unit; /**< Physical core. */ + unsigned long proposed_nrdy; /**< Proposed No. of ready threads + so that cores are equally balanced. */ } cpu_arch_t; - -#endif - -#ifdef __ASM__ #endif Index: kernel/arch/sparc64/include/types.h =================================================================== --- kernel/arch/sparc64/include/types.h (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/include/types.h (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -52,9 +52,9 @@ typedef uint8_t asi_t; -/**< Formats for uintptr_t, size_t */ +/** Formats for uintptr_t, size_t */ #define PRIp "llx" #define PRIs "llu" -/**< Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */ +/** Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */ #define PRId8 "d" #define PRId16 "d" Index: kernel/arch/sparc64/src/asm.S =================================================================== --- kernel/arch/sparc64/src/asm.S (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/src/asm.S (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -1,29 +1,29 @@ -# -# Copyright (c) 2005 Jakub Jermar -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ #include @@ -32,6 +32,6 @@ .text -.register %g2, #scratch -.register %g3, #scratch +.register %g2, #scratch +.register %g3, #scratch /* @@ -40,58 +40,72 @@ .global memcpy memcpy: - mov %o0, %o3 ! save dst - add %o1, 7, %g1 - and %g1, -8, %g1 - cmp %o1, %g1 - be,pn %xcc, 3f - add %o0, 7, %g1 - mov 0, %g3 -0: - brz,pn %o2, 2f - mov 0, %g2 -1: - ldub [%g3 + %o1], %g1 - add %g2, 1, %g2 - cmp %o2, %g2 - stb %g1, [%g3 + %o0] - bne,pt %xcc, 1b - mov %g2, %g3 -2: - jmp %o7 + 8 ! exit point - mov %o3, %o0 -3: - and %g1, -8, %g1 - cmp %o0, %g1 - bne,pt %xcc, 0b - mov 0, %g3 - srlx %o2, 3, %g4 - brz,pn %g4, 5f - mov 0, %g5 -4: - sllx %g3, 3, %g2 - add %g5, 1, %g3 - ldx [%o1 + %g2], %g1 - mov %g3, %g5 - cmp %g4, %g3 - bne,pt %xcc, 4b - stx %g1, [%o0 + %g2] -5: - and %o2, 7, %o2 - brz,pn %o2, 2b - sllx %g4, 3, %g1 - mov 0, %g2 - add %g1, %o0, %o0 - add %g1, %o1, %g4 - mov 0, %g3 -6: - ldub [%g2 + %g4], %g1 - stb %g1, [%g2 + %o0] - add %g3, 1, %g2 - cmp %o2, %g2 - bne,pt %xcc, 6b - mov %g2, %g3 - - jmp %o7 + 8 ! exit point - mov %o3, %o0 + mov %o0, %o3 /* save dst */ + add %o1, 7, %g1 + and %g1, -8, %g1 + cmp %o1, %g1 + be,pn %xcc, 3f + add %o0, 7, %g1 + mov 0, %g3 + + 0: + + brz,pn %o2, 2f + mov 0, %g2 + + 1: + + ldub [%g3 + %o1], %g1 + add %g2, 1, %g2 + cmp %o2, %g2 + stb %g1, [%g3 + %o0] + bne,pt %xcc, 1b + mov %g2, %g3 + + 2: + + jmp %o7 + 8 /* exit point */ + mov %o3, %o0 + + 3: + + and %g1, -8, %g1 + cmp %o0, %g1 + bne,pt %xcc, 0b + mov 0, %g3 + srlx %o2, 3, %g4 + brz,pn %g4, 5f + mov 0, %g5 + + 4: + + sllx %g3, 3, %g2 + add %g5, 1, %g3 + ldx [%o1 + %g2], %g1 + mov %g3, %g5 + cmp %g4, %g3 + bne,pt %xcc, 4b + stx %g1, [%o0 + %g2] + + 5: + + and %o2, 7, %o2 + brz,pn %o2, 2b + sllx %g4, 3, %g1 + mov 0, %g2 + add %g1, %o0, %o0 + add %g1, %o1, %g4 + mov 0, %g3 + + 6: + + ldub [%g2 + %g4], %g1 + stb %g1, [%g2 + %o0] + add %g3, 1, %g2 + cmp %o2, %g2 + bne,pt %xcc, 6b + mov %g2, %g3 + + jmp %o7 + 8 /* exit point */ + mov %o3, %o0 /* @@ -100,58 +114,72 @@ .global memcpy_from_uspace memcpy_from_uspace: - mov %o0, %o3 ! save dst - add %o1, 7, %g1 - and %g1, -8, %g1 - cmp %o1, %g1 - be,pn %xcc, 3f - add %o0, 7, %g1 - mov 0, %g3 -0: - brz,pn %o2, 2f - mov 0, %g2 -1: - lduba [%g3 + %o1] ASI_AIUS, %g1 - add %g2, 1, %g2 - cmp %o2, %g2 - stb %g1, [%g3 + %o0] - bne,pt %xcc, 1b - mov %g2, %g3 -2: - jmp %o7 + 8 ! exit point - mov %o3, %o0 -3: - and %g1, -8, %g1 - cmp %o0, %g1 - bne,pt %xcc, 0b - mov 0, %g3 - srlx %o2, 3, %g4 - brz,pn %g4, 5f - mov 0, %g5 -4: - sllx %g3, 3, %g2 - add %g5, 1, %g3 - ldxa [%o1 + %g2] ASI_AIUS, %g1 - mov %g3, %g5 - cmp %g4, %g3 - bne,pt %xcc, 4b - stx %g1, [%o0 + %g2] -5: - and %o2, 7, %o2 - brz,pn %o2, 2b - sllx %g4, 3, %g1 - mov 0, %g2 - add %g1, %o0, %o0 - add %g1, %o1, %g4 - mov 0, %g3 -6: - lduba [%g2 + %g4] ASI_AIUS, %g1 - stb %g1, [%g2 + %o0] - add %g3, 1, %g2 - cmp %o2, %g2 - bne,pt %xcc, 6b - mov %g2, %g3 - - jmp %o7 + 8 ! exit point - mov %o3, %o0 + mov %o0, %o3 /* save dst */ + add %o1, 7, %g1 + and %g1, -8, %g1 + cmp %o1, %g1 + be,pn %xcc, 3f + add %o0, 7, %g1 + mov 0, %g3 + + 0: + + brz,pn %o2, 2f + mov 0, %g2 + + 1: + + lduba [%g3 + %o1] ASI_AIUS, %g1 + add %g2, 1, %g2 + cmp %o2, %g2 + stb %g1, [%g3 + %o0] + bne,pt %xcc, 1b + mov %g2, %g3 + + 2: + + jmp %o7 + 8 /* exit point */ + mov %o3, %o0 + + 3: + + and %g1, -8, %g1 + cmp %o0, %g1 + bne,pt %xcc, 0b + mov 0, %g3 + srlx %o2, 3, %g4 + brz,pn %g4, 5f + mov 0, %g5 + + 4: + + sllx %g3, 3, %g2 + add %g5, 1, %g3 + ldxa [%o1 + %g2] ASI_AIUS, %g1 + mov %g3, %g5 + cmp %g4, %g3 + bne,pt %xcc, 4b + stx %g1, [%o0 + %g2] + + 5: + + and %o2, 7, %o2 + brz,pn %o2, 2b + sllx %g4, 3, %g1 + mov 0, %g2 + add %g1, %o0, %o0 + add %g1, %o1, %g4 + mov 0, %g3 + + 6: + + lduba [%g2 + %g4] ASI_AIUS, %g1 + stb %g1, [%g2 + %o0] + add %g3, 1, %g2 + cmp %o2, %g2 + bne,pt %xcc, 6b + mov %g2, %g3 + + jmp %o7 + 8 /* exit point */ + mov %o3, %o0 /* @@ -160,58 +188,72 @@ .global memcpy_to_uspace memcpy_to_uspace: - mov %o0, %o3 ! save dst - add %o1, 7, %g1 - and %g1, -8, %g1 - cmp %o1, %g1 - be,pn %xcc, 3f - add %o0, 7, %g1 - mov 0, %g3 -0: - brz,pn %o2, 2f - mov 0, %g2 -1: - ldub [%g3 + %o1], %g1 - add %g2, 1, %g2 - cmp %o2, %g2 - stba %g1, [%g3 + %o0] ASI_AIUS - bne,pt %xcc, 1b - mov %g2, %g3 -2: - jmp %o7 + 8 ! exit point - mov %o3, %o0 -3: - and %g1, -8, %g1 - cmp %o0, %g1 - bne,pt %xcc, 0b - mov 0, %g3 - srlx %o2, 3, %g4 - brz,pn %g4, 5f - mov 0, %g5 -4: - sllx %g3, 3, %g2 - add %g5, 1, %g3 - ldx [%o1 + %g2], %g1 - mov %g3, %g5 - cmp %g4, %g3 - bne,pt %xcc, 4b - stxa %g1, [%o0 + %g2] ASI_AIUS -5: - and %o2, 7, %o2 - brz,pn %o2, 2b - sllx %g4, 3, %g1 - mov 0, %g2 - add %g1, %o0, %o0 - add %g1, %o1, %g4 - mov 0, %g3 -6: - ldub [%g2 + %g4], %g1 - stba %g1, [%g2 + %o0] ASI_AIUS - add %g3, 1, %g2 - cmp %o2, %g2 - bne,pt %xcc, 6b - mov %g2, %g3 - - jmp %o7 + 8 ! exit point - mov %o3, %o0 + mov %o0, %o3 /* save dst */ + add %o1, 7, %g1 + and %g1, -8, %g1 + cmp %o1, %g1 + be,pn %xcc, 3f + add %o0, 7, %g1 + mov 0, %g3 + + 0: + + brz,pn %o2, 2f + mov 0, %g2 + + 1: + + ldub [%g3 + %o1], %g1 + add %g2, 1, %g2 + cmp %o2, %g2 + stba %g1, [%g3 + %o0] ASI_AIUS + bne,pt %xcc, 1b + mov %g2, %g3 + + 2: + + jmp %o7 + 8 /* exit point */ + mov %o3, %o0 + + 3: + + and %g1, -8, %g1 + cmp %o0, %g1 + bne,pt %xcc, 0b + mov 0, %g3 + srlx %o2, 3, %g4 + brz,pn %g4, 5f + mov 0, %g5 + + 4: + + sllx %g3, 3, %g2 + add %g5, 1, %g3 + ldx [%o1 + %g2], %g1 + mov %g3, %g5 + cmp %g4, %g3 + bne,pt %xcc, 4b + stxa %g1, [%o0 + %g2] ASI_AIUS + + 5: + + and %o2, 7, %o2 + brz,pn %o2, 2b + sllx %g4, 3, %g1 + mov 0, %g2 + add %g1, %o0, %o0 + add %g1, %o1, %g4 + mov 0, %g3 + + 6: + + ldub [%g2 + %g4], %g1 + stba %g1, [%g2 + %o0] ASI_AIUS + add %g3, 1, %g2 + cmp %o2, %g2 + bne,pt %xcc, 6b + mov %g2, %g3 + + jmp %o7 + 8 /* exit point */ + mov %o3, %o0 .global memcpy_from_uspace_failover_address @@ -219,6 +261,6 @@ memcpy_from_uspace_failover_address: memcpy_to_uspace_failover_address: - jmp %o7 + 8 ! exit point - mov %g0, %o0 ! return 0 on failure + jmp %o7 + 8 /* exit point */ + mov %g0, %o0 /* return 0 on failure */ .global memsetb @@ -232,2 +274,6 @@ nop +.global early_putchar +early_putchar: + retl + nop Index: kernel/arch/sparc64/src/mm/sun4u/frame.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4u/frame.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/src/mm/sun4u/frame.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -49,27 +49,30 @@ void frame_arch_init(void) { - unsigned int i; - pfn_t confdata; - if (config.cpu_active == 1) { + unsigned int i; + for (i = 0; i < memmap.cnt; i++) { - uintptr_t start = (uintptr_t) memmap.zones[i].start; - size_t size = memmap.zones[i].size; - + /* To be safe, make the available zone possibly smaller */ + uintptr_t new_start = ALIGN_UP((uintptr_t) memmap.zones[i].start, + FRAME_SIZE); + size_t new_size = ALIGN_DOWN(memmap.zones[i].size - + (new_start - ((uintptr_t) memmap.zones[i].start)), FRAME_SIZE); + /* * The memmap is created by HelenOS boot loader. * It already contains no holes. */ - - confdata = ADDR2PFN(start); + + pfn_t confdata = ADDR2PFN(new_start); + if (confdata == ADDR2PFN(KA2PA(PFN2ADDR(0)))) confdata = ADDR2PFN(KA2PA(PFN2ADDR(2))); - zone_create(ADDR2PFN(start), - SIZE2FRAMES(ALIGN_DOWN(size, FRAME_SIZE)), + + zone_create(ADDR2PFN(new_start), SIZE2FRAMES(new_size), confdata, 0); - last_frame = max(last_frame, start + ALIGN_UP(size, - FRAME_SIZE)); + + last_frame = max(last_frame, new_start + new_size); } - + /* * On sparc64, physical memory can start on a non-zero address. @@ -80,5 +83,5 @@ frame_mark_unavailable(ADDR2PFN(KA2PA(PFN2ADDR(0))), 1); } - + end_of_identity = PA2KA(last_frame); } Index: kernel/arch/sparc64/src/mm/sun4u/tlb.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4u/tlb.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/src/mm/sun4u/tlb.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -27,5 +27,5 @@ */ -/** @addtogroup sparc64mm +/** @addtogroup sparc64mm * @{ */ @@ -58,5 +58,6 @@ static void dtlb_pte_copy(pte_t *, size_t, bool); static void itlb_pte_copy(pte_t *, size_t); -static void do_fast_instruction_access_mmu_miss_fault(istate_t *, const char *); +static void do_fast_instruction_access_mmu_miss_fault(istate_t *, uintptr_t, + const char *); static void do_fast_data_access_mmu_miss_fault(istate_t *, tlb_tag_access_reg_t, const char *); @@ -222,10 +223,10 @@ * Forward the page fault to the address space page fault * handler. - */ + */ page_table_unlock(AS, true); if (as_page_fault(page_16k, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { do_fast_instruction_access_mmu_miss_fault(istate, - __func__); + istate->tpc, __func__); } } @@ -258,5 +259,5 @@ /* NULL access in kernel */ do_fast_data_access_mmu_miss_fault(istate, tag, - __func__); + "Dereferencing NULL pointer"); } else if (page_8k >= end_of_identity) { /* @@ -438,9 +439,8 @@ void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, - const char *str) -{ - fault_if_from_uspace(istate, "%s.", str); - dump_istate(istate); - panic("%s.", str); + uintptr_t va, const char *str) +{ + fault_if_from_uspace(istate, "%s, Address=%p.", str, va); + panic_memtrap(istate, PF_ACCESS_EXEC, va, "%s.", str); } @@ -451,11 +451,7 @@ va = tag.vpn << MMU_PAGE_WIDTH; - if (tag.context) { - fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va, - tag.context); - } - dump_istate(istate); - printf("Faulting page: %p, ASID=%d.\n", va, tag.context); - panic("%s.", str); + fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va, + tag.context); + panic_memtrap(istate, PF_ACCESS_READ, va, "%s.", str); } @@ -466,12 +462,7 @@ va = tag.vpn << MMU_PAGE_WIDTH; - - if (tag.context) { - fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va, - tag.context); - } - printf("Faulting page: %p, ASID=%d\n", va, tag.context); - dump_istate(istate); - panic("%s.", str); + fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va, + tag.context); + panic_memtrap(istate, PF_ACCESS_WRITE, va, "%s.", str); } Index: kernel/arch/sparc64/src/mm/sun4v/frame.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4v/frame.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/src/mm/sun4v/frame.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -47,25 +47,28 @@ void frame_arch_init(void) { - unsigned int i; - pfn_t confdata; - if (config.cpu_active == 1) { + unsigned int i; + for (i = 0; i < memmap.cnt; i++) { - uintptr_t start = (uintptr_t) memmap.zones[i].start; - size_t size = memmap.zones[i].size; - + /* To be safe, make the available zone possibly smaller */ + uintptr_t new_start = ALIGN_UP((uintptr_t) memmap.zones[i].start, + FRAME_SIZE); + size_t new_size = ALIGN_DOWN(memmap.zones[i].size - + (new_start - ((uintptr_t) memmap.zones[i].start)), FRAME_SIZE); + /* * The memmap is created by HelenOS boot loader. * It already contains no holes. */ - - confdata = ADDR2PFN(start); + + pfn_t confdata = ADDR2PFN(new_start); + if (confdata == ADDR2PFN(KA2PA(PFN2ADDR(0)))) confdata = ADDR2PFN(KA2PA(PFN2ADDR(2))); - zone_create(ADDR2PFN(start), - SIZE2FRAMES(ALIGN_DOWN(size, FRAME_SIZE)), + + zone_create(ADDR2PFN(new_start), SIZE2FRAMES(new_size), confdata, 0); } - + /* * On sparc64, physical memory can start on a non-zero address. Index: kernel/arch/sparc64/src/mm/sun4v/tlb.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4v/tlb.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/src/mm/sun4v/tlb.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -28,5 +28,5 @@ */ -/** @addtogroup sparc64mm +/** @addtogroup sparc64mm * @{ */ @@ -62,5 +62,6 @@ static void itlb_pte_copy(pte_t *); static void dtlb_pte_copy(pte_t *, bool); -static void do_fast_instruction_access_mmu_miss_fault(istate_t *, const char *); +static void do_fast_instruction_access_mmu_miss_fault(istate_t *, uintptr_t, + const char *); static void do_fast_data_access_mmu_miss_fault(istate_t *, uint64_t, const char *); @@ -235,9 +236,9 @@ * Forward the page fault to the address space page fault * handler. - */ + */ page_table_unlock(AS, true); if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { do_fast_instruction_access_mmu_miss_fault(istate, - __func__); + istate->tpc, __func__); } } @@ -354,10 +355,9 @@ } -void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, +void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, uintptr_t va, const char *str) { - fault_if_from_uspace(istate, "%s.", str); - dump_istate(istate); - panic("%s.", str); + fault_if_from_uspace(istate, "%s, Address=%p.", str, va); + panic_memtrap(istate, PF_ACCESS_EXEC, va, "%s.", str); } @@ -365,11 +365,8 @@ uint64_t page_and_ctx, const char *str) { - if (DMISS_CONTEXT(page_and_ctx)) { - fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, DMISS_ADDRESS(page_and_ctx), - DMISS_CONTEXT(page_and_ctx)); - } - dump_istate(istate); - printf("Faulting page: %p, ASID=%d\n", DMISS_ADDRESS(page_and_ctx), DMISS_CONTEXT(page_and_ctx)); - panic("%s\n", str); + fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, + DMISS_ADDRESS(page_and_ctx), DMISS_CONTEXT(page_and_ctx)); + panic_memtrap(istate, PF_ACCESS_READ, DMISS_ADDRESS(page_and_ctx), + "%s."); } @@ -377,11 +374,8 @@ uint64_t page_and_ctx, const char *str) { - if (DMISS_CONTEXT(page_and_ctx)) { - fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, DMISS_ADDRESS(page_and_ctx), - DMISS_CONTEXT(page_and_ctx)); - } - printf("Faulting page: %p, ASID=%d\n", DMISS_ADDRESS(page_and_ctx), DMISS_CONTEXT(page_and_ctx)); - dump_istate(istate); - panic("%s\n", str); + fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, + DMISS_ADDRESS(page_and_ctx), DMISS_CONTEXT(page_and_ctx)); + panic_memtrap(istate, PF_ACCESS_WRITE, DMISS_ADDRESS(page_and_ctx), + "%s."); } Index: kernel/arch/sparc64/src/panic.S =================================================================== --- kernel/arch/sparc64/src/panic.S (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ (revision ) @@ -1,40 +1,0 @@ -# -# Copyright (c) 2005 Jakub Jermar -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -.text - -#include - -.global panic_printf -panic_printf: - call printf - nop - call halt - nop - /* Not reached. */ - Index: kernel/arch/sparc64/src/trap/exception.c =================================================================== --- kernel/arch/sparc64/src/trap/exception.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/src/trap/exception.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -44,5 +44,5 @@ #include -void dump_istate(istate_t *istate) +void istate_decode(istate_t *istate) { const char *tpcs = symtab_fmt_name_lookup(istate->tpc); @@ -58,6 +58,5 @@ { fault_if_from_uspace(istate, "%s.", __func__); - dump_istate(istate); - panic("%s.", __func__); + panic_badtrap(istate, n, "%s.", __func__); } @@ -66,6 +65,5 @@ { fault_if_from_uspace(istate, "%s.", __func__); - dump_istate(istate); - panic("%s.", __func__); + panic_badtrap(istate, n, "%s.", __func__); } @@ -74,6 +72,5 @@ { fault_if_from_uspace(istate, "%s.", __func__); - dump_istate(istate); - panic("%s.", __func__); + panic_badtrap(istate, n, "%s.", __func__); } @@ -82,6 +79,5 @@ { fault_if_from_uspace(istate, "%s.", __func__); - dump_istate(istate); - panic("%s.", __func__); + panic_badtrap(istate, n, "%s.", __func__); } @@ -90,6 +86,5 @@ { fault_if_from_uspace(istate, "%s.", __func__); - dump_istate(istate); - panic("%s.", __func__); + panic_badtrap(istate, n, "%s.", __func__); } @@ -98,6 +93,5 @@ { fault_if_from_uspace(istate, "%s.", __func__); - dump_istate(istate); - panic("%s.", __func__); + panic_badtrap(istate, n, "%s.", __func__); } @@ -118,6 +112,5 @@ #else fault_if_from_uspace(istate, "%s.", __func__); - dump_istate(istate); - panic("%s.", __func__); + panic_badtrap(istate, n, "%s.", __func__); #endif } @@ -127,6 +120,5 @@ { fault_if_from_uspace(istate, "%s.", __func__); - dump_istate(istate); - panic("%s.", __func__); + panic_badtrap(istate, n, "%s.", __func__); } @@ -135,6 +127,5 @@ { fault_if_from_uspace(istate, "%s.", __func__); - dump_istate(istate); - panic("%s.", __func__); + panic_badtrap(istate, n, "%s.", __func__); } @@ -143,6 +134,5 @@ { fault_if_from_uspace(istate, "%s.", __func__); - dump_istate(istate); - panic("%s.", __func__); + panic_badtrap(istate, n, "%s.", __func__); } @@ -151,6 +141,5 @@ { fault_if_from_uspace(istate, "%s.", __func__); - dump_istate(istate); - panic("%s.", __func__); + panic_badtrap(istate, n, "%s.", __func__); } @@ -159,7 +148,5 @@ { fault_if_from_uspace(istate, "%s.", __func__); - dump_istate(istate); - describe_dmmu_fault(); - panic("%s.", __func__); + panic_badtrap(istate, n, "%s.", __func__); } @@ -168,6 +155,5 @@ { fault_if_from_uspace(istate, "%s.", __func__); - dump_istate(istate); - panic("%s.", __func__); + panic_badtrap(istate, n, "%s.", __func__); } @@ -176,6 +162,5 @@ { fault_if_from_uspace(istate, "%s.", __func__); - dump_istate(istate); - panic("%s.", __func__); + panic_badtrap(istate, n, "%s.", __func__); } @@ -184,6 +169,5 @@ { fault_if_from_uspace(istate, "%s.", __func__); - dump_istate(istate); - panic("%s.", __func__); + panic_badtrap(istate, n, "%s.", __func__); } @@ -192,6 +176,5 @@ { fault_if_from_uspace(istate, "%s.", __func__); - dump_istate(istate); - panic("%s.", __func__); + panic_badtrap(istate, n, "%s.", __func__); } @@ -200,6 +183,5 @@ { fault_if_from_uspace(istate, "%s.", __func__); - dump_istate(istate); - panic("%s.", __func__); + panic_badtrap(istate, n, "%s.", __func__); } @@ -208,6 +190,5 @@ { fault_if_from_uspace(istate, "%s.", __func__); - dump_istate(istate); - panic("%s.", __func__); + panic_badtrap(istate, n, "%s.", __func__); } @@ -216,6 +197,5 @@ { fault_if_from_uspace(istate, "%s.", __func__); - dump_istate(istate); - panic("%s.", __func__); + panic_badtrap(istate, n, "%s.", __func__); } Index: kernel/arch/sparc64/src/trap/sun4v/interrupt.c =================================================================== --- kernel/arch/sparc64/src/trap/sun4v/interrupt.c (revision 9e19672e604500bd1dcbfa4a5b950669c4f79b13) +++ kernel/arch/sparc64/src/trap/sun4v/interrupt.c (revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2) @@ -111,5 +111,5 @@ ((void (*)(void)) data1)(); } else { - printf("Spurious interrupt on %d, data = %lx.\n", + printf("Spurious interrupt on %d, data = %" PRIx64 ".\n", CPU->arch.id, data1); }