Index: kernel/arch/arm32/include/mm/page.h
===================================================================
--- kernel/arch/arm32/include/mm/page.h	(revision c09adc10434b7de65842eae8fc63537922e8c7d6)
+++ kernel/arch/arm32/include/mm/page.h	(revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup arm32mm	
+/** @addtogroup arm32mm
  * @{
  */
@@ -40,4 +40,5 @@
 #include <mm/mm.h>
 #include <arch/exception.h>
+#include <trace.h>
 
 #define PAGE_WIDTH	FRAME_WIDTH
@@ -192,7 +193,8 @@
 /** Sets the address of level 0 page table.
  *
- * @param pt    Pointer to the page table to set.
- */   
-static inline void set_ptl0_addr(pte_t *pt)
+ * @param pt Pointer to the page table to set.
+ *
+ */
+NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
 {
 	asm volatile (
@@ -205,12 +207,13 @@
 /** Returns level 0 page table entry flags.
  *
- *  @param pt     Level 0 page table.
- *  @param i      Index of the entry to return.
- */
-static inline int get_pt_level0_flags(pte_t *pt, size_t i)
+ * @param pt Level 0 page table.
+ * @param i  Index of the entry to return.
+ *
+ */
+NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i)
 {
 	pte_level0_t *p = &pt[i].l0;
 	int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT);
-
+	
 	return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) |
 	    (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) |
@@ -220,14 +223,15 @@
 /** Returns level 1 page table entry flags.
  *
- *  @param pt     Level 1 page table.
- *  @param i      Index of the entry to return.
- */
-static inline int get_pt_level1_flags(pte_t *pt, size_t i)
+ * @param pt Level 1 page table.
+ * @param i  Index of the entry to return.
+ *
+ */
+NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i)
 {
 	pte_level1_t *p = &pt[i].l1;
-
+	
 	int dt = p->descriptor_type;
 	int ap = p->access_permission_0;
-
+	
 	return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) |
 	    ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) |
@@ -241,15 +245,15 @@
 }
 
-
 /** Sets flags of level 0 page table entry.
  *
- *  @param pt     level 0 page table
- *  @param i      index of the entry to be changed
- *  @param flags  new flags
- */
-static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
+ * @param pt    level 0 page table
+ * @param i     index of the entry to be changed
+ * @param flags new flags
+ *
+ */
+NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
 {
 	pte_level0_t *p = &pt[i].l0;
-
+	
 	if (flags & PAGE_NOT_PRESENT) {
 		p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
@@ -262,5 +266,5 @@
 		p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
 		p->should_be_zero = 0;
-    }
+	}
 }
 
@@ -268,13 +272,14 @@
 /** Sets flags of level 1 page table entry.
  *
- *  We use same access rights for the whole page. When page is not preset we
- *  store 1 in acess_rigts_3 so that at least one bit is 1 (to mark correct
- *  page entry, see #PAGE_VALID_ARCH).
- *
- *  @param pt     Level 1 page table.
- *  @param i      Index of the entry to be changed.
- *  @param flags  New flags.
- */  
-static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
+ * We use same access rights for the whole page. When page
+ * is not preset we store 1 in acess_rigts_3 so that at least
+ * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH).
+ *
+ * @param pt    Level 1 page table.
+ * @param i     Index of the entry to be changed.
+ * @param flags New flags.
+ *
+ */
+NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
 {
 	pte_level1_t *p = &pt[i].l1;
@@ -287,12 +292,12 @@
 		p->access_permission_3 = p->access_permission_0;
 	}
-  
+	
 	p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
-
+	
 	/* default access permission */
 	p->access_permission_0 = p->access_permission_1 = 
 	    p->access_permission_2 = p->access_permission_3 =
 	    PTE_AP_USER_NO_KERNEL_RW;
-
+	
 	if (flags & PAGE_USER)  {
 		if (flags & PAGE_READ) {
