Index: kernel/arch/amd64/include/asm.h
===================================================================
--- kernel/arch/amd64/include/asm.h	(revision 3d6beaa35f8c97b40779781a9022e244474c064e)
+++ kernel/arch/amd64/include/asm.h	(revision bd48f4ce0bcae08987a78c5940f9588ac0feddb2)
@@ -39,7 +39,5 @@
 #include <typedefs.h>
 #include <arch/cpu.h>
-
-extern void asm_delay_loop(uint32_t t);
-extern void asm_fake_loop(uint32_t t);
+#include <trace.h>
 
 /** Return base address of current stack.
@@ -50,5 +48,5 @@
  *
  */
-static inline uintptr_t get_stack_base(void)
+NO_TRACE static inline uintptr_t get_stack_base(void)
 {
 	uintptr_t v;
@@ -57,5 +55,5 @@
 		"andq %%rsp, %[v]\n"
 		: [v] "=r" (v)
-		: "0" (~((uint64_t) STACK_SIZE-1))
+		: "0" (~((uint64_t) STACK_SIZE - 1))
 	);
 	
@@ -63,10 +61,12 @@
 }
 
-static inline void cpu_sleep(void)
-{
-	asm volatile ("hlt\n");
-}
-
-static inline void __attribute__((noreturn)) cpu_halt(void)
+NO_TRACE static inline void cpu_sleep(void)
+{
+	asm volatile (
+		"hlt\n"
+	);
+}
+
+NO_TRACE static inline void __attribute__((noreturn)) cpu_halt(void)
 {
 	while (true) {
@@ -77,5 +77,4 @@
 }
 
-
 /** Byte from port
  *
@@ -86,5 +85,5 @@
  *
  */
-static inline uint8_t pio_read_8(ioport8_t *port)
+NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
 {
 	uint8_t val;
@@ -107,5 +106,5 @@
  *
  */
-static inline uint16_t pio_read_16(ioport16_t *port)
+NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
 {
 	uint16_t val;
@@ -128,5 +127,5 @@
  *
  */
-static inline uint32_t pio_read_32(ioport32_t *port)
+NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
 {
 	uint32_t val;
@@ -149,9 +148,10 @@
  *
  */
-static inline void pio_write_8(ioport8_t *port, uint8_t val)
+NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
 {
 	asm volatile (
 		"outb %b[val], %w[port]\n"
-		:: [val] "a" (val), [port] "d" (port)
+		:: [val] "a" (val),
+		   [port] "d" (port)
 	);
 }
@@ -165,9 +165,10 @@
  *
  */
-static inline void pio_write_16(ioport16_t *port, uint16_t val)
+NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
 {
 	asm volatile (
 		"outw %w[val], %w[port]\n"
-		:: [val] "a" (val), [port] "d" (port)
+		:: [val] "a" (val),
+		   [port] "d" (port)
 	);
 }
@@ -181,16 +182,19 @@
  *
  */
-static inline void pio_write_32(ioport32_t *port, uint32_t val)
+NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
 {
 	asm volatile (
 		"outl %[val], %w[port]\n"
-		:: [val] "a" (val), [port] "d" (port)
+		:: [val] "a" (val),
+		   [port] "d" (port)
 	);
 }
 
 /** Swap Hidden part of GS register with visible one */
-static inline void swapgs(void)
-{
-	asm volatile("swapgs");
+NO_TRACE static inline void swapgs(void)
+{
+	asm volatile (
+		"swapgs"
+	);
 }
 
@@ -203,5 +207,5 @@
  *
  */
-static inline ipl_t interrupts_enable(void) {
+NO_TRACE static inline ipl_t interrupts_enable(void) {
 	ipl_t v;
 	
@@ -224,5 +228,5 @@
  *
  */
-static inline ipl_t interrupts_disable(void) {
+NO_TRACE static inline ipl_t interrupts_disable(void) {
 	ipl_t v;
 	
@@ -244,5 +248,5 @@
  *
  */
-static inline void interrupts_restore(ipl_t ipl) {
+NO_TRACE static inline void interrupts_restore(ipl_t ipl) {
 	asm volatile (
 		"pushq %[ipl]\n"
@@ -259,5 +263,5 @@
  *
  */
-static inline ipl_t interrupts_read(void) {
+NO_TRACE static inline ipl_t interrupts_read(void) {
 	ipl_t v;
 	
@@ -276,5 +280,5 @@
  *
  */
-static inline bool interrupts_disabled(void)
+NO_TRACE static inline bool interrupts_disabled(void)
 {
 	ipl_t v;
@@ -289,7 +293,6 @@
 }
 
-
 /** Write to MSR */
-static inline void write_msr(uint32_t msr, uint64_t value)
+NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value)
 {
 	asm volatile (
@@ -301,5 +304,5 @@
 }
 
-static inline unative_t read_msr(uint32_t msr)
+NO_TRACE static inline unative_t read_msr(uint32_t msr)
 {
 	uint32_t ax, dx;
@@ -314,5 +317,4 @@
 }
 
-
 /** Enable local APIC
  *
@@ -320,5 +322,5 @@
  *
  */
-static inline void enable_l_apic_in_msr()
+NO_TRACE static inline void enable_l_apic_in_msr()
 {
 	asm volatile (
@@ -328,5 +330,5 @@
 		"orl $(0xfee00000),%%eax\n"
 		"wrmsr\n"
-		::: "%eax","%ecx","%edx"
+		::: "%eax", "%ecx", "%edx"
 	);
 }
@@ -337,5 +339,5 @@
  *
  */
-static inline void invlpg(uintptr_t addr)
+NO_TRACE static inline void invlpg(uintptr_t addr)
 {
 	asm volatile (
@@ -350,5 +352,5 @@
  *
  */
-static inline void gdtr_load(ptr_16_64_t *gdtr_reg)
+NO_TRACE static inline void gdtr_load(ptr_16_64_t *gdtr_reg)
 {
 	asm volatile (
@@ -363,5 +365,5 @@
  *
  */
-static inline void gdtr_store(ptr_16_64_t *gdtr_reg)
+NO_TRACE static inline void gdtr_store(ptr_16_64_t *gdtr_reg)
 {
 	asm volatile (
@@ -376,5 +378,5 @@
  *
  */
-static inline void idtr_load(ptr_16_64_t *idtr_reg)
+NO_TRACE static inline void idtr_load(ptr_16_64_t *idtr_reg)
 {
 	asm volatile (
@@ -388,5 +390,5 @@
  *
  */
-static inline void tr_load(uint16_t sel)
+NO_TRACE static inline void tr_load(uint16_t sel)
 {
 	asm volatile (
@@ -396,5 +398,5 @@
 }
 
-#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
+#define GEN_READ_REG(reg) NO_TRACE static inline unative_t read_ ##reg (void) \
 	{ \
 		unative_t res; \
@@ -406,5 +408,5 @@
 	}
 
-#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
+#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (unative_t regn) \
 	{ \
 		asm volatile ( \
@@ -436,4 +438,7 @@
 extern void interrupt_handlers(void);
 
+extern void asm_delay_loop(uint32_t);
+extern void asm_fake_loop(uint32_t);
+
 #endif
 
