Index: arch/ppc32/loader/asm.S
===================================================================
--- arch/ppc32/loader/asm.S	(revision 5eb84ab5eac9daf9f14f20c74cb2965d9cadb5e1)
+++ arch/ppc32/loader/asm.S	(revision bcc223b2118fdcae4360e3501331c5c216a57266)
@@ -29,4 +29,9 @@
 #include "regname.h"
 #include "spr.h"
+
+.data
+
+flush_buffer:
+	.space 4
 
 .text
@@ -145,4 +150,38 @@
 	b halt
 
+flush_instruction_cache:
+
+	# Flush data cache
+	
+	lis r3, flush_buffer@h
+	ori r3, r3, flush_buffer@l
+	li r4, L1_CACHE_LINES
+	mtctr r4
+	
+	0:
+	
+	lwz r4, 0(r3)
+	addi r3, r3, L1_CACHE_BYTES
+	bdnz 0b
+	
+	# Invalidate instruction cache
+	
+	li r3, 0
+	ori	r3, r3, (HID0_ICE | HID0_DCE | HID0_ICFI | HID0_DCI)
+	mfspr r4, SPRN_HID0
+	or r5, r4, r3
+	isync
+	mtspr SPRN_HID0, r5
+	sync
+	isync
+	
+	# Enable instruction cache
+	
+	ori	r5, r4, HID0_ICE
+	mtspr SPRN_HID0, r5
+	sync
+	isync
+	blr
+
 jump_to_kernel:
 	mfmsr r4
@@ -150,4 +189,4 @@
 	mtspr SPRN_SRR0, r3
 	mtspr SPRN_SRR1, r4
-	sync
-	RFI
+	bl flush_instruction_cache
+	rfi
Index: arch/ppc32/loader/spr.h
===================================================================
--- arch/ppc32/loader/spr.h	(revision 5eb84ab5eac9daf9f14f20c74cb2965d9cadb5e1)
+++ arch/ppc32/loader/spr.h	(revision bcc223b2118fdcae4360e3501331c5c216a57266)
@@ -30,12 +30,18 @@
 #define __SPR_H__
 
-#define MSR_DR (1<<27)
-#define MSR_IR (1<<26)
+#define MSR_DR (1 << 27)
+#define MSR_IR (1 << 26)
 
 #define SPRN_SRR0  0x1a
 #define SPRN_SRR1  0x1b
+#define SPRN_HID0  0x3f0
 
-/* Works for PPC32 */
-#define L1_CACHE_BYTES (1 << 5)
+#define HID0_ICE  (1 << 15)
+#define HID0_DCE  (1 << 14)
+#define HID0_ICFI (1 << 11)
+#define HID0_DCI  (1 << 10)
+
+#define L1_CACHE_LINES (128 * 8)
+#define L1_CACHE_BYTES 5
 
 #endif